PD - 91607B IRLR/U3410 HEXFET® Power MOSFET Logic Level Gate Drive l Ultra Low On-Resistance l Surface Mount (IRLR3410) l Straight Lead (IRLU3410) l Advanced Process Technology l Fast Switching l Fully Avalanche Rated Description l D VDSS = 100V RDS(on) = 0.105Ω G ID = 17A S Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D -P A K T O -2 52 A A I-P A K T O -25 1 A A Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. Units 17 12 60 79 0.53 ± 16 150 9.0 7.9 5.0 -55 to + 175 A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case ) Thermal Resistance Parameter RθJC RθJA RθJA www.irf.com Junction-to-Case Junction-to-Ambient (PCB mount) ** Junction-to-Ambient Typ. Max. Units ––– ––– ––– 1.9 50 110 °C/W 1 5/11/98 IRLR/U3410 Electrical Characteristics @ TJ = 25°C (unless otherwise specified) ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 100 ––– ––– ––– ––– 1.0 7.7 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 0.122 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 7.2 53 30 26 RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current LD Internal Drain Inductance ––– 4.5 LS Internal Source Inductance ––– 7.5 Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance ––– ––– ––– 800 160 90 V(BR)DSS IGSS Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA 0.105 VGS = 10V, ID = 10A 0.125 W VGS = 5.0V, ID = 10A 0.155 VGS = 4.0V, ID = 9.0A 2.0 V VDS = VGS, ID = 250µA ––– S VDS = 25V, ID = 9.0A 25 VDS = 100V, VGS = 0V µA 250 VDS = 80V, VGS = 0V, TJ = 150°C 100 VGS = 16V nA -100 VGS = -16V 34 ID = 9.0A 4.8 nC VDS = 80V 20 VGS = 5.0V, See Fig. 6 and 13 ––– VDD = 50V ––– ID = 9.0A ns ––– RG = 6.0Ω, VGS = 5.0V ––– RD = 5.5Ω, See Fig. 10 Between lead, ––– nH 6mm (0.25in.) G from package ––– and center of die contact ––– VGS = 0V ––– pF VDS = 25V ––– ƒ = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 17 ––– ––– showing the A G integral reverse ––– ––– 60 p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 9.0A, VGS = 0V ––– 140 210 ns TJ = 25°C, IF =9.0A ––– 740 1100 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by Pulse width ≤ 300µs; duty cycle ≤ 2% max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25°C, L = 3.1mH RG = 25Ω, IAS = 9.0A. (See Figure 12) Uses IRL530N data and test conditions ISD ≤ 9.0A, di/dt ≤ 540A/µs, VDD ≤ V(BR)DSS, This is applied for I-PAK, LS of D-PAK is measured between lead and TJ ≤ 175°C center of die contact ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com IRLR/U3410 100 100 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP ID , D rain-to-S ource C urrent (A ) ID , D rain-to-S ource C urrent (A ) TOP 10 1 2.5V 20µ s P U LS E W ID TH T J = 25°C 0.1 0.1 1 10 10 2.5V 1 20µ s P U LS E W ID TH T J = 175°C 0.1 A 0.1 100 3.0 R D S (on ) , D rain-to-S ource O n R esistance (N orm alized) 100 I D , D ra in -to-S o urc e C urren t (A ) T J = 2 5 °C T J = 1 7 5 °C 10 1 V DS = 5 0V 2 0 µ s P U L S E W ID T H 3 4 5 6 7 8 9 V G S , G a te -to -S o u rc e V o lta g e (V ) Fig 3. Typical Transfer Characteristics www.irf.com A 100 Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics 2 10 V D S , D rain-to-S ource V oltage (V ) V D S , D rain-to-S ource V oltage (V ) 0.1 1 10 A I D = 15A 2.5 2.0 1.5 1.0 0.5 V G S = 10V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 180 T J , Junction T em perature (°C ) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRLR/U3410 V GS C iss C rss C oss C , C apacitanc e (pF ) 1200 = = = = 15 0V , f = 1M H z C gs + C gd , C ds S H O R TE D C gd C ds + C gd V G S , G ate-to-S ource V oltage (V ) 1400 C is s 1000 800 600 C os s 400 C rs s 200 0 10 V D S = 8 0V V D S = 5 0V V D S = 2 0V 12 9 6 3 FO R TE S T C IR C U IT S E E FIG U R E 13 0 A 1 I D = 9.0A 100 0 V D S , D rain-to-S ource V oltage (V ) 30 40 A 50 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 O P E R A TIO N IN TH IS A R E A LIM ITE D B Y R D S (on) I D , D rain C urrent (A ) I S D , R everse D rain C urrent (A ) 20 Q G , Total G ate C harge (nC ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage T J = 175°C 10 T J = 25°C V G S = 0V 1 0.4 0.6 0.8 1.0 1.2 V S D , S ource-to-D rain V oltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage 4 10 A 1.4 100 10µ s 10 10 0µ s 1m s T C = 25°C T J = 175°C S ingle P ulse 1 1 10m s 10 100 A 1000 V D S , D rain-to-S ource V oltage (V ) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U3410 20 RD VDS VGS I D , Drain Current (A) 15 D.U.T. RG + -VDD 5.0V 10 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % Fig 10a. Switching Time Test Circuit 5 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( ° C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 P DM 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3410 15V L VDS D .U .T RG IA S 10V tp D R IV E R + V - DD A 0 .0 1 Ω Fig 12a. Unclamped Inductive Test Circuit E A S , S ingle P ulse A valanc he E nergy (m J) 350 TO P 300 B O TTO M ID 3.7A 6.4A 9.0A 250 200 150 100 50 0 V D D = 25V 25 50 A 75 100 125 150 175 S tarting T J , Junc tion T em perature (°C ) V (B R )D S S tp Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform 6 IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRLR/U3410 Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + - - + • • • • RG Driver Gate Drive D= Period P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test - VDD P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U3410 Package Outline TO-252AA Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) 1.14 (.045) 0.89 (.035) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 10.42 (.410) 9.40 (.370) LE A D A S S IG N M E N T S 1 - GATE 3 0.51 (.020) M IN. -B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2 - D R A IN 3 - SOURCE 4 - D R A IN 0.58 (.023) 0.46 (.018) M A M B N O TE S : 1 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982. 2.28 (.090) 4.57 (.180) 2 C O N TR O LLIN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O JE D E C O U TLIN E TO -252A A . 4 D IM E N S IO N S S H O W N A RE B E F O R E S O LD E R D IP , S O LD E R D IP M A X. +0.16 (.006). Part Marking Information TO-252AA (D-PARK) E XA M P L E : TH IS IS A N IR F R 1 20 W IT H A S S E M B LY LOT CODE 9U1P IN TE R N A TIO N A L R E C T IF IE R LO G O A IR F R 1 20 9U A S S E M B LY LOT CODE 8 F IR S T P O R TIO N OF PART NUMBER 1P S E C O N D P O R TIO N OF PART NUMBER www.irf.com IRLR/U3410 Package Outline TO-251AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A- 0.58 (.023) 0.46 (.018) 1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) LE A D A S S IG N M E N T S 4 1 - GATE 2 - D R A IN 6.45 (.245) 5.68 (.224) 3 - SOURCE 4 - D R A IN 6.22 (.245) 5.97 (.235) 1.52 (.060) 1.15 (.045) 1 2 3 -B- N O TE S : 1 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982. 2.28 (.090) 1.91 (.075) 2 C O N T R O LLIN G D IM E N S IO N : IN C H . 3 C O N F O R M S TO J E D E C O U T LIN E T O -252A A . 9.65 (.380) 8.89 (.350) 4 D IM E N S IO N S S H O W N A R E B E F O R E S O LD E R D IP , S O LD E R D IP M A X. +0.16 (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 3X 1.14 (.045) 0.89 (.035) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2X M A M B 0.58 (.023) 0.46 (.018) Part Marking Information TO-251AA (I-PARK) E X A M P L E : T H IS IS A N IR F U 1 2 0 W IT H A S S E M B L Y LO T C OD E 9U 1P IN T E R N A T IO N A L R E C TIF IE R LO GO IR F U 120 9U ASSEMBLY LOT CODE www.irf.com F IR S T P O R T IO N OF PART NUMBER 1P S E C O N D P O R T IO N OF PART NUMBER 9 IRLR/U3410 Tape & Reel Information TO-252AA TR TRR 1 6.3 ( .6 41 ) 1 5.7 ( .6 19 ) 12 .1 ( .4 7 6 ) 11 .9 ( .4 6 9 ) F E E D D IR E C T IO N TRL 16 .3 ( .64 1 ) 15 .7 ( .61 9 ) 8 .1 ( .3 18 ) 7 .9 ( .3 12 ) F E E D D IR E C T IO N NOTES : 1 . C O N T R O LL IN G D IM E N S IO N : M ILL IM E T E R . 2 . A LL D IM E N S IO N S A R E S H O W N IN M ILL IM E T E R S ( IN C H E S ). 3 . O U T L IN E C O N F O R M S T O E IA -4 81 & E IA -54 1. 1 3 IN C H 16 m m NO TES : 1. O U T L IN E C O N F O R M S T O E IA -4 81 . WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371 Data and specifications subject to change without notice. 5/98 10 www.irf.com