INTEGRATED CIRCUITS DATA SHEET TDA9725 Y/C automatic adjustment processor (VHS standard) Product specification Supersedes data of 1995 Dec 06 File under Integrated Circuits, IC02 1996 Oct 14 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 FEATURES GENERAL DESCRIPTION • Automatic adjustment by control loops The TDA9725 is an integrated circuit for chrominance and luminance processing (record and playback) in VHS tape recorders for PAL, SECAM/ME and NTSC systems (4.43 MHz playback only) with internal filter and without adjustments. • Integrated filters • Simple SVHS playback • Colour sequence correction for long-play still mode • Automatic gain control for FM. QUICK REFERENCE DATA SYMBOL PARAMETER VCC supply voltage ICC supply current Vi(p-p) video input voltage; CVBS signal (peak-to-peak value) VoREC(p-p) video output record voltage (peak-to-peak value) VoPB(p-p) CONDITIONS MIN. TYP. MAX. UNIT 4.5 5.0 5.5 V 140 170 200 mA 0.6 1.0 2.0 V video/sync = 7/3 2.03 2.14 2.25 V video output playback voltage (peak-to-peak value) video/sync = 7/3; nominal FM signal 2.03 2.14 2.25 V ViFM(p-p) FM input voltage (peak-to-peak value) FM AGC active 63 200 632 mV VoFM(p-p) FM output voltage (peak-to-peak value) RL = 1 kΩ 0.7 0.9 1.1 V VCFT(p-p) chrominance input voltage (+FM) from tape (peak-to-peak value) 11 110 310 mV VCTT(p-p) chrominance output voltage to tape (peak-to-peak value) 467 660 932 mV Tstg storage temperature −25 − +150 °C Tamb operating ambient temperature −20 − +70 °C VCC = 5 V; playback ORDERING INFORMATION TYPE NUMBER TDA9725 1996 Oct 14 PACKAGE NAME SDIP52 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) 2 VERSION SOT247-1 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 BLOCK DIAGRAM handbook, full pagewidth LPNC GND(Y) CCCD 1.3 kΩ 10 µF 47 nF 52 51 CAGC CVBSI VTC VFC 49 48 4.7 µF 22 nF 1 µF 50 SYNC CSS YNR VCC(Y) CVBSO CHI 1HDL CCD 47 46 45 44 HSS 43 CCD AGC 41 10 µF 40 LPF AGC REC AGC DETECTOR CLAMP 1 42 to BPF 4.43 50 kΩ SYNC SEPARATOR 22 µH 0.1 µF 4.7 µF A PB DOP CLPA CLAMP 2 NOISE CLIP REC YNR PROCESSOR EDIT 50 kΩ PB YNR MIXER Y/C MIXER SCL NOISE CANCELLER 1 PB NLDE EDIT 25 kΩ CHARACTER INSERT REC EDIT PICTURE YLPF PB 50 kΩ PB REC CLAMP 3 1.6 V TDA9725 NLE DTE 2.5 dB to pin 6 SQPB DEVIATION/PLAYBACK DETECTOR DEVIATION CONTROL f0 PROCESSOR FM DEMODULATOR SUBLPF REC DROP-OUT DETECTOR DOUBLE LIMITER DOP ENVELOPE DETECTOR GATE CLPB PB ME SQPB W/DC FM AGC PB MODULATOR to CLP3 1 2 3 4 5 1 kΩ 4.7 µF (1) PCTL CDEV 50 kΩ 6 7 MEO 270 Ω 22 nF 0.1 µF TP2 1 nF 5% SQPB CCLP3 CF0E 1.5 kΩ 8 9 10 MDEC MDEB 470 Ω 1.5 kΩ 11 pin 14 HIGH 0.33 µF FMI CFMA FMO MGB694 0.1 µF VCC(FM) (1) Low leakage current. All capacitors for loop filter ±10%; all other capacitors +10%/−50%; all resistors ±5%; all inductors ±10%; unless otherwise specified. Fig.1 Block diagram (continued in Fig.2). 3 14 PTR peaking 1996 Oct 14 13 0.01 µF 1 kΩ 680 pF 5% NFB 12 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 CF892 handbook, full pagewidth 4 AGCKP1 270 Ω COMB -15 dB 3 2 TP1 1.3 kΩ PBCO PBCI 39 38 37 GND(C) 15 µH 10 nF VCC(C) CFT 10 nF SNP 0.1 µF 10 nF CFI CDO 36 35 BMI 34 CTT fH/2 ACCO 33 32 31 30 29 28 27 A 50 kΩ SEC LPF COMB DRIVER C* fH/2 from 4 PHI BPF 630 BALANCED MIXER PB REC NAP ACC CK H BLANK BURST DOWN PB/SP PB PB/LP PB REC BURST UP BPF 4.43 REC from pin 43 REC ACC DETECTOR LPF 630 CK fH/2 CK CK/FPC DETECTOR TDA9725 fsc PHI/PB VXO X2 3rd LOCK REC MUTE HSS TIMER VXO PB RECORD AFC MUTE REC REC FPC to BM SLD DIVIDER SUBMIXER LPF 4 PHI : 4 8.0 kΩ VCO FREQUENCY DETECTOR 50 kΩ 15 VCC(C) PB SEC MUTE : 40 16 17 18 19 20 21 22 23 24 XTALI 0.1 µF (1) 1 µF ELS CK FCO BGP 22 kΩ ROT 120 kΩ 0.1 µF (1) 25 26 XTALO TEW 8H 470 pF 680 Ω 47 nF 1 µF (1) 4.43619 MHz fsc 33 pF 2 fsc 6.8 µH VCC(C) 4.7 kΩ LFVXO LFVCO MGB695 (1) Low leakage current. Fig.2 Block diagram (continued from Fig.1). 1996 Oct 14 4 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) Table 1 TDA9725 Explanation of symbols in Figs 1 and 2 SYMBOL SYMBOL PIN DESCRIPTION DESCRIPTION ROT 19 rotary pulse input AGCKP1 mode with shortened key pulse for AGC LFVXO 20 loop filter VXO BGP burst gate pulse LFVCO 21 loop filter VCO DOP dropout pulse n.c. 22 not connected; note 1 fH line frequency fsc 23 fsc output fsc subcarrier frequency (4.433619 MHz) XTALI 24 VXO input from crystal HDL CCD charged coupled device with 1H delay XTALO 25 VXO output to crystal NLDE non-linear de-emphasis 2fsc 26 2fsc output NLEDTE non-linear emphasis/detail enhancer fH/2 27 fH/2 output ROT rotary pulse CTT 28 chrominance output to tape VXO voltage controlled XTAL oscillator VCC(C) 29 chrominance supply voltage YNR vertical noise reduction CFT 30 playback chrominance input from tape YLPF luminance low-pass filter GND(C) 31 chrominance ground ACCO 32 automatic chrominance control output PINNING SYMBOL PIN DESCRIPTION PCTL 1 picture control/edit switch input CDEV 2 deviation/playback AGC detector input TP2 3 test pin 2/correlation detector output 4 negative feedback input of main emphasis NFB BMI 33 balanced mixer input SNP 34 switch (SECAM/NTSC/PAL) CDO 35 comb driver output CFI 36 chrominance input from comb filter TP1 37 test pin 1; note 1 PBCO 38 playback chrominance output PBCI 39 playback chrominance input luminance supply voltage VCC(Y) 5 main emphasis output/white clip/modulator input/SQPB selector 40 CVBSO 41 CVBS output CCLP3 6 capacitor for clamp 3 CHI 42 CF0E 7 storage capacitor for f0 processor (record)/envelope detector (playback) character insertion input (artificial sync/black/white/through) CVBSI 43 CVBS input 44 AGC detector capacitor 45 sync separator push-pull output MEO MDEC 8 main de-emphasis output CAGC MDEB 9 main de-emphasis and peaking output SYNC VCC(FM) 10 FM supply voltage CSS 46 sync separator detector capacitor 47 YNR switch FMO 11 FM output YNR PTR 12 switch (PB/TRICK/REC) VFC 48 video input from 1HDL CCD FMI 13 playback FM input VTC 49 video output to 1HDL CCD 14 storage capacitor for FM AGC CCCD 50 storage capacitor for CCD AGC level 15 PAL: switch (LP C*/LP/SP); NTSC: switch (EP/LP/SP) GND(Y) 51 luminance ground LPNC 52 low-pass filter noise canceller CK 16 colour killer terminal FCO 17 frequency correction output BGP 18 burst gate pulse output CFMA ELS 1996 Oct 14 Note 1. It is recommended that this pin should be connected to ground. 5 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 handbook, halfpage PCTL 1 52 LPNC CDEV 2 51 GND(Y) TP2 3 50 CCCD NFB 4 49 VTC MEO 5 48 VFC CCLP3 6 47 YNR CF0E 7 46 CSS MDEC 8 45 SYNC MDEB 9 44 CAGC VCC(FM) 10 43 CVBSI FMO 11 42 CHI PTR 12 41 CVBSO FMI 13 TDA9725 40 VCC(Y) 39 PBCI CFMA 14 38 PBCO ELS 15 CK 16 37 TP1 FCO 17 36 CFI BGP 18 35 CDO ROT 19 34 SNP LFVXO 20 33 BMI LFVCO 21 32 ACCO 31 GND(C) n.c. 22 30 CFT fsc 23 29 VCC(C) XTALI 24 28 CTT XTALO 25 27 fH/2 2fsc 26 MGB693 Fig.3 Pin configuration. 1996 Oct 14 6 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 FUNCTIONAL DESCRIPTION Playback (PB)/video to video (VV) mode Record (REC)/electric to electric (EE) mode LUMINANCE LUMINANCE The FM signal is fed via FM AGC and double limiter to the controlled FM demodulator. After demodulation and filtering in sub low-pass filter (SUBLPF) main de-emphasis, YLPF and non-linear de-emphasis the signal is fed to the vertical noise reduction (YNR) and in parallel to the sync separator. The chrominance signal is added in the Y/C mixer. The complete CVBS signal is available at pin 41. From input pin 43 the CVBS signal is fed via the automatic gain control (AGC) and subclamp (SCL) to the output pin 41. Instead of the controlled and clamped CVBS signal it is also possible to switch (dependent on the level at pin 42) white, black or sync-level to this pin. To eliminate chrominance parts the CVBS signal is fed to the luminance low-pass filter (YLPF) and to the sync separator stage. The sync signal is available at pin 45. The signal is also fed via vertical emphasis non-linear emphasis (NLE), deviation control stage, main emphasis and white-dark clip to the FM modulator. The FM signal is available at pin 11. CHROMINANCE The 627 kHz chrominance signal coming from tape via BPF 627 kHz and field ACC to the balanced mixer. Mixed with 5.06 MHz the 4.43 MHz chrominance signal is fed via comb driver stage to the external comb filter (pin 35) and via internal conjugated complex (C*) stage and internal AC coupling to the luminance part. CHROMINANCE The chrominance signal is selected out of CVBS (from pin 43) in BPF 4.43 MHz (band-pass filter) and controlled in automatic chrominance control (ACC). The chrominance signal is mixed with 5.06 MHz to 627 kHz and via LPF 627 kHz to the output pin 30. Record and playback In both modes record (REC) and playback (PB) the 5.06 MHz mixer frequency is produced by the 20.24 MHz voltage controlled oscillator (VCO) and a divide-by-four. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 0 − 6.0 V VI input voltage at pin 22 0 − 1.6 V Vn input voltage on all other pins 0 − VCC V II input current at pin 22 − − 10 mA Ptot total power dissipation − − 1250 mW Tstg storage temperature −25 − +150 °C Tamb operating ambient temperature −20 − +70 °C Ves electrostatic handling for all pins −300 − +300 V note 1 Note 1. Charge device model class B: discharging a 200 pF capacitor via a 0 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Oct 14 PARAMETER thermal resistance from junction to ambient in free air 7 VALUE UNIT 43 K/W Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 CHARACTERISTICS VCC = 5 V; Tamb = +25 °C and typical application (see Figs 1 and 2), unless otherwise specified. Luminance part: All amplitudes are VBS peak-to-peak values, unless otherwise specified. Chrominance part: All amplitudes for PAL and NTSC are red values with 75% saturation and chrominance-to-burst ratio of 2.2 : 1, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCC supply voltage IPB current consumption (I10 + I29 + I40) IREC current consumption (I10 + I29 + I40) 4.5 5.0 5.5 V playback mode 140 170 200 mA record mode 125 155 185 mA FM SUPPLY (PIN 10) IPB DC playback current − 22 − mA IREC DC record current − 12 − mA playback mode − 85 − mA record mode − 85 − mA CHROMINANCE SUPPLY (PIN 29) ICC(C) DC supply current LUMINANCE SUPPLY (PIN 40) IPB DC playback current − 63 − mA IREC DC record current − 57 − mA pin open-circuit − 1.6 − V sharp picture 0 − 1.6 V soft picture 1.6 − 3.2 V edit mode 4.1 − 5.0 V 1.8 2.5 3.2 V Picture control/edit switch input (pin 1) V1 DC input voltage Deviation/playback AGC detector input (pin 2) V2 detection voltage Test pin 2/correlation detector output (pin 3) VOH HIGH level output voltage correlation of Y signal; pin 37 LOW; RL ≥ 10 kΩ 1.5 2.1 3.0 V VOL LOW level output voltage non-correlation of Y signal − 0.1 0.5 V 1996 Oct 14 8 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Negative feedback input of main emphasis (pin 4; open-base) and main emphasis output/white-clip/modulator/SQPB selector (pin 5) FEEDBACK LOOP CLOSED (PIN 4 CONNECTED TO PIN 5; MAIN EMPHASIS OFF) VSY DC voltage level sync tip − 1.9 − V VoREC(p-p) record output voltage level; standard output level (peak-to-peak value) video/sync = 7/3; ∆VCC = ±0.25 V; Tamb = −10 to +70 °C 450 500 550 mV tFRAMEDET time for correcting carrier interleave relationship to half picture HIGH during half picture 1; note 1 − − 200 ms NON-LINEAR EMPHASIS/DETAIL ENHANCER; notes 2 and 3 RD1 response D1 −20 dB; fi = 500 kHz; SP; NORM 1.7 2.7 3.7 dB RD2 response D2 −20 dB; fi = 2 MHz; SP; NORM 6.0 7.5 9.0 dB RS1 response S1 −20 dB; fi = 500 kHz; SP; EDIT 1.0 1.7 2.4 dB RS1 response S2 −20 dB; fi = 2 MHz; SP; EDIT 4.5 5.5 6.5 dB RL1 response L1 −20 dB; fi = 500 kHz; LP 3.1 4.4 5.7 dB RL2 response L2 −20 dB; fi = 2 MHz; LP 7.0 9.0 11 dB RL3 response L3 0 dB; fi = 2 MHz; LP 1.6 2.3 3.0 dB −30 dB recursive; note 4 3.5 4.3 5.3 dB VERTICAL EMPHASIS PL1 peak level 1 PL2 peak level 2 −20 dB recursive; note 4 3.5 4.0 4.5 dB PL3 peak level 3 0 dB recursive 0 0.4 1.0 dB FEEDBACK LOOP NORMAL APPLICATION DCL dark-clip level 50 60 70 % WCL white-clip level 180 187 194 % V5 SQPB input voltage 4.0 − − V playback mode Record storage capacitor for f0 processor and playback storage capacitor for envelope detector (pin 7) − 1.2 − V DC voltage of normal mode playback mode; Vi = 350 mV (p-p); pin 14 HIGH 2.3 3.3 4.0 V VOFF DC voltage of dropout correction (DOC) off mode playback mode 0 − 1.3 V VNS DC voltage at no input signal playback mode 1.1 1.6 2.1 V GEon envelope detector switch-on level (dropout active) playback mode; 0 dB = Vi = 350 mV (p-p); fi = 3.8 MHz; pin 14 HIGH −13 −10 −7 dB tenv envelope detector operating Ci = 0.1 µF time 380 500 620 µs VI DC voltage VNOR 1996 Oct 14 record mode 9 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Main de-emphasis output (pin 8; open collector) V8 DC output voltage fi = 3.8 MHz at VHS 2.9 3.4 3.9 V VVID(p-p) video output voltage level (peak-to-peak value) fDEV = 1 MHz 230 300 370 mV ΦDEM demodulator sensitivity VHS mode 0.23 0.3 0.37 V/MHz SQPB mode 0.14 0.19 0.24 V/MHz LIN1 demodulator linearity 1 VHS mode 0.97 1.0 1.03 SQPB mode 0.90 1.0 1.07 V 0 ( 5 MHz ) – V 0 ( 4 MHz ) -------------------------------------------------------------------V 0 ( 4 MHz ) – V 0 ( 3 MHz ) LIN2 demodulator linearity 2 V 0 ( 9 MHz ) – V 0 ( 7 MHz ) -------------------------------------------------------------------V 0 ( 7 MHz ) – V 0 ( 5 MHz ) Main de-emphasis and peaking output (pin 9) V9 DC output voltage 1.1 1.6 2.1 V VVR(p-p) reverse video voltage level (peak-to-peak value) fi = 3.8 MHz at VHS 230 300 370 mV αDEM suppression of demodulated carrier 40 − − dB FM output (pin 11) V11 DC mean value output voltage RL = 1 kΩ 2.9 3.2 3.5 V V11(p-p) output voltage level (peak-to-peak value) RL = 1 kΩ 0.7 0.9 1.1 V fsync sync output frequency V5 = Vsync; V43 = 0 dB 3.75 3.8 3.85 MHz ∆fsync stability of sync output frequency ∆VCC = ±0.25 V or Tamb = −10 to +70 °C −20 − +20 kHz fdev frequency deviation V5 = Vwhite; V43 = 0 dB; video/sync = 7/3 0.95 1.0 1.05 MHz ∆fdev stability of frequency deviation ∆VCC = ±0.25 V or Tamb = −10 to +70 °C −20 − +20 kHz ∆frot carrier interleave frequency rotary pulse (pin 19) HIGH/LOW; at SP and LP 6.8 7.8 8.8 kHz H2 second harmonic distortion fi = 3.8 MHz dB Lmod modulator linearity 1996 Oct 14 10 − −50 −42 0.95 1.00 1.05 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Switch: PB/TRICK/REC (pin 12) RI internal resistance to ground 40 50 60 kΩ VPB voltage range for active playback mode 3.5 − 5 V VTR voltage range for active trick mode 1.75 − 3 V VREC voltage range for active record mode 0 − 1.25 V 1.7 2.2 2.7 V Playback FM input (pin 13) V13 DC voltage Vi(p-p) input voltage level (peak-to-peak value) FM AGC active 63 200 632 mV FM AGC not active; pin 14 HIGH − 350 − mV ViBO(p-p) boundary input voltage (peak-to-peak value) fi = 3.8 MHz; pin 14 HIGH 10 − 1000 mV GDOC DOC on level Vi = 350 mV (p-p); fi = 3.8 MHz; pins 7 and 14 HIGH −18 −15 −12 dB ∆Ghys DOC on/off hysteresis Vi = 350 mV (p-p); fi = 3.8 MHz; pins 7 and 14 HIGH 1 3 5 dB GEon envelope detector switch-on level playback mode; 0 dB = Vi = 350 mV (p-p); fi = 3.8 MHz; pin 14 HIGH −13 −10 −7 dB Storage capacitor for FM AGC (pin 14; playback mode) V14 DC voltage AGC on 2.6 3.1 3.6 V DC input voltage AGC off 4.3 − 5.0 V 40 50 60 kΩ Switch LP C*/LP/SP at PAL; EP/LP/SP at NTSC (pin 15) RI internal resistance to ground VC input voltage for active C* (conjugated complex chrominance signal) PAL 3.5 − 5 V VE input voltage for active EP NTSC 3.5 − 5 V VL input voltage for active LP 1.75 − 3 V VS input voltage for active SP 0 − 1.25 V 1996 Oct 14 11 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Colour killer terminal (pin 16) VNC DC voltage black and white luminance input without chrominance 1.6 1.8 2.0 V V16 input voltage forced colour off 0 − 1.5 V forced colour on 3.0 − 4.3 V Vth threshold voltage colour on 2.0 2.2 2.4 V CKth colour killer threshold relative to nominal input; V30 = 110 mV (p-p) −25 −30 −35 dB CKhys colour killer hysteresis relative to nominal input; V30 = 110 mV (p-p) 1 3 5 dB 0.8 − 4.2 V Frequency correction output (pin 17) V17 operating range IoSLD SLD output current SLD ±12 ±17 ±22 µA tSLD SLD pulse duration SLD − 1 − tH fSLH start of detection at positive SLD/PAL frequency deviation SLD/NTSC (referenced to fsc + N × fH at pin 35; −I17) 1.0 2.0 3.0 kHz 2.0 4.0 5.0 kHz start of detection at negative frequency deviation (referenced to fsc + N × fH at pin 35; +I17) SLD/PAL −3.0 −2.0 −1.0 kHz SLD/NTSC −5.0 −4.0 −2.0 kHz IofDET output current of frequency detector FDET ±12 ±17 ±22 µA tfDET frequency detector pulse duration FDET 68 73 78 µs ffDETH start of detection at positive record mode frequency deviation (referenced to fsc + N × fH at pin 35; −I17) 40 70 100 kHz ffDETL start of detection at negative frequency deviation (referenced to fsc + N × fH at pin 35; +I17) −100 −70 −40 kHz fSLL 1996 Oct 14 record mode 12 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Burst gate pulse output (or sandcastle output; pin 18); note 5 tBGP burst gate pulse duration 4.2 4.45 4.7 µs tBGS start of burst gate beyond sync start at pin 45 3.25 3.5 3.75 µs VO(L) LOW level DC output voltage inactive; I18 = 1 mA − − 0.7 V inactive; I18 = 0 mA − − 0.5 V VO(M) medium level DC output voltage horizontal blanking; 10 kΩ connected to VCC 2.2 2.6 3.0 V VO(H) HIGH level DC output voltage BGP; I18 = −0.4 mA 4.0 4.4 − V BGP; I18 = 0 mA 4.6 − − V tVBL(start) vertical blanking of BGP start referring to first equalisation pulse in mid of line − 0 − tH tVBL(stop) vertical blanking of BGP stop referring to rotary transition 23 − − tH − − tH referring to last equalisation pulse 1 in mid of line Rotary pulse input (pin 19; open PNP base) VC2 voltage for −90° phase rotation channel 2 0 − 2.25 V VC1 voltage for non-rotation (PAL) or +90° rotation (NTSC) channel 1 2.75 − 5 V Loop filter VXO (pin 20; record mode) V20 DC voltage 1 2.4 3.6 V ΦVXO VXO sensitivity −1.6 −1.2 −0.8 Hz/mV fPI(U) upper pull-in frequency 0.6 1.0 1.8 kHz fPI(L) lower pull-in frequency −1.8 −1.0 −0.6 kHz 1.3 2.1 2.9 V fH related; record mode −34 −38 −42 kHz/V fsc related; playback mode −1.3 −1.5 −1.7 MHz/V 1.8 2.3 2.8 V 500 600 700 mV Loop filter VCO (pin 21) V21 DC voltage ΦVCO VCO sensitivity fsc output (pin 23) V23 DC output voltage Vo(p-p) output signal voltage (peak-to-peak value) H2 second harmonic distortion − − −25 dB H3 third harmonic distortion − − −20 dB 2.6 3.0 3.4 V no load VXO input from crystal (pin 24); note 6 V24 1996 Oct 14 DC voltage 13 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT VXO output to crystal (pin 25) V25 DC output voltage ∆fosc deviation of oscillator frequency 2.9 3.3 3.7 V due to internal spread; playback mode −50 − +50 Hz video signal without burst; record mode −1.4 − +1.4 kHz no video signal; record mode −100 − +100 Hz VCC = 4.75 to 5.25 V; Tamb = −10 to +70 °C; playback mode −100 − +100 Hz 4.5 4.9 − V 1.2 kΩ connected to VCC and emitter follower (EF) 40 55 70 mV tuned LC circuit to VCC and EF 400 550 700 mV tuned LC circuit (Q > 20) and EF − − −30 dB 2fsc output (pin 26) V26 DC output voltage Vo output signal voltage H2 second harmonic distortion fH/2 output; coupled to burst sequence (pin 27) VO(L) LOW level DC output voltage burst phase = +135° − − 0.5 V VO(H) HIGH level DC output voltage burst phase = −135° 4.5 − − V VNTSC4.43 input level for forced NTSC 4.43 mode (no NAP) NTSC; playback mode − − 1.5 V colour on 2.1 2.4 2.7 V Chrominance output to tape (pin 28); see Table 2 V28 DC output voltage colour killer active − 0.1 0.3 V Vo(p-p) chrominance output signal voltage (N × fH) (peak-to-peak value) record mode; PAL 467 660 932 mV GUP SECAM-fOR burst related to PAL burst SECAM 0.2 1.0 1.8 dB H2 second harmonic distortion V33 = 0 dB − − −40 dB V33 = +6 dB − − −35 dB V33 = 0 dB − − −40 dB V33 = +6 dB − − −35 dB 40 − − dB H3 third harmonic distortion αCK colour killer suppression Playback chrominance input from tape (pin 30) V30 DC voltage Vi(p-p) input signal voltage (peak-to-peak value) 1996 Oct 14 1.7 2.2 2.7 V chrominance + FM − − 310 mV chrominance 11 110 220 mV 14 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT ACC output (pin 32); see Table 5 V32 DC output voltage 1.75 2.25 2.75 V Vo(p-p) controlled output signal voltage (peak-to-peak value) Vi = 0 dB; record mode 370 460 550 mV Vi = 0 dB; playback mode; PAL; −15 dB comb filter 350 440 530 mV ∆Go deviation of output signal Vi = −15 dB/+6 dB; record and playback modes −1.0 − +1.0 dB H2 second harmonic distortion nominal input and output signal − − −40 dB H3 third harmonic distortion nominal input and output signal − − −40 dB Balanced mixer input (pin 33) V33 DC voltage 1.6 1.9 2.2 V Vi(p-p) nominal input signal voltage (peak-to-peak value) − 440 − mV 40 50 60 kΩ active SECAM mode 3.5 − 5 V active NTSC mode 1.75 − 3 V active PAL mode 0 − 1.25 V Switch SECAM/NTSC/PAL (pin 34) RI internal resistance to ground Vi input voltage Comb driver output (pin 35); see Tables 3, 4 and 10 V35 DC output voltage record and playback modes 2.0 2.5 3.0 V Vo(p-p) output signal voltage (peak-to-peak value) playback mode; NTSC; −10 dB comb filter 304 380 456 mV playback mode; PAL/SECAM; −15 dB comb filter 540 675 810 mV H2 second harmonic distortion playback mode; 0 dB − − −40 dB H3 third harmonic distortion playback mode; 0 dB − − −40 dB ∆GBD(S) burst down playback mode; NTSC; SP −6.0 −5.0 −4.0 dB ∆GBD(E) burst down playback mode; NTSC; EP −5.0 −4.0 −3.0 dB GSECid gain of output signal for SECAM identification record mode (ACC is not active) from pin 43 − 3.0 − dB Chrominance input from comb filter (pin 36) VGL DC voltage for glass comb AC coupled 3.2 4.0 4.8 V VCCD DC voltage for CCD comb DC coupled 0 − 1.5 V Vi(p-p) input signal voltage (peak-to-peak value) PAL; NTSC − 120 − mV 1996 Oct 14 15 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Playback chrominance output (pin 38; sync blanking is always active); see Table 6 V38 DC output voltage 1.1 1.6 2.1 V Vo(p-p) output signal voltage (peak-to-peak value) V30 = 110 mV (p-p) 270 325 420 mV H2 second harmonic distortion V30 = 110 mV (p-p) − − −40 dB αCK colour killer/pilot burst suppression colour killer or sync blanking interval 40 − − dB ∆VC* output amplitude deviation C to C*; V36 = 120 mV (p-p) −1.5 0 +1.5 dB ∆ϕC* output phase deviation C to C* or NAP line n to n + 1 −15 0 +15 ° ∆ϕNAP phase for NAP burst NAP burst to −(B − Y) axis ±30 ±45 ±60 ° α2fsc 2fsc suppression C*; V36 = 120 mV (p-p) 35 − − dB α3fsc 3fsc suppression C*; V36 = 120 mV (p-p) 18 25 − dB Playback chrominance input (pin 39) V39 DC voltage 1.7 2.0 2.3 V Vi(p-p) input voltage (peak-to-peak value) − 325 − mV Vth threshold level of AGCKP1 record mode (no reaction on copy guard) 2.6 3.0 3.4 V sync tip; RL = 2.1 kΩ 0.9 1.05 1.2 V CVBS output (pin 41); see Table 7 V41 DC output voltage RECORD MODE VoREC(p-p) record output voltage (standard output level) (peak-to-peak value) video/sync = 7/3; RL = 2.1 kΩ 2.03 2.14 2.25 V ∆VoREC(p-p) record output voltage level stability (peak-to-peak value) ∆VCC = ±0.25 V or Tamb = −10 to +70 °C −40 − +40 mV Vo(p-p) compressed sync output voltage (200 IRE) (peak-to-peak value) video/sync = 7.0/1.5 2.13 2.32 2.52 V GCON control characteristic of AGC V43 = 0.5 to 2.0 V (p-p) 0 0.2 1.0 dB ∆VCG VHS standard (signal amplitude for copy guard tapes) 100% = typical output level; copy guard 7 lines/field 35 − 48 % 1996 Oct 14 16 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT PLAYBACK MODE VoPB(p-p) playback output voltage (peak-to-peak value) video/sync = 7/3; nominal FM signal; RL = 2.1 kΩ; test: EE without ME, MDE, peaking, YNR 2.03 2.14 2.25 V ∆VoPB(p-p) playback output voltage level stability (peak-to-peak value) ∆VCC = ±0.25 V or Tamb = −10 to +70 °C −40 − +40 mV black-to-white = 100%; TRICK VNC white noise clip level ∆Vos offset voltage between DOC mode and normal mode 115 135 150 % −25 − +25 mV αct DOC switch crosstalk − − −40 dB tatt attack time of switching to DOC mode from normal mode − 0.7 1.0 µs trec recovery time of switching to normal mode from DOC mode 4.0 5.0 6.0 µs Vo(p-p) chrominance output voltage (peak-to-peak value) V30 = 110 mV (p-p) 1.0 1.2 1.4 V ∆GCHROM chrominance frequency response Vi = V39; fi = 5 to 1 MHz −2 − +2 dB 0 dB = 2.0 V (p-p); fi = 1 MHz VERTICAL SYNCHRONIZATION PULSE/CHARACTER INSERT (RECORD AND PLAYBACK MODES) ∆VST artificial sync tip level voltage offset V42 = 0 to 5 V; playback mode −50 0 +50 mV ∆Vbl(p-p) artificial black level voltage (peak-to-peak value) V42 = 5 to 3 V 0.58 0.68 0.78 V ∆Vwh(p-p) artificial white level voltage (peak-to-peak value) V42 = 5 to 2 V 1.7 1.9 2.05 V αVIDEO suppression of video at character insert 40 − − dB NON-LINEAR DE-EMPHASIS (PLAYBACK MODE); note 7 S1 response S1 −20 dB; fi = 500 kHz; SP −2.9 −1.9 −0.9 dB S2 response S2 −20 dB; fi = 2 MHz; SP −6.5 −5.0 −3.5 dB L1 response L1 −20 dB; fi = 500 kHz; LP −6.5 −4.8 −3.0 dB L2 response L2 −20 dB; fi = 2 MHz; LP −10.2 −8.4 −6.7 dB L3 response L3 0 dB; fi = 2 MHz; LP −4.8 −3.2 −1.8 dB NOISE CANCELLER (PLAYBACK MODE); note 8 NC1 response NC1 −30 dB; fi = 1 MHz; NORMAL −5.5 −3.5 −1.4 dB NC2 response NC2 −30 dB; fi = 2 MHz; NORMAL −15.0 −11.6 −8.0 dB NC4 response NC4 0 dB; fi = 2 MHz; NORMAL −1.3 −0.3 +0.7 dB NCED response NCEDIT −30 dB; fi = 2 MHz; EDIT −5.0 −3.4 −1.8 dB 1996 Oct 14 17 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT LINE NOISE CANCELLER (YNR WEAK; PLAYBACK MODE); note 9 LNC1 depth 1 −30 dB non-recursive −7.0 −5.5 −4.5 dB LNC2 depth 2 −20 dB non-recursive −4.3 −3.3 −2.3 dB LNC3 depth 3 0 dB non-recursive −1.0 −0.2 0 dB −10.0 −8.5 −7.5 dB VERTICAL NOISE CANCELLER (YNR STRONG; PLAYBACK MODE); note 9 VNC1 depth 1 −30 dB recursive VNC2 depth 2 −20 dB recursive −9.0 −7.5 −6.5 dB VNC3 depth 3 0 dB recursive −1.8 −0.4 0 dB PICTURE CONTROL; (note 10) PC1 response 1 (sharp) V1 = 0 V; fi = 0.5 MHz 0 0.5 1.0 dB PC2 response 2 (sharp) V1 = 0 V; fi = 2 MHz 3.7 4.7 5.7 dB PC3 response 3 (soft) V1 = 3.2 V; fi = 0.5 MHz −2.3 −1.3 −0.8 dB PC4 response 4 (soft) V1 = 3.2 V; fi = 2 MHz −6.8 −5.8 −4.8 dB PC5 response 5 (centre) pin 1 open-circuit or > 4.1 V; fi = 2 MHz −0.5 +0.0 +0.5 dB td delay time pin 1 open-circuit; fi = 0.1 MHz 185 210 235 ns 40 50 60 kΩ Character insert (artificial sync/black/white/through; pin 42) Ri internal resistance to ground VAS input voltage for artificial sync (inserts sync level) 4.0 − 5.0 V VAB input voltage for artificial black (inserts black level) 2.75 − 3.5 V VAW input voltage for artificial white (inserts white level) 1.5 − 2.25 V VTHR input voltage for through mode 0 − 1.0 V V42 = 0 to 1.0 V CVBS input (pin 43) V43 DC voltage 2.35 2.75 3.15 V Vi(p-p) CVBS input voltage (peak-to-peak value) 0.3 1.0 2.0 V 1.8 2.5 3.2 V AGC detector (pin 44) V44 1996 Oct 14 detector voltage V43 = 1 V (p-p) 18 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) SYMBOL PARAMETER TDA9725 CONDITIONS MIN. TYP. MAX. UNIT Sync separator push-pull output (pin 45) VO(H) HIGH level output voltage RL = 2 kΩ to ground 4.5 − − V VO(L) LOW level output voltage RL = 10 kΩ to VCC − − 0.3 V tdFE front edge delay time referenced to sync start pin 48; note 11 600 750 900 ns tdBE back edge delay time referenced to sync end pin 48; note 11 100 350 600 ns Φsync input sensitivity (slicing level for sync) sync-to-black = 100% 26 33 40 % 2.3 − 3.3 V 40 50 60 kΩ YNR off mode 3.5 − 5.0 V YNR1 mode 1.75 − 3.0 V YNR2 mode 0 − 1.25 V Sync separator detector (pin 46) V46 detector voltage YNR switch (pin 47); see Table 11 RI internal resistance to ground V47 input voltage Video input from 1HDL CCD (pin 48) V48 DC voltage 1.5 1.9 2.3 V Vi(p-p) input voltage for constant output signal at pin 49 (peak-to-peak value) 178 283 449 mV 0.9 1.4 1.9 V 380 420 460 mV Video output to 1HDL CCD (pin 49) VoST sync tip output voltage Vo(p-p) output voltage (peak-to-peak value) CCD with −3 dB (record mode) Storage capacitor for CCD level AGC (pin 50) V50 DC voltage 1.4 2.1 2.8 V GCCD CCD gain control range 0 3 6 dB 1.0 1.2 1.4 V Low-pass filter input for noise canceller (pin 52) V52 1996 Oct 14 DC voltage 19 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 Notes to the characteristics 1. 50 Hz; rotary transition 8 to 4 lines beyond vertical pulse. 2. Test mode; YNR off; main emphasis off; V50 = 1.5 V (minimum gain). 3. Input: V48 = 143 mV sync and 0 dB = V48 = 333 mV picture. Output: 0 dB = V5 picture at ≤50 kHz and given input level. 4. Input: V43 = 300 mV sync and 0 dB = V43 = 700 mV picture. Output: 0 dB = V5 picture at 1, 2 and 3 × fH and given input level. 5. Burst gate pulse output with no external components; sandcastle output with 10 kΩ resistor to VCC. 6. Crystal characteristics: TEW 8H: fnom = 4.433619 MHz ± 15 × 10−6; RS ≤ 90 Ω; C1 = 11 fF; L1 = 117.14791 mH; C0 = 2.6 pF. 7. Input: V8 = 90 mV sync and 0 dB = V8 = 210 mV picture. Output: 0 dB = V41 at ≤50 kHz and given input level. Noise canceller off; picture control centre; YNR off; measured with YLPF. 8. Input: V8 = 90 mV sync and 0 dB = V8 = 210 mV picture. Output: 0 dB = V41 at 100 kHz and given input level. Picture control centre; NLDE off; YNR off. Pin 52: R = 1.3 kΩ; C = 47 nF (parasitic capacitance: 5 pF from pin 52 to GND). 9. Input: V8 = 90 mV sync and 0 dB = V8 = 210 mV picture. Output: 0 dB = V41 at 1, 2 and 3 × fH and given input level. Picture control at centre; NC off; NLDE off. 10. Input: V8 = 90 mV sync and V8 = 67 mV picture. Output: 0 dB = V41 at 100 kHz referring to YNRMIX signal at pin 3 of the same frequency. Noise canceller off; YNR off; NLDE off. 11. Input: V48 = 143 mV sync; V50 = 1.5 V; dropout or test mode forced DOC. 1996 Oct 14 20 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 CHROMINANCE FILTER CHARACTERISTICS Table 2 Low-pass filter 630 kHz; frequency response pin 33 to pin 28 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PAL; NTSC/REC ∆G1 frequency response 1 G(1 MHz)/G(0.2 MHz) −4 −3 −2 dB ∆G2 frequency response 2 G(1.5 MHz)/G(0.2 MHz) −9 −7 −5 dB ∆G3 frequency response 3 G(2 MHz)/G(0.2 MHz) −10 −14 −18 dB ∆G4 frequency response 4 G(3 MHz)/G(0.2 MHz) − − −25 dB ∆G5 frequency response 5 G(4.43 MHz)/G(0.2 MHz) − − −40 dB ∆G7 frequency response 7 G(9.5 MHz)/G(0.2 MHz) − − −35 dB td group delay 1 fi = 0.63 MHz 295 335 375 ns frequency response (2) G(1.5 MHz)/G(0.2 MHz) −5 −3 −1 dB SECAM; REC ∆G2 Table 3 Band-pass filter 4.43 MHz at record mode; frequency response pin 43 to pin 35 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PAL; NTSC/REC ∆G1 frequency response 1 G(<2.7 MHz)/G(4.43 MHz) − − −22 dB ∆G2 frequency response 2 G(2.7 MHz)/G(4.43 MHz) − − −30 dB ∆G3 frequency response 3 G(3.93 MHz)/G(4.43 MHz) −3.8 −2.8 −1.8 dB ∆G4 frequency response 4 G(4.93 MHz)/G(4.43 MHz) −2.5 −1.5 −0.5 dB ∆G5 frequency response 5 G(6.2 MHz)/G(4.43 MHz) − − −30 dB ∆G6 frequency response 6 G(>6.2 MHz)/G(4.43 MHz) − − −15 dB td group delay 1 fi = 4.43 MHz 410 450 490 ns frequency response 7 G(5.7 MHz)/G(4.43 MHz) − − −25 dB SECAM; REC ∆G7 1996 Oct 14 21 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) Table 4 TDA9725 Band-pass filter 4.43 MHz at playback mode; frequency response pin 33 to pin 35 (test mode) SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PAL; NTSC/PB ∆G1 frequency response 1 G(<2.7 MHz)/G(4.43 MHz) − − −20 dB ∆G2 frequency response 2 G(2.9 MHz)/G(4.43 MHz) − ∆G3 frequency response 3 G(3.93 MHz)/G(4.43 MHz) −3.7 − −30 dB −2.7 −1.7 dB ∆G4 frequency response 4 G(4.93 MHz)/G(4.43 MHz) −3.9 −2.9 −1.9 dB ∆G5 frequency response 5 G(5.7 MHz)/G(4.43 MHz) − −30 −25 dB ∆G6 frequency response 6 ∆G7 frequency response 7 G(6 MHz)/G(4.43 MHz) − − −22 dB G(>6 MHz)/G(4.43 MHz) − − −15 dB td group delay 1 fi = 4.43 MHz 445 485 525 ns ∆G8 frequency response 8 G(1.9 MHz)/G(4.43 MHz) − −30 −22 dB ∆G9 frequency response 9 G(5.5 MHz)/G(4.43 MHz) − −30 −22 dB SECAM; PB Table 5 Band-pass filter 630 kHz; frequency response pin 30 to pin 32 (test mode) SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PB ∆G1 frequency response 1 G(<100 Hz)/G(630 kHz) − − −20 dB ∆G2 frequency response 2 G(100 kHz)/G(630 kHz) −7 −5 −3 dB ∆G3 frequency response 3 G(930 kHz)/G(630 kHz) −3 −2 −1 dB ∆G4 frequency response 4 G(1.5 MHz)/G(630 kHz) − −15 −10 dB ∆G5 frequency response 5 G(2.3 MHz)/G(630 kHz) − − −40 dB ∆G6 frequency response 6 G(>2.4 MHz)/G(630 kHz) − − −33 dB td group delay 1 fi = 630 kHz; pin 36 normal 710 750 790 ns ∆td group delay 4 difference V36 = 4 to 1 V −210 −170 ns Table 6 −250 Low-pass filter C*; frequency response pin 36 to pin 38 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PB; C ∆G1 frequency response 1 G(5 MHz)/G(2 MHz) 0 −1.5 −3 dB ∆G2 frequency response 2 G(13.3 MHz)/G(2 MHz) −18 −25 − dB ∆G3 frequency response 3 G(>13.3 MHz)/G(2 MHz) −18 − − dB td group delay 1 fi = 4.43 MHz 65 95 125 ns 1996 Oct 14 22 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 LUMINANCE FILTER CHARACTERISTICS Table 7 Low-pass filter 4.43 MHz; frequency response pin 43 to pin 3 (test mode) SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT REC ∆G1 frequency response 1 G(2 MHz)/G(0.2 MHz) −1.0 +0.5 +1.5 dB ∆G2 frequency response 2 G(3 MHz)/G(0.2 MHz) −2.5 −1.0 +0.5 dB ∆G3 frequency response 3 G(4.43 MHz)/G(0.2 MHz) − −40 −30 dB td group delay 1 fi = 0.2 MHz 710 750 790 ns Table 8 Sub-low-pass filter; frequency response from FM demodulator to pin 9 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ∆G1 frequency response 1 G(3 MHz)/G(0.2 MHz) −4.5 −2 0 dB ∆G2 frequency response 2 G(6 MHz)/G(0.2 MHz) − −25 −15 dB Sensitivity Table 9 Sensitivity of PB APC (multiplication factor for phase detector sensitivity) PAL NTSC/NAP NTSC4.4 PROGRAM SP NORM TRICK LP SP LP EP SP LP EP 2 1(2) 2(1)(2) 2(1)(2) 2(1)(2) 4(1) 2(1)(2) 2(1)(2) 2 1(1)(2) 2(1)(2) 2(1)(2) 2(1)(2) 2(1)(2) 2(1)(2) 2(1)(2) Notes 1. No alternating reference for APC loop. 2. Comb filter is inside the APC loop. Burst down logic Table 10 Burst down logic MODE Playback 1996 Oct 14 SYSTEM NTSC BURST DOWN SP ON (−5.0 dB) LP OFF EP ON (−4.0 dB) PAL OFF SECAM OFF 23 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 OPERATION MODE Table 11 Operation mode (PART 1) For PAL RECORD, SECAM ME RECORD, PAL PLAYBACK, SECAM ME PLAYBACK and NTSC PLAYBACK. EP mode at NTSC PLAYBACK activates the same functions as LP mode. EDIT OFF FILTER MODE SP YNR REC PB NLE NLDE REC EDIT ON CONDITIONS LP SP YNR off; pin 47 HIGH OFF OFF YNR 1; pin 47 medium OFF OFF YNR 2; pin 47 LOW OFF vertical emphasis OFF LP YNR off; pin 47 HIGH OFF YNR 1; pin 47 medium VNC (strong) LNC (weak) OFF OFF YNR 2; pin 47 LOW LNC (weak) VNC (strong) OFF LNC (weak) YNR off; pin 47 HIGH NLE(C) + DTE NLE(D) NLE(C) NLE(D) NLDE(D) NLDE(C) NLDE(D) YNR 1; pin 47 medium YNR 2; pin 47 LOW PB NLDE(C) Noise canceller PB ON WEAK Picture control PB ON OFF ON ON FM carrier interleave Table 12 Operation mode (PART 2) FUNCTION Clamps CONDITIONS REC PB ON NORM dropout; maximum 128 lines Character insert Search noise clip REC or PB SQPB 1996 Oct 14 PB OFF VIDEO; pin 42 LOW through WHITE; pin 42 = M1 white level (85%) BLACK; pin 42 = M2 black level SYNC; pin 42 HIGH sync tip level REC PB OPERATION OFF NORM TRICK ON VHS; pin 5 open-circuit VHS SQPB; pin 5 HIGH SQPB 24 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 Automatic chrominance control (ACC) characteristics handbook, halfpage MBG150 Vo(p-p) (mV) 440 − 22 +6 0 dB is equivalent to 110 mv (p-p) at pin 30. Fig.4 ACC characteristics. 1996 Oct 14 25 Vi (dB) 1996 Oct 14 2.5 deviation/playback AGC detector 2 DC (V) picture 1.6 control/EDIT switch PIN NAME (DESCRIPTION) 1 PIN NO. EE 4.1 V to 5.0 V EDIT INTERNAL CIRCUITRY Table 13 Internal circuitry of Figs 1 and 2 VV 0 V to 1.6 V sharp 1.6 V to 3.2 V soft 4.1 V to 5.0 V EDIT WAVEFORM VT/IE + 100 Ω/ 1.3 kΩ 50 kΩ Z 1 26 2 80 µA 2.7 µA 1.3 kΩ 100 Ω + 1.3 kΩ + 1.6 kΩ 1.6 V 50 kΩ MBG145 MBG140 INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 main emphasis output/white clip/ modulator input/ SQPB selector negative feedback input of main emphasis 4 5 test pin 2/ correlation detector output PIN NAME (DESCRIPTION) 3 PIN NO. DC (V) 1.9 V (sync) 500 mV sync-white 27 MBG156 0V 0V 1.9 V (sync) 500 mV sync-white MBG157 0 V = non-COR VV 2.1 V = COR EE WAVEFORM VT/1 mA open base VT/ 500 µA Z MBG138 4 + 1 mA 5 200 Ω MBG136 3 500 µA MBG106 INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 main de-emphasis output storage capacitor for f0 processor (REC)/ envelope detector (PB) 7 8 capacitor for clamp 3 PIN NAME (DESCRIPTION) 6 PIN NO. DC (V) 5V 1.2 V EE VV 3.4 V (sync) 300 mV sync-white 3.3 V WAVEFORM MBG159 open collector VT/IE Z + 7 28 200 Ω 8 kΩ MBG143 5V 5V MBG144 MBG135 10 kΩ 10 kΩ 1.3 kΩ 60 pF + Y/C automatic adjustment processor (VHS standard) 9 8 6 55 pF 2 kΩ 5 kΩ 5 kΩ + + INTERNAL CIRCUIT Philips Semiconductors Product specification TDA9725 1996 Oct 14 FM output 11 switch (PB/TRICK/REC) supply voltage for FM parts 10 12 main de-emphasis and peaking PIN NAME (DESCRIPTION) 9 PIN NO. 5.0 DC (V) 29 0 V to 1.25 V REC MBG154 0.9 V (p-p) rectangle 3.2 V 0V EE VV 1.75 V to 3 V TRICK 3.5 V to 5 V PB 3.7 V 1.6 V (sync) 300 mV sync-white WAVEFORM MBG158 50 kΩ VT/IE + 100 Ω VT/IE Z 12 50 kΩ +VCC(FM) MBG107 10 9 8 100 Ω MBG133 11 MBG135 INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 switch (LPC*/LP/SP) at PAL switch (EP/LP/SP) at NTSC storage capacitor for FM AGC 14 15 PB FM input PIN NAME (DESCRIPTION) 13 PIN NO. 0 DC (V) 0 V to 1.25 V SP 1.75 V to 3.0 V LP 3.5 V to 5.0 V LPC* (PAL) 3.5 V to 5.0 V EP (NTSC) 1.6 V EE VV 3.1 V 4.3 V to 5.0 V FM AGC off MBG154 200 mV (p-p) sinusoidal (350 mV (p-p) if FM AGC off) 2.2 V WAVEFORM 50 kΩ 10 kΩ Z 14 30 15 4 kΩ 200 Ω 3 kΩ MBG139 13 + 50 kΩ + MBG134 190 kΩ + 2.2 V 10 kΩ 200 Ω 200 Ω INTERNAL CIRCUIT MBG142 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 BGP output (HIGH active) frequency correction output 17 18 colour killer terminal PIN NAME (DESCRIPTION) 16 PIN NO. 2.1 2.8 DC (V) 31 (b) with 10 kΩ resistor to VCC (a) 0V 2.2 V 5V (b) VV MBG149 Z + 1.8 V 15 kΩ BGP + 1 kΩ BGP 16 18 MBG141 MBG132 20 kΩ MBG137 17 INTERNAL CIRCUIT Y/C automatic adjustment processor (VHS standard) (a) open circuit 0V 5V EE WAVEFORM Philips Semiconductors Product specification TDA9725 1996 Oct 14 loop filter VCO not connected 22 loop filter (REC) VXO 20 21 rotary pulse PIN NAME (DESCRIPTION) 19 PIN NO. 2.1 2.4 DC (V) 0 V to 2.25 V CH2 2.75 V to 5 V CH1 EE WAVEFORM VV HIGH open base Z 32 MBG129 21 MBG130 20 19 + 1.8 kΩ 80 kΩ MBG131 2.5 V INTERNAL CIRCUIT 1.4 V 2.8 V 2.4 V Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 VXO output to crystal VXO input from crystal 24 25 fSC output PIN NAME (DESCRIPTION) 23 PIN NO. 3.3 3.0 2.3 DC (V) 230 mV (p-p) 250 mV (p-p) 600 mV (p-p) EE 33 MBG154 MBG154 MBG154 WAVEFORM VV VT/ 700 µA 9 kΩ/ 1.3 kΩ VT/ 300 µA Z 24 700 µA 500 Ω 9 kΩ 3V 300 µA + MBG103 25 + MBG127 PB MBG104 23 5.2 kΩ 1.5 kΩ 500 Ω + INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 chrominance output to tape supply voltage chrominance 29 fH/2 output (coupled to burst sequence) NAP/NTSC4.43 switch 27 28 2fSC output PIN NAME (DESCRIPTION) 26 PIN NO. 34 5.0 2.4 4.9 DC (V) 660 mV (p-p) MBG148 5V MBG153 MBG154 0V 2.4 V normal 0 V colour off PB + REC PB: forced 0 V: NTSC4.43 mode 550 mV (p-p) EE WAVEFORM VV VT/ 0.8 mA Z MBG111 2.5 V 30 kΩ + 8.0 kΩ 7.5 27 28 MBG110 0.8 mA 500 Ω 2 kΩ MBG109 26 INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 ACC output 32 balanced mixer input ground 31 33 PB chrominance input from tape PIN NAME (DESCRIPTION) 30 PIN NO. 1.9 2.25 0 2.2 DC (V) 440 mV (p-p) 440 mV (p-p) EE VV 35 MBG153 MBG153 MBG155 chrominance 110 mV (p-p) and FM WAVEFORM 2.7 kΩ VT/ 400 µA 10 kΩ Z 33 30 8 kΩ 1 kΩ + 2.7 kΩ 1.9 V MBG125 400 µA MBG124 MBG115 32 10 kΩ 2.2 V 2.7 kΩ 10 kΩ INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 36 chrominance input from comb filter 4.0 2.5 comb driver output 35 DC (V) switch 0 SECAM/NTSC/PAL PIN NAME (DESCRIPTION) 34 PIN NO. 120 mV (p-p) 4.0 V: glass comb <1.5 V: CCD comb PAL and glass: 675 mV (p-p) NTSC or CCD: 380 mV (p-p) 0 V to 1.25 V PAL 1.75 V to 3.0 V NTSC 3.5 V to 5.0 V SECAM EE WAVEFORM 36 MBG153 MBG153 VV 80 kΩ/ 9 kΩ VT/1 mA 50 kΩ Z + + 50 kΩ 10 kΩ 4.0 V MBG101 36 1 mA MBG116 80 kΩ 34 11 µA 120 Ω 710 Ω 35 MBG123 INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 37 PB chrominance input supply voltage luminance 40 PB chrominance output 38 39 test pin 1 PIN NAME (DESCRIPTION) 37 PIN NO. >3.4 V: AGCKP1 EE 325 mV (p-p) 325 mV (p-p) WAVEFORM VV MBG153 MBG153 20 kΩ VT/ 600 µA 50 kΩ Z MBG122 39 100 kΩ 45 pF 4 kΩ 200 Ω 50 kΩ MBG102 37 38 600 µA 200 Ω 20 kΩ 2.0 V + MBG114 INTERNAL CIRCUIT Y/C automatic adjustment processor (VHS standard) 5.0 1.6 (2.0) 1.6 0 DC (V) Philips Semiconductors Product specification TDA9725 1996 Oct 14 video input character insert (artificial sync/ black/white/ through) 42 43 video output PIN NAME (DESCRIPTION) 41 PIN NO. 2.75 0.0 1.05 sync DC (V) sync-white: 1.0 V (p-p) chrominance: 660 mV (p-p) 0 V to 1.0 V through 1.5 V to 2.25 V white 2.75 V to 3.5 V black 4.0 V to 5.0 V sync sync-white: 2.14 V (p-p) chrominance: 1.2 V (p-p) EE MBG152 MBG152 WAVEFORM VV 50 kΩ VT/1 mA Z 42 38 MBG120 2.75 V 43 MBG119 50 kΩ 2 kΩ 50 kΩ 11.5 kΩ 41 + MBG113 50 kΩ 3.5 kΩ 20 kΩ 1.0 mA 5 kΩ + + INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 1996 Oct 14 sync separator detector sync separator output 45 46 AGC detector PIN NAME (DESCRIPTION) 44 PIN NO. 3.1 2.5 DC (V) 0V 5V EE WAVEFORM MBG147 VV VT/IE + 500 Ω VT/IE + 100 Ω Z 39 + 500 Ω 200 Ω + 45 + MBG117 500 Ω 220 kΩ 46 + MBG121 40 kΩ 1 kΩ MBG112 2.5 µA 125 Ω 44 Y/C automatic adjustment processor (VHS standard) 200 kΩ 200 Ω 60 µA 2.4 kΩ + INTERNAL CIRCUIT Philips Semiconductors Product specification TDA9725 1996 Oct 14 video output to 1H CCD video input from 1H CCD 48 49 YNR switch PIN NAME (DESCRIPTION) 47 PIN NO. 1.4 sync 1.9 0 DC (V) 420 mV (p-p) 283 mV (p-p) 0 V to 1.25 V YNR2 1.75 V to 3.0 V YNR1 3.5 V to 5.0 V YNR off EE WAVEFORM 40 MBG146 MBG146 VV VT/ 230 µA 40 kΩ 50 kΩ Z 47 MBG105 5 kΩ MBG100 48 40 kΩ 1.9 V + 50 kΩ 49 230 µA 500 Ω MBG118 INTERNAL CIRCUIT Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 PIN NAME (DESCRIPTION) storage capacitor for CCD level AGC ground luminance low-pass filter for noise canceller PIN NO. 50 51 52 1996 Oct 14 1.2 0 2.0 DC (V) EE noise WAVEFORM VV MBG151 1 kΩ Z 230 µA + 50 kΩ 1 kΩ MBG108 95 µA + 52 20 kΩ 15 pF 260 Ω 50 INTERNAL CIRCUIT MBG128 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 41 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 PACKAGE OUTLINE seating plane SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 27 52 pin 1 index E 1 26 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 3.2 2.8 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-01-22 95-03-11 SOT247-1 1996 Oct 14 EUROPEAN PROJECTION 42 Philips Semiconductors Product specification Y/C automatic adjustment processor (VHS standard) TDA9725 The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Oct 14 43 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/50/02/pp44 Date of release: 1996 Oct 14 Document order number: 9397 750 01024