DISCRETE SEMICONDUCTORS DATA SHEET ook, halfpage MBD128 BF1102 Dual N-channel dual gate MOS-FET Preliminary specification 1999 Jul 08 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 PINNING - SOT363 FEATURES • Two low noise gain controlled amplifiers in a single package PIN • Specially designed for 5 V applications • Superior cross-modulation performance during AGC • High forward transfer admittance • High forward transfer admittance to input capacitance ratio. DESCRIPTION 1 gate 1 (1) 2 gate 2 (1,2) 3 drain (1) 4 drain (2) 5 source (1,2) 6 gate 1 (2) APPLICATIONS • Gain controlled low noise amplifier for VHF and UHF applications such as television tuners and professional communications equipment. g2 (1, 2) handbook, halfpage 6 5 4 g1 (1) DESCRIPTION The BF1102 is a combination of two equal dual gate MOS-FETs with shared source and gate 2 leads. The source and substrate are interconnected. An internal bias circuit enables DC stabilization and a very good cross-modulation performance at 5 V supply voltage. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. g1 (2) AMP1 d (1) d (2) AMP2 1 2 3 Marking code: W1. s (1, 2) MBL029 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET unless otherwise specified − − 7 V − − 40 mA − − 200 mW − 43 − mS VDS drain-source voltage ID drain current (DC) Ptot total power dissipation Ts ≤ 102 °C; note 1 yfs forward transfer admittance ID = 15 mA Cig1-s input capacitance at gate 1 ID = 15 mA − 2.8 − pF Crss reverse transfer capacitance f = 1 MHz − 30 − fF F noise figure f = 800 MHz − − 2.8 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 − − dBµV Tj operating junction temperature − 150 °C − Note 1. Ts is the temperature at the soldering point of the source lead. CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 1999 Jul 08 2 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET unless otherwise specified VDS drain-source voltage − 7 V ID drain current (DC) − 40 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current − ±10 mA Ptot total power dissipation − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − +150 °C Ts ≤ 102 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER thermal resistance from junction to soldering point Rth j-s MGS359 250 Ptot (mW) handbook, halfpage 200 150 100 50 0 0 50 100 150 Ts (°C) 200 Fig.2 Power derating curve. 1999 Jul 08 3 VALUE UNIT 240 K/W Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 µA V(BR)G1-SS gate-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA 6 15 V V(BR)G2-SS gate-source breakdown voltage VGS = VDS = 0; IG2-S = 5 mA 6 15 V V(F)S-G1 forward source-gate voltage VG2-S = VDS = 0; IS-G1 = −10 mA 0.5 1.5 V V(F)S-G2 forward source-gate voltage VG1-S = VDS = 0; IS-G2 = −10 mA 0.5 1.5 V 7 − V VG1-S(th) gate-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 20 µA 0.3 1 V VG2-S(th) gate-source threshold voltage VDS = 5 V; VG1-S = 4 V; ID = 20 µA 0.3 1.2 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG = 120 kΩ; note 1 12 20 mA IG1-S gate cut-off current VG1-S = 5 V; VG2-S = VDS = 0 − 50 nA IG2-S gate cut-off current VG2-S = 5 V; VG1-S = VDS = 0 − 20 nA Notes 1. RG1 connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET unless otherwise specified (note 1) yfs forward transfer admittance Tj = 25 °C 36 43 50 mS Cig1-ss input capacitance at gate 1 f = 1 MHz 2 2.8 3.6 pF Cig2-ss input capacitance at gate 2 f = 1 MHz − − 7 pF Coss output capacitance f = 1 MHz − 1.6 2.5 pF Crss reverse transfer capacitance f = 1 MHz − 30 50 fF F noise figure f = 800 MHz; YS = YS opt − 2 2.8 dB Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; (note 2) 85 − − dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; (note 2) 100 − − dBµV Notes 1. Not used MOS-FET: VG1-S = 0; VDS = 0. 2. Measured in test circuit of Fig.17. 1999 Jul 08 4 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 ALL GRAPHS FOR ONE MOS-FET MGS360 30 handbook, halfpage handbook, halfpage 2.5 V 3.5 V ID (mA) MGS361 30 VG2-S = 4 V ID (mA) 3V VG1-S = 1.5 V 2V 20 1.4 V 20 1.3 V 1.2 V 1.5 V 10 10 1.1 V 1V 1V 0 0 0.4 0.8 1.2 1.6 0 2.0 2.4 VG1-S (V) 0 VDS = 5 V. VG2-S = 4 V. Tj = 25 °C. Tj = 25 °C. 2 4 6 8 Fig.4 Output characteristics; typical values. Fig.3 Transfer characteristics; typical values. MGS362 160 handbook, halfpage MGS363 50 |yfs | handbook, halfpage VG2-S = 4 V IG1 (µA) 10 VDS (V) 3.5 V VG2-S = 4 V (mS) 3.5 V 40 3V 120 3V 30 80 2.5 V 2.5 V 20 2V 40 10 2V 0 0 0.5 1 1.5 0 2 2.5 VG1-S (V) 0 VDS = 5 V. VDS = 5 V. Tj = 25 °C. T j = 25 °C. Fig.5 1999 Jul 08 Gate 1 current as a function of gate 1 voltage; typical values. Fig.6 5 10 20 ID (mA) 30 Forward transfer admittance as a function of drain current; typical values. Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 MGS364 25 ID (mA) MGS365 15 handbook, halfpage handbook, halfpage ID (mA) 20 10 15 10 5 5 0 0 0 20 40 I G1 (µA) 0 60 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. Fig.7 R G1 = 120 k Ω (connected to VGG ); see Fig.17. Drain current as a function of gate 1 current; typical values. Fig.8 Drain current as a function of gate 1 supply voltage (= VGG); typical values. MGS367 MGS366 30 handbook, halfpage 20 68 kΩ RG1 = 47 kΩ handbook, halfpage ID (mA) 82 kΩ ID (mA) VG1-S = 5 V 4.5 V 16 100 kΩ 4V 120 kΩ 20 3.5 V 150 kΩ 12 3V 180 kΩ 220 kΩ 8 10 4 0 0 0 2 4 6 8 10 VGG = VDS (V) 0 2 4 VG2-S (V) VG2-S = 4 V; Tj = 25 °C. VDS = 5 V; Tj = 25 °C. R G1 connected to VGG; see Fig.17. R G1 = 120 k Ω (connected to VGG ); see Fig.17. Fig.9 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. 1999 Jul 08 6 Fig.10 Drain current as a function of gate 2 voltage; typical values. 6 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 MGS368 40 MGS369 120 handbook, halfpage handbook, halfpage I G1 (µA) Vunw (dB µV) VG1-S = 5 V 30 110 4.5 V 4V 20 100 3.5 V 3V 10 90 0 0 2 4 VG2-S (V) 80 6 0 20 40 60 gain reduction (dB) VDS = 5 V; VGG = 5 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; R G1 = 120 k Ω (connected to VGG ); see Fig.17. VDS = 5 V; Tj = 25 °C. R G1 = 120 k Ω (connected to VGG); see Fig.17. Fig.12 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values. Fig.11 Gate 1 current as a function of gate 2 voltage; typical values. 1999 Jul 08 7 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 MGS370 102 handbook, halfpage MGS371 103 handbook, halfpage yis (mS) 103 −ϕ rs (deg) |yrs | (µS) ϕ rs 102 10 102 |yrs| bis 10 10 1 g is 10 −1 10 102 f (MHz) 1 10 103 102 f (MHz) 1 103 VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V. I D = 15 mA; Tamb = 25 °C. ID = 15 mA; Tamb = 25 °C. Fig.13 Input admittance as a function of frequency; typical values. Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. MGS372 102 handbook, halfpage |yfs | (mS) 102 − ϕ fs (deg) |y fs| MGS373 10 handbook, halfpage yos (mS) bos ϕ fs 10 10 1 g os 1 10 102 f (MHz) 10 −1 10 1 103 VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V. I D = 15 mA; Tamb = 25 °C. ID = 15 mA; Tamb = 25 °C. Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. 1999 Jul 08 102 f (MHz) 103 Fig.16 Output admittance as a function of frequency; typical values. 8 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF L1 C2 RGEN 50 Ω VI R2 50 Ω DUT ≈ 2.2 µH RL 50 Ω C4 4.7 nF RG1 4.7 nF VGG VDS MGS315 Fig.17 Cross-modulation test set-up (for one MOS-FET). 1999 Jul 08 9 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 PACKAGE OUTLINE Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 v M A 4 5 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 1999 Jul 08 REFERENCES IEC JEDEC EIAJ SC-88 10 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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