AD ADG3247

PRELIMINARY TECHNICAL DATA
2.5 V/3.3 V, 16-Bit, 2-Port
Level Translating, Bus Switch
ADG3247
Preliminary Technical Data
FEATURES
225 ps Propagation Delay through the Switch
4.5 Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
40-Lead 6 mm 6 mm LFCSP and 38-Lead TSSOP
Packages
FUNCTIONAL BLOCK DIAGRAM
A0
B0
A7
B7
BE1
A8
B8
A15
B15
BE2
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Plug
Hot Swap
Analog Switching Applications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3247 is a 2.5 V or 3.3 V 16-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
1.
2.
3.
4.
5.
3.3 V or 2.5 V supply operation
Extremely low propagation delay through switch
4.5 Ω switches connect inputs to outputs
Level/voltage translation
40-lead 6 mm ⫻ 6 mm LFCSP and 38-lead TSSOP packages
The ADG3247 is organized as dual 8-bit bus switches with
separate Bus Enable (BEx) inputs. This allows the device to be
used as two 8-bit digital switches or one 16-bit bus switch. These
bus switches allow bidirectional signals to be switched when ON.
In the OFF condition, signal levels up to the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs occurs. Similarly, if the device is operated
from a 2.5 V supply and 2.5 V inputs are applied, the device will
translate the outputs to 1.8 V. In addition to this, the ADG3247
has a level translating select pin (SEL). When SEL is low, VCC is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to applications requiring level translation between different supplies, such
as converter to DSP/microcontroller interfacing.
REV. PrD
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
PRELIMINARY TECHNICAL DATA
ADG3247–SPECIFICATIONS1 (Vnoted.)= 2.3 V to 3.6 V, GND = 0 V, all specifications T
CC
Parameter
Symbol
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
Input Low Voltage
VINL
VINL
Input Leakage Current
II
OFF State Leakage Current
IOZ
ON State Leakage Current
IOL
Max Pass Voltage
VP
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS 3
Propagation Delay A to B or B to A, tPD4
Propagation Delay Matching 5
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Max Data Rate
Channel Jitter
Operating Frequency—Bus Enable
DIGITAL SWITCH
On Resistance
On Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input7
CA OFF
CB OFF
CA, CB ON
CIN
MIN
Conditions
Min
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
0 ⱕ A, B ⱕ VCC
0 ⱕ A, B ⱕ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 µA
VA/VB = VCC = SEL = 2.5 V, IO = –5 µA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA
2.0
1.5
1.5
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
to TMAX, unless otherwise
B Version
Typ2
± 0.01
± 0.01
± 0.01
2.5
1.8
1.8
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V;SEL = VCC
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = SEL = 3.3 V; VA/VB = 2 V
VCC = SEL = 3.3 V; VA/VB = 2 V
1
1
0.5
0.5
0.5
0.5
3.2
3.2
2.2
1.7
2.2
1.75
1.244
50
fBEx
RON
∆RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
4.5
15
5
11
5
14
0.45
0.65
2.3
ICC
ICC
∆ ICC
Unit
0.8
0.7
±1
±1
±1
2.9
2.1
2.1
V
V
V
V
µA
µA
µA
V
V
V
5
5
10
6
tPHL, tPLH CL = 50 pF, VCC = SEL = 3 V
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
Max
Digital Inputs = 0 V or V CC; SEL = VCC
Digital Inputs = 0 V or V CC; SEL = 0 V
VCC = 3.6 V, BE1 = 3.0 V;
BE2 = VCC or GND; SEL = VCC
0.001
0.65
pF
pF
pF
pF
0.225
22.5
4.8
4.8
3.3
2.9
3
2.6
ns
ps
ns
ns
ns
ns
ns
ns
Gbps
ps p-p
10
MHz
8
28
9
18
8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
3.6
1
1.2
V
µA
mA
85
µA
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information.
7
This current applies to the control pins (BEx) only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
LFCSP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 32°C/W
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 98°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the opera tional
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG3247BCP
ADG3247BRU
–40°C to +85°C
–40°C to +85°C
Leaded Chip Scale Package (LFCSP)
Thin Shrink Small Outline Package (TSSOP)
CP-40
RU-38
Table I. Pin Description
Table II. Truth Table
Mnemonic Description
BEx SEL* Function
BEx
SEL
Ax
Bx
L
L
H
Bus Enable (Active Low)
Level Translation Select
Port A, Inputs or Outputs
Port B, Inputs or Outputs
L
H
X
A = B, 3.3 V to 1.8 V Level Shifting
A = B, 3.3 V to 2.5 V/2.5V to 1.8 V Level Shifting
Disconnect
*SEL = 0 only when V DD = 3.3 V ± 10%
40 A5
39 A4
38 A3
37 A2
36 A1
35 A0
34 SEL
33 VCC
32 BE2
31 BE1
PIN CONFIGURATION
40-Lead LFCSP and 38-Lead TSSOP
NC = NO CONNECT
PIN 1
INDICATOR
ADG3247
TOP VIEW
30 B0
29 B1
28 B2
27 B3
26 B4
25 B5
24 B6
23 B7
22 B8
21 B9
GND 11
NC 12
NC 13
NC 14
B15 15
B14 16
B13 17
B12 18
B11 19
B10 20
A6 1
A7 2
A8 3
A9 4
A10 5
A11 6
A12 7
A13 8
A14 9
A15 10
SEL
1
38
VCC
A0
2
37
BE2
36
BE1
A1
3
A2
4
A3
5
ADG3247
B0
TOP VIEW
34 B1
(Not to Scale)
A4
6
33
B2
A5
7
32
B3
A6
8
31
B4
A7
9
30
B5
A8 10
29
B6
A9 11
28
B7
A10 12
27
B8
A11 13
26
B9
A12 14
25
B10
A13 15
24
B11
A14 16
23
B12
A15 17
22
B13
GND 18
21
B14
NC 19
20
B15
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3247 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. PrD
–3–
35
PRELIMINARY TECHNICAL DATA
ADG3247
TERMINOLOGY
VCC
Positive Power Supply Voltage
GND
Ground (0 V) Reference
VINH
Minimum Input Voltage for Logic 1
VINL
Maximum Input Voltage for Logic 0
II
Input Leakage Current at the Control Inputs
IOZ
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
IOL
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
VP
Max Pass Voltage. The max pass voltage relates to the clamped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
RON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬RON
On Resistance Match between Any Two Channels, i.e., RON Max – RON Min
CX OFF
OFF Switch Capacitance
CX ON
ON Switch Capacitance
CIN
Control Input Capacitance. This consists of BEx and SEL.
ICC
Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.
⌬ICC
Extra Power Supply Current Component per each BEx Control Input when the Input is not Driven at the Supplies.
tPLH, tPHL
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON ⫻ CL, where CL is the load capacitance.
tPZH, tPZL
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.
tPHZ, tPLZ
Bus Disable Times. These are the times taken to place the switch in the high impedance OFF state in response to the
control signal. They are measured as the time taken for the output voltage to change by V⌬ from the original quiescent
level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Max Data Rate
Maximum Rate at which Data Can Be Passed through the Switch
Channel Jitter
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel
fBE
Operating Frequency of Bus Enable. This is the maximum frequency at which Bus Enable (BE) can be toggled.
–4–
REV. PrD
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics–ADG3247
40
40
VCC = 3V
TA = 25C
SEL = VCC
35
35
30
30
VCC = 3.3V
20
15
RON – 25
VCC = 3V
TA = 25C
SEL = 0V
35
30
RON – RON – 40
VCC = 2.3V
TA = 25C
SEL = VCC
25
VCC = 2.5V
20
25
VCC = 3.3V
20
15
15
VCC = 3.6V
VCC = 2.7V
10
VCC = 3.6V
5
0
0
0.5
1.0
2.0
1.5
VA/VB – V
3.0
2.5
10
10
5
5
0
3.5
0
0
TPC 1. On Resistance vs.
Input Voltage
1.0
0.5
1.5
2.0
VA/VB – V
2.5
3.0
0
1.0
1.5
2.0
VA/VB – V
3.0
15
VCC = 3.3V
3.0
3.5
SEL = VCC
VCC = 3.6V
TA = 25C
SEL = VCC
IO = –5A
VCC = 2.5V
SEL = VCC
2.5
TPC 3. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
20
0.5
2.5
10
85C
10
VOUT – V
RON – RON – 15
85C
VCC = 3.3V
VCC = 3V
1.5
1.0
5
5
2.0
40C
25C
25C
0.5
40C
0
1.0
VA/VB – V
0.5
0
2.0
1.5
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
0.5
VA/VB – V
1.2
1.0
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
2.5
TA = 25C
SEL = 0V
IO = –5A
VCC = 2.7V
VCC = 2.5V
VCC = 2.3V
1.0
VOUT – V
2.0
1.5
0
0.5
1.0
2.0
1.5
VCC – V
2.5
3.0
3.5
TPC 6. Pass Voltage vs. VCC
1800
2.5
TA = 25C
SEL = VCC
IO = –5A
2.0
VOUT – V
0
0
VCC = 3.6V
TA = 25C
1600
1400
1200
1.5
VCC = 3.3V
VCC = 3V
1.0
ICC – A
0
VCC = 3.3V, SEL = 0V
1000
800
600
0.5
VCC = SEL = 3.3V
400
0.5
VCC = SEL = 2.5V
200
0
0
0.5
1.0
2.0
1.5
VCC – V
2.5
TPC 7. Pass Voltage vs. VCC
REV. PrD
3.0
0
0
0.5
1.0
1.5
2.0
VCC – V
2.5
3.0
TPC 8. Pass Voltage vs. VCC
–5–
3.5
0
0
2
4
6
8 10 12 14 16 18 20
ENABLE FREQUENCY – MHz
TPC 9. ICC vs. Enable Frequency
PRELIMINARY TECHNICAL DATA
ADG3247
3.0
3.0
TA = 25C
VA = 0V
BE = 0
2.5
1.5
VCC = SEL = 3.3V
1.0 V = SEL = 2.5V
CC
0.5
0.5
VCC = SEL = 2.5V
TPC 10. Output Low Characteristic
–2.0
0
TPC 11. Output High Characteristic
–8
–10
–12
–40
–50
–30
–60
–70
0.03
0.1
1
10
100
FREQUENCY – MHz
–50
–90
–100
0.1
1
10
100
FREQUENCY – MHz
1000
90
2.0
ENABLE
DISABLE
TIME – ns
TIME – ns
ENABLE
2.0
80
VCC = SEL = 2.5V
2.5
VCC = 3.3V, SEL = 0V
1.5
0.03
0.1
1
10
100
FREQUENCY – MHz
1000
VCC = SEL = 3.3V
VIN = 2V p-p
20dB ATTENUATION
70
DISABLE
JITTER – ps
DISABLE
TA = 25C
VCC = 3.3V/2.5V
SEL = V CC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50
100
2.5
VCC = SEL = 3.3V
3.0
TPC 15. Off Isolation vs.
Frequency
TPC 14. Crosstalk vs. Frequency
ENABLE
3.0
2.5
–70
–90
0.03
3.5
2.0
1.5
VA/VB – V
–60
–80
1000
TPC 13. Bandwidth vs. Frequency
–40
–80
–100
–14
1.0
TPC 12. Charge Injection vs.
Source Voltage
ATTENUATION – dB
–6
ATTENUATION – dB
–4
0.5
–20
TA = 25C
VCC = 3.3V/2.5V
SEL = V CC
ADJACENT CHANNELS
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50
–30
TA = 25C
VCC = 3.3V/2.5V
SEL = V CC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50
VCC = 3.3V
–1.8
–20
–2
–1.0
–1.2
–1.6
0
–0.10 –0.09 –0.08 –0.07 –0.06 –0.05 –0.04 –0.03 –0.02 –0.01 0
IO – A
0
VCC = 2.5V
–0.8
–1.4
VCC = 3.3V; SEL = 0V
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
IO – A
ATTENUATION – dB
–0.6
1.5
1.0
0
SEL = VCC
ON OFF
CL = InF
–0.4
VCC = SEL = 3.3V
2.0
VCC = 3.3V; SEL = 0V
VOUT – V
VOUT – V
2.0
TA = 25C
–0.2
QINJ – pC
2.5
0
TA = 25C
VA = VCC
BE = 0
1.5
1.0
60
50
40
30
1.0
20
0.5
0.5
10
0
–40
–20
0
20
40
60
TEMPERATURE – C
80
100
TPC 16. Enable/Disable Time
vs. Temperature
0
–40
–20
0
20
40
60
TEMPERATURE – C
80
100
TPC 17. Enable/Disable Time
vs. Temperature
–6–
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – GBPS
TPC 18. Jitter vs. Data Rate;
PRBS 31
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
100
95
EYE WIDTH – %
90
85
VCC = SEL = 3.3V
VIN = 2V p-p
20dB ATTENUATION
80
75
70
65
35mV/DIV
100ps/DIV
60
55
VCC = 3.3V
SEL = 3.3V
VIN = 2V p-p
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) 100%
20dB
ATTENUATION
TA = 25C
37mV/DIV
200ps/DIV
VCC = 2.5V
SEL = 2.5V
VIN = 2V p-p
20dB
ATTENUATION
TA = 28C
50
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – GBPS
TPC 19. Eye Width vs. Data
Rate; PRBS 31
50.1mV/DIV
50ps/DIV
TA = 25C
TPC 20. Eye Pattern; 1.244
GBPS, VCC = 3.3 V, PRBS 31
20dB
ATTENUATION
VCC = 3.3V
SEL = 3.3V
VIN = 2V p-p
TPC 22. Jitter @ 1.244 GBPS,
PRBS 31
REV. PrD
–7–
TPC 21. Eye Pattern; 1 GBPS,
VCC = 2.5 V, PRBS 31
PRELIMINARY TECHNICAL DATA
ADG3247
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that is
used is VIN and VOUT where:
VIN = VA and VOUT = VB
or
VIN = VB and VOUT = VA
VCC
SW1
2 VCC
VIH
OPEN
RL
VOUT
VIN
PULSE
GENERATOR
SWITCH INPUT
GND
tPLH
D.U.T.
tPHL
VH
VT
OUTPUT
RL
CL
RT
VT
0V
VL
Figure 2. Propagation Delay
NOTES
PULSE GENERATOR FOR ALL PULSES: tR 2.5ns, tF 2.5ns,
FREQUENCY 10MHz.
CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
Test Conditions
Symbol
VCC = 3.3 V ± 0.3 V (SEL = VCC)
VCC = 2.5 V ± 0.2 V (SEL = VCC)
VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit
RL
V∆
CL
VT
500
300
50
1.5
500
150
30
0.9
500
150
30
0.9
DISABLE
ENABLE
VINH
VT
CONTROL INPUT BEx
Table III. Switch Position
0V
tPZL
VIN = 0V
VOUT
SW1 @ 2VCC
tPLZ
VCC
VCC
VT
VL + V
VL
tPZH
VIN = VCC
VOUT
SW1 @ GND
Ω
mV
pF
V
TEST
S1
tPLZ, tPZL
tPHZ, tPZH
2 ⫻ VCC
GND
tPHZ
VH
VT
0V
VH – V
0V
Figure 3. Enable and Disable Times
–8–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will, as before, be clamped
to within a voltage threshold below the VCC supply.
Bus switches can be used to provide an ideal solution for interfacing between mixed voltage systems. The ADG3247 is suitable
for applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from
3.3 V directly to 2.5 V.
2.5V
Figure 4 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs;
therefore placing the ADG3247 between the two devices allows the
devices to communicate easily. The bus switch directly connects
the two blocks, thus introducing minimal propagation delay,
timing skew, or noise.
3.3V
In this case, the output will be limited to approximately 1.8 V,
as shown in Figure 7.
VOUT
2.5V
MICROPROCESSOR
2.5V SUPPLY
SEL = 2.5V
1.8V
SWITCH
OUTPUT
3.3V ADC
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
2.5V
ADG3247
3.3V
ADG3247
2.5V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
0V
When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will be clamped to within
a voltage threshold below the VCC supply.
SWITCH
INPUT
VIN
2.5V
Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V to 1.8 V Translation
The ADG3247 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin.
3.3V
3.3V
2.5V
SEL pin: An active low control pin. SEL activates internal
circuitry in the ADG3247 that allows voltage translation between
3.3 V devices and 1.8 V devices.
ADG3247
2.5V
2.5V
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
In this case, the output will be limited to 2.5 V, as shown in
Figure 6.
3.3V
VOUT
ADG3247
1.8V
3.3V SUPPLY
SEL = 3.3V
2.5V
SWITCH
OUTPUT
Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
0V
SWITCH
INPUT
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to VCC.
VIN
3.3V
Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
This device can be used for translation from 2.5 V to 3.3 V
devices, and also between two 3.3 V devices.
REV. PrD
–9–
PRELIMINARY TECHNICAL DATA
VOUT
3.3V SUPPLY
SEL = 0V
1.8V
SWITCH
OUTPUT
CPU
0V
RAM
SWITCH
INPUT
VIN
3.3V
ADG3247 ADG3247
ADG3247
PLUG-IN
CARD (1)
CARD I/O
PLUG-IN
CARD (2)
CARD I/O
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Bus Isolation
Figure 12. ADG3247 in a Hot Plug Application
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3247 is designed specifically for
applications that do not need drive yet require simple logic functions, it solves this requirement. The device isolates access to the
bus, thus minimizing capacitance loading.
Load A
Load C
Bus/
Backplane
Bus Switch
Location
Load B
Load D
Figure 11. Location of Bus Switched in a Bus
Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3247 is suitable for hot swap and hot plug applications.
The output signal of the ADG3247 is limited to a voltage that is
below the VCC supply, as shown in Figures 6, 8, and 10. Therefore the switch acts like a buffer to take the impact from hot
insertion, protecting vital and expensive chipsets from damage.
In hot-plug applications, the system cannot be shutdown when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.
There are many systems that require the ability to handle hot
swapping, such as docking stations, PCI boards for servers, and
line cards for telecommunications switches. If the bus can be
isolated prior to insertion or removal, then there is more control
over the hot swap event. This isolation can be achieved using a
bus switch. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the back plane before any other signal or power pins.
Analog Switching
Bus switches can be used in many analog switching applications;
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS
switch limits the operating voltage (see TPC 1 for a typical plot),
but in many cases this does not present an issue.
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or powerdown, BEx should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the currentsinking capability of the driver.
PACKAGE AND PINOUT
The ADG3247 is packaged in both a small 38-lead TSSOP or a
tiny 40-lead LFCSP package. The area of the TSSOP option is
62.7 mm2, while the area of the LFCSP option is 36 mm2. This
leads to a 43% savings in board space when using the LFCSP
package compared with the TSSOP package. This makes the LFCSP
option an excellent choice for space-constrained applications.
The ADG3247 in the TSSOP package offers a flowthrough
pinout. The term flowthrough signifies that all the inputs are on
opposite sides from the outputs. A flowthrough pinout simplifies
the PCB layout.
–10–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
OUTLINE DIMENSIONS
40-Lead Frame Chip Scale Package [LFCSP]
(CP-40)
Dimensions shown in millimeters
6.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
31
30
PIN 1
INDICATOR
0.50
BSC
5.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
12 MAX
1.00
0.90
0.80
40
1
4.25
3.70 SQ
1.75
BOTTOM
VIEW
21
20
10
11
4.50
REF
1.00 MAX
0.65 NOM
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
38-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-38)
Dimensions shown in millimeters
9.80
9.70
9.60
20
38
4.50
4.40
4.30
1
6.40 BSC
19
PIN 1
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.50
BSC
0.27
0.17
SEATING 0.20
PLANE
0.09
8
0
COMPLIANT TO JEDEC STANDARDS MO-153BD-1
REV. PrD
–11–
0.70
0.60
0.45
–12–
PRINTED IN U.S.A.
C03013–0–2/03(PrD)