2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch ADG3248 FEATURES 225 ps Propagation Delay through the Switch 4.5 ⍀ Switch Connection between Ports Data Rate 1.244 Gbps 2.5 V/3.3 V Supply Operation Level Translation 3.3 V to 2.5 V 2.5 V to 1.8 V Small Signal Bandwidth 610 MHz 6-Lead SC70 Package FUNCTIONAL BLOCK DIAGRAM ADG3248 A0 B A1 IN SWITCHES SHOWN FOR A LOGIC 0 INPUT APPLICATIONS 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Bus Switching Docking Stations Memory Switching Analog Switch Applications GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3248 is a 2.5 V or 3.3 V, high performance 2:1 multiplexer/demultiplexer. It is designed on a low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. 1. 2. 3. 4. 3.3 V or 2.5 V supply operation. Extremely low propagation delay through switch. 4.5 Ω switches connect inputs to outputs. Tiny SC70 package. Each switch of the ADG3248 conducts equally well in both directions when on. The ADG3248 exhibits break-before-make switching action, preventing momentary shorting when switching channels. The ADG3248 is available in a tiny 6-lead SC70 package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADG3248–SPECIFICATIONS1 Parameter Symbol DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH VINH Input Low Voltage VINL VINL Input Leakage Current II OFF State Leakage Current IOZ ON State Leakage Current Maximum Pass Voltage VP CAPACITANCE3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 Propagation Delay Matching5 Transition Time Break-before-Make Time Maximum Data Rate Channel Jitter DIGITAL SWITCH On Resistance On Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current (VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.) Conditions Min VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 2.0 1.7 0 ≤ A, B ≤ VCC 0 ≤ A, B ≤ VCC VA/VB = VCC = 3.3 V, IO = –5 µA VA/VB = VCC = 2.5 V, IO= –5 µA CA OFF CB OFF CA, CB ON CIN f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz tPHL, tPLH CL = 50 pF, VCC = 3 V tTRANS tBBM RL = 510 Ω, CL = 50 pF RL = 510 Ω, CL = 50 pF VCC = 3.3 V; VA/VB = 2 V VCC = 3.3 V; VA/VB = 2 V RON ⌬RON VCC = 3 V, VA = 0 V, IBA = 8 mA VCC = 3 V, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, VA = 0 V, IBA = 8 mA VCC = 2.3 V, VA = 1 V, IBA = 8 mA VCC = 3 V, VA = 0 V, IA = 8 mA ICC Digital Inputs = 0 V or VCC 2.0 1.5 B Version Typ2 Max ± 0.01 ± 0.01 ± 0.01 2.5 1.8 0.8 0.7 ±1 ±1 ±1 2.9 2.1 3.5 4.5 8.5 4 5 Unit V V V V µA µA µA V V pF pF pF pF 0.225 5 29 ns ps ns ns Gbps ps p-p 4.5 12 5 9 0.1 8 28 9 18 0.5 Ω Ω Ω Ω Ω 0.01 3.6 1 V µA 16 10 1.244 45 2.3 NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Typical values are at 25°C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. Specifications subject to change without notice. –2– REV. 0 ADG3248 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION 6-Lead SC70 (TA = 25°C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C A0 1 6 IN 5 VCC ADG3248 GND 2 TOP VIEW A1 3 (Not to Scale) 4 B Table I. Pin Function Descriptions *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Pin No. Mnemonic Description 1 2 3 4 5 6 A0 GND A1 B VCC IN Port A0, Input or Output Ground Reference Port A1, Input or Output Port B, Input or Output Positive Power Supply Voltage Channel Select Table II. Truth Table IN Function L H B = A0 B = A1 ORDERING GUIDE Model Temperature Range Package Description Package Branding ADG3248BKS-R2 ADG3248BKS-REEL ADG3248BKS-REEL7 –40°C to +85°C –40°C to +85°C –40°C to +85°C SC70 (Thin Shrink Small Outline Transistor Package) SC70 (Thin Shrink Small Outline Transistor Package) SC70 (Thin Shrink Small Outline Transistor Package) KS-6 KS-6 KS-6 SMA SMA SMA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3248 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– ADG3248 TERMINOLOGY VCC GND VINH VINL II IOZ IOL VP RON ⌬RON CX OFF CX ON CIN ICC tPLH, tPHL tBBM tTRANS Max Data Rate Channel Jitter Positive Power Supply Voltage. Ground (0 V) Reference. Minimum Input Voltage for Logic 1. Maximum Input Voltage for Logic 0. Input Leakage Current at the Control Inputs. OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state. ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state. Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch. ON Resistance Match between Any Two Channels, i.e., RON max – RON min. OFF Switch Capacitance. ON Switch Capacitance. Control Input Capacitance. This consists of IN. Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins. It is measured when all control inputs are at a logic high or low level and the switches are OFF. Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON × CL, where CL is the load capacitance. On or Off time measured between the 90% points of both switches when switching from one to another. Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the OUT signal. Maximum Rate at which Data Can Be Passed through the Switch. Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel. –4– REV. 0 Typical Performance Characteristics–ADG3248 40 40 TA = 25ⴗC 35 VCC = 3.3V VCC = 2.3V 35 30 15 30 25 RON (⍀) VCC = 3.3V 20 VCC = 2.5V RON (⍀) 25 RON (⍀) 20 TA = 25ⴗC VCC = 3V 20 15 10 ⴙ85ⴗC 15 VCC = 2.7V VCC = 3.6V 5 0 0 0 0.5 1.0 2.0 1.5 VA/VB (V) 3.0 2.5 5 10 5 3.5 0 TPC 1. On Resistance vs. Input Voltage 0.5 1.0 1.5 2.0 VA/VB (V) 3.0 3.0 2.5 VOUT (V) 10 ⴙ85ⴗC 0 1.0 VA/VB (V) 0.5 2.5 TA = 25ⴗC IO = –5A VCC = 2.7V 2.0 2.0 VCC = 3.3V VCC = 3V 1.5 1.5 VCC = 2.5V VCC = 2.3V 1.0 1.0 5 ⴚ40ⴗC ⴙ25ⴗC 0 0 0.5 VA/VB (V) 0.5 0.5 1.0 0 1.2 TPC 4. On Resistance vs. Input Voltage for Different Temperatures 0 0.5 1.0 2.0 1.5 VA/VB (V) 2.5 3.0 0 3.5 TPC 5. Pass Voltage vs. VCC 3.0 2.5 2.0 1.0 0.5 2.0 1.5 VA/VB (V) 2.5 3.0 TA = 25ⴗC ON = OFF CL = 1nF –0.2 VCC = 2.5V –0.4 VCC = 3.3V QINJ (pC) VOUT (V) VCC = 2.5V 1.0 0.5 0 TA = 25ⴗC VA = VCC 2.0 1.5 0 TPC 6. Pass Voltage vs. VCC 3.0 TA = 25ⴗC VA = 0V 2.5 VOUT (V) 2.0 1.5 TPC 3. On Resistance vs. Input Voltage for Different Temperatures VCC = 3.6V TA = 25ⴗC IO = –5A VCC = 2.5V RON (⍀) 2.5 TPC 2. On Resistance vs. Input Voltage 15 ⴙ25ⴗC ⴚ40ⴗC 0 VOUT (V) 10 –0.6 1.5 –0.8 1.0 V = 2.5V CC –1.0 0.5 –1.2 VCC = 3.3V VCC = 3.3V 0 0 0.02 0.04 0.06 IO (A) 0.08 0.10 TPC 7. Output Low Characteristic REV. 0 0 –0.10 –1.4 –0.08 –0.06 –0.04 IO (A) –0.02 0 TPC 8. Output High Characteristic –5– 0 0.5 1.0 1.5 2.0 2.5 VA/VB (V) 3.0 TPC 9. Charge Injection vs. Source Voltage 3.5 0 0 –10 –1 –20 0 TA = 25ⴗC VCC = 3.3V/2.5V VIN = 0dBm N/W ANALYZER: RL = RS = 50⍀ –30 –2 –20 –30 –40 –3 –40 –50 –4 –6 –7 –8 0.03 0.1 –50 –60 TA = 25ⴗC VCC = 3.3V/2.5V VIN = 0dBm N/W ANALYZER: RL = RS = 50⍀ –5 –60 –70 –70 –80 –80 –90 1.0 10 100 FREQUENCY (MHz) 1000 TPC 10. Bandwidth vs. Frequency 25 –90 –100 0.03 0.1 1.0 10 100 FREQUENCY (MHz) 1000 –100 0.03 0.1 TPC 11. Crosstalk vs. Frequency 100 VCC = 3.3V 10 5 0 –40 –20 0 20 40 TEMPERATURE (ⴗC) 60 80 85 TPC 13. Transition Time vs. Temperature VCC = 3.3V 38.7mV/DIV 133.7ps/DIV VIN = 2V p-p 20dB ATTENUATION TA = 25ⴗC TPC 16. Eye Pattern; 1.244 Gbps, VCC = 3.3 V, PRBS 31 70 EYE WIDTH (%) JITTER (ps p-p) tTRANS (ns) 15 60 50 40 95 VCC = 3.3V 90 V = 1.5V p-p A 85 20dB ATTENUATION 80 75 70 30 65 20 60 10 55 0 0.5 1000 100 VCC = 3.3V VA = 1.5V p-p 80 20dB ATTENUATION VCC = 2.5V 1.0 10 100 FREQUENCY (MHz) TPC 12. Off Isolation vs. Frequency 90 20 TA = 25ⴗC VCC = 3.3V/2.5V VIN = 0dBm N/W ANALYZER: RL = RS = 50⍀ –10 ATTENUATION (dB) 1 ATTENUATION (dB) ATTENUATION (dB) ADG3248 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9 TPC 14. Jitter vs. Data Rate; PRBS 31 VCC = 2.5V 20mV/DIV 166.3ps/DIV VIN = 1V p-p % EYE WIDTH = ((CLOCK PERIOD – JITTER p-p)/CLOCK PERIOD) ⴛ 100% 50 0.5 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9 TPC 15. Eye Width vs. Data Rate; PRBS 31 20dB ATTENUATION TA = 25ⴗC TPC 17. Eye Pattern; 1 Gbps, VCC = 2.5 V, PRBS 31 –6– REV. 0 ADG3248 BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation VOUT 2.5V SWITCH OUTPUT Bus switches can provide an ideal solution for interfacing between mixed voltage systems. The ADG3248 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V. 0V 3.3V 2.5V 3.3V ADC ADG3248 Figure 1 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3248 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3V 2.5V MICROPROCESSOR 3.3V SUPPLY SWITCH INPUT VIN 3.3V Figure 3. 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Translation When VCC is 2.5 V and the input signal range is 0 V to VCC, the maximum output signal will, as before, be clamped to within a voltage threshold below the VCC supply. In this case, the output will be limited to approximately 1.8 V, as shown in Figure 5. 2.5V ADG3248 2.5V 1.8V Figure 1. Level Translation between a 3.3 V ADC and a 2.5 V Microprocessor 3.3 V to 2.5 V Translation Figure 4. 2.5 V to 1.8 V Voltage Translation When VCC is 3.3 V and the input signal range is 0 V to VCC, the maximum output signal will be clamped to within a voltage threshold below the VCC supply. VOUT 2.5V SUPPLY 1.8V SWITCH OUTPUT In this case, the output will be limited to 2.5 V, as shown in Figure 3. This device can be used for translation from 2.5 V to 3.3 V devices and also between two 3.3 V devices. 3.3V 0V 3.3V 2.5V Analog Switching Bus switches can be used in many analog switching applications, for example, video graphics. Bus switches can have lower on resistance, smaller ON and OFF channel capacitance, and thus improved frequency performance than their analog counterparts. The bus switch channel itself, consisting solely of an NMOS switch, limits the operating voltage (see TPC 1 for a typical plot), but in many cases, this does not present an issue. 2.5V Figure 2. 3.3 V to 2.5 V Voltage Translation REV. 0 VIN 2.5V Figure 5. 2.5 V to 1.8 V Voltage Translation ADG3248 2.5V SWITCH INPUT –7– ADG3248 MEMORY ADDRESS Multiplexing Many systems, such as docking stations and memory banks, have a large number of common bus signals. Common problems faced by designers of these systems include • Noise due to simultaneous switching of the address and data bus signals DATA MEMORY BANK B MEMORY BANK C Figure 6 shows an array of memory banks in which each address and data signal is loaded by the sum of the individual loads. If a bus switch is used as shown in Figure 7, the output load on the memory address and data bits is halved. The speed at which the selected bank’s data can flow is much improved because the capacitance loading is halved and the switches introduce negligible propagation delay. Bus noise is also reduced. MEMORY BANK D Figure 6. All Memory Banks Are Permanently Connected to the Bus MEMORY ADDRESS MEMORY BANK A MEMORY BANK B ADG3248 Large delays caused by capacitive loading of the bus ADG3248 • MEMORY BANK A DATA MEMORY BANK C MEMORY BANK D Figure 7. ADG3248 Used to Reduce Both Access Time and Noise –8– REV. 0 ADG3248 OUTLINE DIMENSIONS 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 2.00 BSC 6 5 4 2 3 2.10 BSC 1.25 BSC 1 PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 0.10 MAX 1.10 MAX 0.22 0.08 0.30 0.15 SEATING PLANE 8ⴗ 4ⴗ 0ⴗ 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB REV. 0 –9– 0.46 0.36 0.26 –10– –11– –12– C04404–0–10/03(0)