NBSG11 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com The NBSG11 is a 1-to-2 differential fanout buffer, optimized for low skew and ultra-low JITTER. Inputs incorporate internal 50 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. • • • • • • • MARKING DIAGRAM* SG 11 LYW FCBGA-16 BA SUFFIX CASE 489 Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 Internal Input Termination Resistors SG11 ALYW QFN-16 MN SUFFIX CASE 485G A = Assembly Location L = Wafer Lot Y = Year W = Work Week • • Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices *For further details, refer to Application Note AND8002/D ORDERING INFORMATION Device 4x4 mm FCBGA-16 100 Units / Tray NBSG11BAR2 4x4 mm FCBGA-16 500 / Tape & Reel NBSG11MN 3x3 mm QFN-16 123 Units / Rail NBSG11MNR2 3x3 mm QFN-16 3000 / Tape & Reel NBSG11BAEVB April, 2003 - Rev. 6 1 Shipping NBSG11BA Board Semiconductor Components Industries, LLC, 2003 Package Description NBSG11BA Evaluation Board Publication Order Number: NBSG11/D NBSG11 1 A VTCLK B 2 3 4 NC NC Q1 VEE CLK VCC VTCLK 1 CLK 2 VEE NC NC VCC 16 15 14 13 Exposed Pad (EP) 12 Q0 11 Q0 Q1 NBSG11 CLK C VEE VTCLK D VCC NC NC CLK 3 10 Q1 VTCLK 4 9 Q1 Q0 Q0 Figure 1. BGA-16 Pinout (Top View) 5 6 7 8 VEE NC NC VCC Figure 2. QFN-16 Pinout (Top View) Table 1. Pin Description Pin BGA QFN Name I/O D1 1 VTCLK - C1 2 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC. B1 3 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Internal 75 k to VEE. A1 4 VTCLK - Internal 50 Termination Pin. See Table 2. B2,C2 5,16 VEE - Negative Supply Voltage A2,A3,D2, D3 6,7,14,15 NC - No Connect B3,C3 8,13 VCC - Positive Supply Voltage A4 9 Q1 RSECL Output Inverted Differential Output 1. Typically Terminated with 50 to VTT = VCC - 2 V B4 10 Q1 RSECL Output Noninverted Differential Output 1. Typically Terminated with 50 to VTT = VCC - 2 V C4 11 Q0 RSECL Output Inverted Differential output 0. Typically Terminated with 50 to VTT = VCC - 2 V D4 12 Q0 RSECL Output Noninverted Differential Output 0. Typically Terminated with 50 to VTT = VCC - 2 V N/A - EP - Description Internal 50 Termination Pin. See Table 2. Exposed Pad (Note 2) 1. The NC pins are electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. http://onsemi.com 2 NBSG11 VCC VTCLK Q1 36.5 K 50 Q1 CLK CLK 50 75 K Q0 75 K Q0 VTCLK VEE Figure 3. Logic Diagram Table 2. Interfacing Options INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK and VTCLK to VCC LVDS Connect VTCLK and VTCLK together AC-COUPLED Bias VTCLK and VTCLK Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An external voltage should be be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (CLK, CLK) 75 k Internal Input Pullup Resistor (CLK) ESD Protection 36.5 k Human Body Model Machine Model > 2 kV > 100 V FCBGA-16 QFN-16 Level 3 Level 1 Moisture Sensitivity (Note 4) Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V-0 @ 0.125 in 125 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NBSG11 Table 4. MAXIMUM RATINGS (Note 5) Symbol Parameter Condition 1 Condition 2 Rating Units VCC Positive Power Supply VEE = 0 V 3.6 V VEE Negative Power Supply VCC = 0 V -3.6 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 -3.6 V V VINPP Differential Input Voltage 2.8 |VCC - VEE| V V Iout Output Current Continuous Surge 25 50 mA mA TA Operating Temperature Range 16 FCBGA 16 QFN -40 to +70 -40 to +85 °C Tstg Storage Temperature Range -65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) (Note 6) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 16 FCBGA 16 FCBGA 16 QFN 16 QFN 108 86 41.6 35.2 °C/W °C/W °C/W °C/W JC Thermal Resistance (Junction-to-Case) 1S2P (Note 6) 2S2P (Note 7) 16 FCBGA 16 QFN 5.0 4.0 °C/W °C/W Tsol Wave Solder < 15 Seconds 225 °C VI ≤ VCC VI ≥ VEE VCC - VEE VCC - VEE < |D - D| 2.8 V 2.8 V 5. Maximum Ratings are those values beyond which device damage may occur. 6. JEDEC standard multilayer board - 1S2P (1 signal, 2 power). 7. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 8) -40 °C Symbol Characteristic 25°C 70°C(BGA)/85°C(QFN)** Min Typ Max Min Typ Max Min Typ Max Unit 45 60 75 45 60 75 45 60 75 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 9) 1450 1530 1575 1525 1565 1600 1550 1590 1625 mV VOUTPP Output Amplitude Voltage 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single-Ended) (Note 11) VCC1435 mV VCC1000 mV* VCC VCC1435 mV VCC1000 mV* VCC VCC1435 mV VCC1000 mV* VCC V VIL Input LOW Voltage (Single-Ended) (Note 12) VIH2.5 V VCC1400 mV* VIH150 mV VIH2.5 V VCC1400 mV* VIH150 mV VIH2.5 V VCC1400 mV* VIH150 mV V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 1.2 2.5 1.2 2.5 1.2 2.5 V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 IIH Input HIGH Current (@ VIH, VIHMAX) 80 150 80 150 80 150 A IIL Input LOW Current (@ VIL, VILMIN) 25 100 25 100 25 100 A NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 9. All loading with 50 to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 11. VIH cannot exceed VCC. 12. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70°C and devices packaged in QFN-16 have maximum temperature specification of 85°C. http://onsemi.com 4 NBSG11 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 13) -40 °C Symbol Characteristic 25°C 70°C(BGA)/85°C(QFN)** Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 45 60 75 45 60 75 45 60 75 mA VOH Output HIGH Voltage (Note 14) 2250 2330 2375 2325 2365 2400 2350 2390 2425 mV VOUTPP Output Amplitude Voltage 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single-Ended) (Note 16) VCC1435 mV VCC1000 mV* VCC VCC1435 mV VCC1000 mV* VCC VCC1435 mV VCC1000 mV* VCC V VIL Input LOW Voltage (Single-Ended) (Note 17) VIH2.5 V VCC1400 mV* VIH150 mV VIH2.5 V VCC1400 mV* VIH150 mV VIH2.5 V VCC1400 mV* VIH150 mV V VIHCMR Input HIGH Voltage Common Mode Range (Note 15) (Differential Configuration) 1.2 3.3 1.2 3.3 1.2 3.3 V RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 IIH Input HIGH Current (@ VIH, VIHMAX) 80 150 80 150 80 150 A IIL Input LOW Current (@ VIL, VILMIN) 25 100 25 100 25 100 A NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 14. All loading with 50 to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 16. VIH cannot exceed VCC. 17. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70°C and devices packaged in QFN-16 have maximum temperature specification of 85°C. http://onsemi.com 5 NBSG11 Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 18) -40 °C Symbol Characteristic 25°C 70°C(BGA)/85°C(QFN)** Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 45 60 75 45 60 75 45 60 75 mA VOH Output HIGH Voltage (Note 19) -1050 -970 -925 -975 -935 -900 -950 -910 -875 mV VOUTPP Output Amplitude Voltage 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single-Ended) (Note 21) VCC1435 mV VCC1000 mV* VCC VCC1435 mV VCC1000 mV* VCC VCC1435 mV VCC1000 mV* VCC V VIL Input LOW Voltage (Single-Ended) (Note 22) VIH2.5 V VCC1400 mV* VIH150 mV VIH2.5 V VCC1400 mV* VIH150 mV VIH2.5 V VCC1400 mV* VIH150 mV V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 20) 0.0 V RTIN Internal Input Termination Resistor 50 55 IIH IIL VEE+1.2 45 0.0 50 55 Input HIGH Current (@ VIH, VIHMAX) 80 Input LOW Current (@ VIL, VILMIN) 25 VEE+1.2 45 0.0 VEE+1.2 50 55 45 150 80 150 80 150 A 100 25 100 25 100 A NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 21. VIH cannot exceed VCC. 22. VIL always ≥ VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70°C and devices packaged in QFN-16 have maximum temperature specification of 85°C. Table 8. AC CHARACTERISTICS for FCBGA-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 °C Symbol Characteristic fmax Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 23) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 24) Within-Device Skew (Note 25) Device-to-Device Skew (Note 26) tJITTER RMS Random Clock Jitter Min Typ 10.709 12 90 125 160 3 6 25 0.2 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 27) tr tf Output Rise/Fall Times (20% - 80%) @ 1 GHz Max 70°C Min Typ Max Min Typ 10.709 12 90 125 160 15 15 50 3 6 25 1 0.2 Max 10.709 12 90 125 160 ps 15 15 50 3 6 25 15 15 50 ps 1 0.2 1 Unit GHz ps fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C TBD 75 Q, Q 20 30 TBD 2600 75 55 20 30 TBD 2600 75 55 20 30 2600 mV 55 ps 23. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. For minimum fmax value of 10.709 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% - 80%). 24. See Figure 5. tSKEW = |tPLH - tPHL| for a nominal 50% Differential Clock Input Waveform. 25. Within-Device skew is defined as identical transitions on similar paths through a device. 26. Device-to-device skew for identical transitions at identical VCC levels. 27. VINPP (MAX) cannot exceed VCC - VEE. http://onsemi.com 6 NBSG11 Table 9. AC CHARACTERISTICS for QFN-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 °C Symbol Characteristic fmax Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 28) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 29) Within-Device Skew (Note 30) Device-to-Device Skew (Note 31) tJITTER RMS Random Clock Jitter 25°C Min Typ Max 10.5 12 90 125 160 3 6 25 0.2 85°C Min Typ Max Min Typ 10.5 12 90 125 160 15 15 50 3 6 25 1 0.2 Max 10.5 12 90 125 160 ps 15 15 50 3 6 25 15 15 50 ps 1 0.2 1 Unit GHz ps fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 32) tr tf Output Rise/Fall Times (20% - 80%) @ 1 GHz TBD 75 Q, Q 15 30 TBD 2600 75 55 20 30 TBD 2600 75 55 20 30 2600 mV 55 ps 28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. For minimum fmax value of 10.5 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% - 80%). 29. See Figure 5. tSKEW = |tPLH - tPHL| for a nominal 50% Differential Clock Input Waveform. 30. Within-Device skew is defined as identical transitions on similar paths through a device. 31. Device-to-device skew for identical transitions at identical VCC levels. 32. VINPP (MAX) cannot exceed VCC - VEE. 600 8.5 500 7.5 OUTPUT AMP. ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÑÑÑÑÑÑ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÔÔÔ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÒÒ ÔÔÔ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÕÕ ŠŠŠ ÒÒ ÔÔÔ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÑÑÑÑÑ ÚÚ ÕÕ ŠŠŠ ÒÒ ÔÔÔ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÒÒÒ ÑÑÑÑÑ ÚÚ ÕÕ ŠŠŠ ÒÒ ÔÔÔ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ ÒÒÒ ÚÚ ÕÕ ŠŠŠ ÒÒ ÔÔÔ ÓÓ ÑÑ ÓÓÓ ÔÔ ÖÖÖ ÑÑ 6.5 400 5.5 OUTPUT P-P SPEC 300 4.5 3.5 200 2.5 100 1.5 RMS JITTER 0.5 0 1 2 3 4 5 6 7 8 9 INPUT FREQUENCY (GHz) 10 11 12 Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 7 -0.5 JITTERout ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 9.5 NBSG11 CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPLH tPHL Figure 5. AC Reference Measurement Q D Receiver Device Driver Device Q D 50 50 VTT VTT = VCC - 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices) http://onsemi.com 8 NBSG11 PACKAGE DIMENSIONS FCBGA-16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA -XD M -YK E M 0.20 3X e 4 3 2 FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA 1 A 3 B b 16 X C D S VIEW M-M 0.15 M Z X Y 0.08 M Z 5 0.15 Z A A2 A1 16 X 4 -Z- 0.10 Z DETAIL K ROTATED 90 CLOCKWISE http://onsemi.com 9 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG11 PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. -XA M -Y- DIM A B C D E F G H J K L M N P R B N 0.25 (0.010) T 0.25 (0.010) T J R MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031 C 0.08 (0.003) T -T- K SEATING PLANE E H G L 5 8 4 9 F 12 1 16 D 13 P NOTE 3 0.10 (0.004) M T X Y ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 10 NBSG11/D