Order this document by MTD6N15/D SEMICONDUCTOR TECHNICAL DATA N–Channel Enhancement–Mode Silicon Gate TMOS POWER FET 6.0 AMPERES 150 VOLTS RDS(on) = 0.3 OHM This TMOS Power FET is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. • • • • Silicon Gate for Fast Switching Speeds Low RDS(on) — 0.3 Ω Max Rugged — SOA is Power Dissipation Limited Source–to–Drain Diode Characterized for Use With Inductive Loads • Low Drive Requirement — VGS(th) = 4.0 V Max • Surface Mount Package on 16 mm Tape D CASE 369A–13, Style 2 DPAK (TO–252) G S MAXIMUM RATINGS Rating Symbol Value Unit Drain–Source Voltage VDSS 150 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 150 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 50 µs) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous Drain Current — Pulsed ID IDM 6.0 20 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 20 0.16 Watts W/°C Total Power Dissipation @ TA = 25°C Derate above 25°C PD 1.25 0.01 Watts W/°C Total Power Dissipation @ TA = 25°C (1) Derate above 25°C PD 1.75 0.014 Watts W/°C TJ, Tstg – 65 to +150 °C RθJC RθJA RθJA 6.25 100 71.4 °C/W Operating and Storage Junction Temperature Range THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient (1) ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 150 — Vdc — — 10 100 OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0 Vdc) TJ = 125°C µAdc IDSS (1) These ratings are applicable when surface mounted on the minimum pad size recommended. (continued) Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. TMOS Motorola Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTD6N15 ELECTRICAL CHARACTERISTICS — continued (TJ = 25°C unless otherwise noted) Symbol Min Max Unit Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — 100 nAdc Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) TJ = 100°C VGS(th) 2.0 1.5 4.5 4.0 Vdc Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) — 0.3 Ohm Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 100°C) VDS(on) — — 1.8 1.5 gFS 2.5 — mhos Ciss — 1200 pF Coss — 500 Crss — 120 td(on) — 50 tr — 180 td(off) — 200 tf — 100 Characteristic OFF CHARACTERISTICS — continued ON CHARACTERISTICS* Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) See Figure 11 Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS* (TJ = 100°C) Turn–On Delay Time (VDD = 25 Vdc, ID = 3.0 Adc, RG = 50 Ω) See Figures 13 and 14 Rise Time Turn–Off Delay Time Fall Time Total Gate Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 Vdc) See Figure 12 Gate–Source Charge Gate–Drain Charge Qg 15 (Typ) 30 Qgs 8.0 (Typ) — Qgd 7.0 (Typ) — VSD 1.3 (Typ) 2.0 ns nC SOURCE–DRAIN DIODE CHARACTERISTICS* Forward On–Voltage (IS = 6.0 Adc, di/dt = 25 A/µs VGS = 0 Vdc,) Forward Turn–On Time ton Reverse Recovery Time Vdc Limited by stray inductance trr 325 (Typ) — ns * Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. PD, POWER DISSIPATION (WATTS) TA TC 2.5 25 2 20 1.5 15 1 10 0.5 5 0 0 TC 25 50 75 100 125 150 T, TEMPERATURE (°C) Figure 1. Power Derating 2 Motorola TMOS Power MOSFET Transistor Device Data MTD6N15 TYPICAL ELECTRICAL CHARACTERISTICS I D , DRAIN CURRENT (AMPS) 10 V VGS(th) , GATE THRESHOLD VOLTAGE (VOLTS) 24 9V 20 TJ = 25°C 16 8V 12 8 7V 4 6V 5V 0 0 10 20 30 40 50 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 3.6 2.8 2.4 2 – 50 60 TJ = 25°C I D , DRAIN CURRENT (AMPS) VDS = 10 V 12 10 8 6 4 100°C – 55°C 2 0 4 6 8 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 10 1.6 0.20 TJ = 100°C 25°C 0.15 – 55°C 0.10 0.05 0 0 4 8 12 16 ID, DRAIN CURRENT (AMPS) 20 Figure 6. On–Resistance versus Drain Current Motorola TMOS Power MOSFET Transistor Device Data VGS = 0 V ID = 0.25 mA 1.2 0.8 0.4 0 – 50 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) 200 Figure 5. Breakdown Voltage Variation With Temperature RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 0.30 0.25 150 2 Figure 4. Transfer Characteristics VGS = 10 V 0 50 100 TJ, JUNCTION TEMPERATURE (°C) Figure 3. Gate–Threshold Voltage Variation With Temperature V(BR)DSS , DRAIN–TO–SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 2. On–Region Characteristics 14 VDS = VGS ID = 1 mA 3.2 2 1.6 VGS = 10 V ID = 3 A 1.2 0.8 0.4 0 – 50 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) 200 Figure 7. On–Resistance Variation With Temperature 3 MTD6N15 SAFE OPERATING AREA 20 100 µs 10 µs 10 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 20 1 ms 5 2 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.5 0.2 0.1 dc 15 TJ ≤ 150°C 10 5 TC = 25°C VGS = 20 V SINGLE PULSE 0.05 0.03 0.3 0.5 0.7 1 2 3 5 7 10 20 30 50 70 100 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 200 300 0 0 20 Figure 8. Maximum Rated Forward Biased Safe Operating Area 40 60 80 100 120 140 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 160 Figure 9. Maximum Rated Switching Safe Operating Area SWITCHING SAFE OPERATING AREA The FBSOA curves define the maximum drain–to–source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance–General Data and Its Use” provides detailed instructions. The switching safe operating area (SOA) of Figure 9 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn– on and turn–off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) FORWARD BIASED SAFE OPERATING AREA 0.7 0.5 D = 0.5 0.3 0.2 TJ(max) – TC RθJC 0.2 0.1 P(pk) 0.1 0.05 0.07 0.02 0.05 0.03 0.02 0.01 0.01 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 t, TIME OR PULSE WIDTH (ms) 20 RθJC(t) = r(t) RθJC RθJC(t) = 6.25°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 50 100 200 500 1000 Figure 10. Thermal Response 4 Motorola TMOS Power MOSFET Transistor Device Data MTD6N15 2000 TJ = 25°C VGS = 0 C, CAPACITANCE (pF) 1600 1200 800 400 0 15 Ciss VDS = 0 Coss Crss 25 30 5 5 10 20 35 15 0 VGS VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) 10 VGS, GATE SOURCE VOLTAGE (VOLTS) 16 TJ = 25°C ID = 6 A 12 75 V 120 V VDS = 50 V 8 4 0 0 8 12 Qg, TOTAL GATE CHARGE (nC) 4 Figure 11. Capacitance Variation 16 20 Figure 12. Gate Charge versus Gate–To–Source Voltage RESISTIVE SWITCHING VDD ton td(on) RL Vout Vin PULSE GENERATOR Rgen 50 Ω tr 90% td(off) tf 90% OUTPUT, Vout INVERTED DUT z = 50 Ω toff 10% 90% 50 Ω INPUT, Vin 50% 50% 10% PULSE WIDTH Figure 13. Switching Test Circuit Motorola TMOS Power MOSFET Transistor Device Data Figure 14. Switching Waveforms 5 MTD6N15 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface 0.165 4.191 between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.100 2.54 0.118 3.0 0.063 1.6 0.190 4.826 0.243 6.172 inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. PD = 150°C – 25°C = 1.75 Watts 71.4°C/W The 71.4°C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power 6 dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RθJA versus drain pad area is shown in Figure 15. 100 RθJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (°C/W) The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: Board Material = 0.0625″ G–10/FR–4, 2 oz Copper 1.75 Watts 80 TA = 25°C 60 3.0 Watts 40 5.0 Watts 20 0 2 4 6 A, AREA (SQUARE INCHES) 8 10 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. Motorola TMOS Power MOSFET Transistor Device Data ÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. MTD6N15 ÇÇ ÇÇ ÇÇ ÇÇ SOLDER PASTE OPENINGS STENCIL Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. Motorola TMOS Power MOSFET Transistor Device Data • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. 7 MTD6N15 TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 –189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 4 STEP 5 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 “SOAK” “SPIKE” STEP 6 VENT STEP 7 COOLING 205° TO 219°C PEAK AT SOLDER JOINT 170°C 160°C 150°C 150°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) 140°C 100°C DESIRED CURVE FOR LOW MASS ASSEMBLIES 50°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile 8 Motorola TMOS Power MOSFET Transistor Device Data MTD6N15 PACKAGE DIMENSIONS –T– C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R Z A S U K F J L H D G STYLE 2: PIN 1. 2. 3. 4. 2 PL 0.13 (0.005) M T GATE DRAIN SOURCE DRAIN DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 ––– 0.030 0.050 0.138 ––– MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 ––– 0.77 1.27 3.51 ––– CASE 369A–13 ISSUE W Motorola TMOS Power MOSFET Transistor Device Data 9 MTD6N15 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 10 ◊ *MTD6N15/D* Motorola TMOS Power MOSFET TransistorMTD6N15/D Device Data