19-2991; Rev 0; 10/03 IEEE 802.3af PD Interface Controller For Power-Over-Ethernet Features ♦ Fully Integrated IEEE 802.3af-Compliant PD Interface An integrated MOSFET provides PD isolation during detection and classification. The MAX5940A/MAX5940B guarantee a leakage current offset of less than 10µA during the detection phase. A programmable current limit prevents high inrush current during power-on. The device features power-mode UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5940A provides an active-high (PGOOD) opendrain output and a fixed UVLO threshold. The MAX5940B provides both active-high (PGOOD) and active-low (PGOOD) outputs and has an adjustable UVLO threshold with the default value compliant to the 802.3af standard. The MAX5940A/MAX5940B are designed to work with or without an external diode bridge. The MAX5940A/MAX5940B are available in 8-pin SO packages and are rated over the extended temperature range of -40°C to +85°C. ♦ Gate Output Allows External Control of the Internal Isolation MOSFET Applications IP Phones Security Cameras Wireless Access Nodes IEEE 802.3af Power Devices ♦ PD Detection and Programmable Classification Signatures ♦ Less than 10µA Leakage Current Offset During Detection ♦ Integrated MOSFET For Isolation and Inrush Current Limiting ♦ Programmable Inrush Current Control ♦ Programmable Undervoltage Lockout (MAX5940B Only) ♦ Wide UVLO Hysteresis Accommodates TwistedPair Cable Voltage Drop ♦ PGOOD/PGOOD Outputs to Enable Downstream DC-DC Converters ♦ -40°C to +85°C Operating Temperature Range Ordering Information PINPACKAGE PART TEMP RANGE UVLO MAX5940AESA -40°C to +85°C 8 SO Fixed MAX5940BESA -40°C to +85°C 8 SO Adjustable Pin Configurations appear at end of data sheet. Computer Telephony Typical Operating Circuits D1* DC-DC CONVERTER GND V+ GND 60V 68nF RDISC 25.5kΩ RCL D2* -48V 2 8 COUT MAX5014 RCLASS GND 3 VREG SS_SHDN MAX5940A GATE 4 VEE *OPTIONAL. PGOOD OUT LOAD 6 5 CGATE Typical Operating Circuits continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5940A/MAX5940B General Description The MAX5940A/MAX5940B provide complete interface function for a powered device (PD) to comply with the IEEE 802.3af standard in a power-over-ethernet system. MAX5940A/MAX5940B provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also feature power-mode undervoltage lockout (UVLO) with wide hysteresis, and power-good outputs. MAX5940A/MAX5940B IEEE 802.3af PD Interface Controller For Power-Over-Ethernet ABSOLUTE MAXIMUM RATINGS UVLO, PGOOD, PGOOD to VEE .....................................20mA GATE to VEE ....................................................................80mA Continuous Power Dissipation (TA = +70°C) 8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) ................................+300°C (All voltages are referenced to VEE, unless otherwise noted.) GND........................................................................-0.3V to +80V OUT, PGOOD ...........................................-0.3V to (GND + 0.3V) RCLASS, GATE ......................................................-0.3V to +12V UVLO ........................................................................-0.3V to +8V PGOOD to OUT.........................................-0.3V to (GND + 0.3V) Maximum Input/Output Current (continuous) OUT to VEE ...................................................................500mA GND, RCLASS to VEE .....................................................70mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 µA DETECTION MODE Input Offset Current (Note 2) Effective Differential Input Resistance (Note 3) IOFFSET dR VIN = 1.4V to 10.1V VIN = 1.4V up to 10.1V with 1V step, OUT = PGOOD = GND 550 VIN rising 20.8 kΩ CLASSIFICATION MODE Classification Current Turn-Off Threshold (Note 4) VTH,CLSS Class 0, RCL = 10kΩ Classification Current (Notes 5, 6) ICLASS 21.8 0 22.5 V 2 VIN = 12.6V to Class 1, RCL = 732Ω 20V, RDISC = Class 2, RCL = 392Ω 25.5kΩ Class 3, RCL = 255Ω 9.17 11.83 17.29 19.71 26.45 29.55 Class 4, RCL = 178Ω 36.6 41.4 mA POWER MODE Operating Supply Voltage VIN VIN = (GND - VEE) Operating Supply Current IIN Measure at GND, not including RDISC 1 35.4 36.6 MAX5940B, UVLO = VEE 37.4 38.6 39.9 VIN increasing Default Power Turn-Off Voltage VUVLO, OFF VIN decreasing, UVLO = VEE for MAX5940B External UVLO Programming Range MAX5940A 4.2 MAX5940B, UVLO = VEE 7.4 VIN,EX Set UVLO externally (MAX5940B only) (Note 7) 12 VREF, UVLO UVLO External Reference Voltage Hysteresis HYST UVLO Bias Current IUVLO 2 30 UVLO UVLO External Reference Voltage mA 0.4 34.3 VUVLO, ON VHYST, V MAX5940A Default Power Turn-On Voltage Default Power Turn-On/Off Hysteresis 67 V V V 67 V 2.400 2.460 2.522 V Ratio to VREF,UVLO 19.2 20 20.9 % UVLO = 2.460V -1.5 +1.5 µA _______________________________________________________________________________________ IEEE 802.3af PD Interface Controller For Power-Over-Ethernet (VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1) PARAMETER UVLO Input Ground-Sense Threshold (Note 8) SYMBOL VTH,G,UVLO UVLO Input Ground-Sense Glitch Rejection Power Turn-Off Voltage, Undervoltage Lockout Deglitch Time (Note 9) Isolation Switch N-Channel MOSFET On-Resistance Isolation Switch N-Channel MOSFET Off-Threshold Voltage CONDITIONS UVLO = VEE tOFF_DLY RON VGSTH VIN, VUVLO falling Output current = 300mA, VGATE = 6V, measured between OUT and VEE mV µs ms 0.6 1.1 TA = +85°C 0.8 1.5 OUT = GND, VGATE - VEE, output current < 1µA IG VGATE = 2V VGATE Ω 0.5 V 38 80 Ω 5 10 15 µA IGATE = 1µA 5.59 5.76 5.93 V VOUT - VEE, |VOUT - VEE| decreasing, VGATE = 5.75V 1.16 1.23 1.31 V 4.62 4.76 Hysteresis VGSEN 440 TA = +25°C (Note 10) GATE Charging Current PGOOD, PGOOD Assertion VGATE Threshold UNITS 0.32 Power-off mode, VIN = 12V, UVLO = VEE for MAX5940B VOUTEN MAX 7 RG PGOOD, PGOOD Assertion VOUT Threshold TYP 50 GATE Pulldown Switch Resistance GATE High Voltage MIN (GATE - VEE) increasing, OUT = VEE Hysteresis 70 mV 4.91 80 V mV ISINK = 2mA; for PGOOD, OUT ≤ (GND - 5V) 0.4 V PGOOD Leakage Current (Note 11) GATE = high, GND - VOUT = 67V 1 µA PGOOD Leakage Current (Note 11) GATE = VEE, PGOOD - VEE = 67V 1 µA PGOOD, PGOOD Output Low Voltage (Note 11) VOLDCDC Note 1: All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design. Note 2: The input offset current is illustrated in Figure 1. Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external resistance. See Figure 1. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be ±1%, 100ppm or better. ICLASS includes the IC bias current and the current drawn by RDISC. Note 6: See the Thermal Dissipation section for details. Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turnon threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage (MAX5940B only). Note 8: When the UVLO input voltage is below VTH,G,UVLO, the MAX5940B sets the UVLO threshold internally. Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the MAX5940A/MAX5940B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V). Note 10: Guaranteed by design. Note 11: PGOOD references to OUT while PGOOD references to VEE. _______________________________________________________________________________________ 3 MAX5940A/MAX5940B ELECTRICAL CHARACTERISTICS (continued) IIN dRi ≅ 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) IOFFSET ≅ IINi - VINi dRi IINi + 1 dRi IINi IOFFSET VINi 1V VINi + 1 VIN Figure1 . Effective Differential Input Resistance/Offset Current Typical Operating Characteristics (VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE (MAX5940B), TA = -40°C to +85°C. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) 0.3 IIN + IRDISC 0.2 0.1 40 CLASS 4 30 CLASS 3 20 CLASS 2 CLASS 1 10 CLASS 0 0 0 2 4 6 8 10 5 10 15 20 25 30 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT OFFSET CURRENT vs. INPUT VOLTAGE NORMALIZED UVLO vs. TEMPERATURE PGOOD OUTPUT LOW VOLTAGE vs. CURRENT 1.006 NORMALIZED UVLO -1.0 1.008 -1.5 -2.0 -2.5 200 1.004 1.002 1.000 0.998 150 100 0.996 50 0.994 -3.0 250 VPGOOD (mV) -0.5 UVLO = VEE 12 MAX5940A/B toc06 1.010 MAX5940A/B toc04 0 0.992 0 0.990 -3.5 1 3 5 7 INPUT VOLTAGE (V) 4 0 MAX5940A/B toc05 0 3.5 MAX5940A/B toc03 0.4 50 MAX5940A/B toc02 DETECTION CURRENT (mA) RDISC = 25.5kΩ CLASSIFICATION CURRENT (mA) MAX5940A/B toc01 0.5 EFFECTIVE DIFFERENTIAL INPUT RESISTANCE vs. INPUT VOLTAGE CLASSIFICATION CURRENT vs. INPUT VOLTAGE EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (MΩ) DETECTION CURRENT vs. INPUT VOLTAGE INPUT OFFSET CURRENT (µA) MAX5940A/MAX5940B IEEE 802.3af PD Interface Controller For Power-Over-Ethernet 9 11 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 5 10 ISINK (mA) _______________________________________________________________________________________ 15 20 IEEE 802.3af PD Interface Controller For Power-Over-Ethernet OUT LEAKAGE CURRENT vs. TEMPERATURE PGOOD OUTPUT LOW VOLTAGE vs. CURRENT VPGOOD (mV) 240 160 80 MAX5940A/B toc08 320 INRUSH CURRENT CONTROL (VIN = 12V) MAX5940A/B toc09 20 VOUT = 67V OUT LEAKAGE CURRENT (nA) MAX5940A/B toc07 400 16 VGATE 5V/div 12 IINRUSH 100mA/div 8 VOUT TO VEE 10V/div 4 PGOOD 10V/div 0 0 0 5 10 15 20 -40 -15 10 35 60 1ms/div 85 TEMPERATURE (°C) ISINK (mA) INRUSH CURRENT CONTROL (VIN = 48V) INRUSH CURRENT CONTROL (VIN = 67V) MAX5940A/B toc10 MAX5940A/B toc11 VGATE 5V/div VGATE 5V/div IINRUSH 100mA/div IINRUSH 100mA/div VOUT TO VEE 50V/div VOUT TO VEE 50V/div PGOOD PGOOD 50V/div 50V/div 2ms/div 2ms/div _______________________________________________________________________________________ 5 MAX5940A/MAX5940B Typical Operating Characteristics (continued) (VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE (MAX5940B), TA = -40°C to +85°C. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) MAX5940A/MAX5940B IEEE 802.3af PD Interface Controller For Power-Over-Ethernet Pin Description PIN MAX5940A MAX5940B 1, 7 — NAME N.C. — 1 UVLO 2 2 RCLASS FUNCTION No Connection. Not internally connected. Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its threshold, the device enters power mode. Connect UVLO to VEE to use the default undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull UVLO to between VTH,G,UVLO and VREF,UVLO. Classification Setting. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1 and 2). Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters power mode. Connect an external 100V ceramic capacitor (CGATE) from GATE to OUT to program the inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection and classification functions operate normally when GATE is pulled to VEE. 3 3 GATE 4 4 VEE Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect VEE to -48V. 5 5 OUT Output Voltage. Drain of the integrated isolation N-channel power MOSFET. 6 6 PGOOD Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled to OUT (given that VOUT is at least 5V below GND). Connect PGOOD to the ON pin of a downstream DC-DC converter. Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to VEE. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream DC-DC converter. — 7 PGOOD 8 8 GND Ground. GND is the positive input terminal. Detailed Description Operating Modes The PD front-end section of the MAX5940A/MAX5940B operates in 3 different modes, PD detection signature, PD classification, and PD power, depending on its input voltage (VIN = GND - VEE). All voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the IEEE 802.3af standard (see Figure 4). Detection Mode (1.4V ≤ VIN ≤ 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum), and then records the current measurements at the two points. The PSE then computes ∆V/∆I to ensure the presence of the 25.5kΩ signature resistor. In this mode, most of the MAX5940A/ 6 MAX5940B internal circuitry is off and the offset current is less than 10µA. If the voltage applied to the PD is reversed, install protection diodes on the input terminal to prevent internal damage to the MAX5940A/MAX5940B (see the Typical Application Circuits). Since the PSE uses a slope technique (∆V/∆I) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process. Classification Mode (12.6V ≤ VIN ≤ 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different classes as shown in Table 1. An external resistor (RCL) connected from RCLASS to VEE sets the classification current. _______________________________________________________________________________________ IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B Table 1. PD Power Classification/RCL Selection CLASS USAGE RCL (Ω) MAXIMUM POWER USED BY PD (W) 0 Default 10k 0.44 to 12.95 1 Optional 732 0.44 to 3.84 2 Optional 392 3.84 to 6.49 3 Optional 255 6.49 to 12.95 4 Not Allowed 178 Reserved* *Class 4 reserved for future use. Table 2. Setting Classification Current CLASS RCL (Ω) VIN* (V) 0 10k 12.6 to 20 1 732 2 392 3 4 CLASS CURRENT SEEN AT VIN (mA) IEEE 802.3af PD CLASSIFICATION CURRENT SPECIFICATION (mA) MIN MAX MIIN MAX 0 2 0 4 12.6 to 20 9.17 11.83 9 12 12.6 to 20 17.29 19.71 17 20 255 12.6 to 20 26.45 29.55 26 30 178 12.6 to 20 36.6 41.4 36 44 *VIN is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop. The PSE determines the class of a PD by applying a voltage at the PD input and measures the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5940A/MAX5940B exhibit a current characteristic with values indicated in Table 2. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by the 25.5kΩ detection signature resistor and the supply current of the MAX5940A/MAX5940B so the total current drawn by the PD is within the IEEE 802.3af standard figures. The classification current is turned off whenever the device is in power mode. Power Mode During power mode, when VIN rises above the undervoltage lockout threshold (V UVLO,ON ), the MAX5940A/ MAX5940B gradually turn on the internal N-channel MOSFET Q1 (see Figure 2). The MAX5940A/MAX5940B charge the gate of Q1 with a constant current source (10µA, typ). The drain-to-gate capacitance of Q1 limits the voltage rise rate at the drain of the MOSFET, thereby limiting the inrush current. To reduce the inrush current, add external drain-to-gate capacitance (see the Inrush Current section). When the drain of Q1 is within 1.2V of its source voltage and its gate-to-source voltage is above 5V, the MAX5940A/MAX5940B asserts the PGOOD/PGOOD outputs. The MAX5940A/MAX5940B have a wide UVLO hysteresis and turn-off deglitch time to compensate for the high impedance of the twistedpair cable. Undervoltage Lockout The MAX5940A/MAX5940B operate up to a 67V supply voltage with a default UVLO turn-on (VUVLO,ON) set at 35V (MAX5940A) or 39V (MAX5940B) and a UVLO turnoff (VUVLO,OFF) set at 30V. The MAX5940B has an adjustable UVLO threshold using a resistor-divider connected to UVLO (see Figure 3). When the input voltage is above the UVLO threshold, the IC is in power mode and the MOSFET is on. When the input voltage goes below the UVLO threshold for more than tOFF_DLY, the MOSFET turns off. _______________________________________________________________________________________ 7 MAX5940A/MAX5940B IEEE 802.3af PD Interface Controller For Power-Over-Ethernet GND 2.46V UVLO REF EN GND CLASSIFICATION 6.8V RCLASS R1 (PGOOD) MAX5940B Q4 R2 20% R3 VGATE 1.2V, REF EN (UVLO) PGOOD 5V, REF Q3 OUT Q2 200mV GATE Q1 VEE ( ) MAX5940B. Figure 2. Block Diagram To adjust the UVLO threshold (MAX5940B only), connect an external resistor-divider from GND to UVLO and from UVLO to VEE. Use the following equations to calculate R1 and R2 for a desired UVLO threshold: R2 = 25.5kΩ x VIN = 12V TO 67V VREF,UVLO GND VIN,EX R1 R1 = 25.5kΩ - R2 where VIN,EX is the desired UVLO threshold. Since the resistor-divider replaces the 25.5kΩ PD detection resistor, ensure that the sum of R1 and R2 equals 25.5kΩ ±1%. When using the external resistor-divider, the MAX5940B has an external reference voltage hysteresis of 20% (typ). When UVLO is programmed externally, the turn-off threshold is 80% (typ) of the new UVLO threshold. UVLO MAX5940B R2 VEE Figure 3. Setting Undervoltage Lockout with an External Resistor-Divider 8 _______________________________________________________________________________________ IEEE 802.3af PD Interface Controller For Power-Over-Ethernet IINRUSH = IG x COUT CGATE PGOOD/PGOOD Outputs (MAX5940A/MAX5940B) PGOOD is an open-drain, active-high logic output. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled to VOUT (given that VOUT is at least 5V below GND). Connect PGOOD to the ON pin of a downstream DC-DC converter. Connect a 100kΩ pullup resistor from PGOOD to GND if needed. (MAX5940B only) PGOOD is an open-drain, active-low logic output. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream DC-DC converter. Connect a 100kΩ pullup resistor from PGOOD to GND if needed. Thermal Dissipation During classification mode, if the PSE applies the maximum DC voltage, the maximum voltage drop from GND to VRCLASS will be 13V. If the maximum classification current of 42mA flows through the MAX5940A/ MAX5940B, then the maximum DC power dissipation will be 546mW, which is slightly higher than the maximum DC power dissipation of the IC at maximum operating temperature. However, according to the IEEE 802.3af standard, the duration of the classification mode is limited to 75ms (max). The MAX5940A/MAX5940B handle the maximum classification power dissipation for the maximum duration time without sustaining any internal damage. If the PSE violates the IEEE 802.3af standard by exceeding the 75ms maximum classification duration, it may cause internal damage to the IC. _______________________________________________________________________________________ 9 MAX5940A/MAX5940B Inrush Current Limit The MAX5940A/MAX5940B charge the gate of the internal MOSFET with a constant current source (10µA, typ). The drain-to-gate capacitance of the MOSFET limits the voltage rise rate at the drain, thereby limiting the inrush current. Add an external capacitor from GATE to OUT to further reduce the inrush current. Use the following equation to calculate the inrush current: IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B Typical Application Circuits Application Circuit 1 POWER-OVER SIGNAL PAIRS VREG RX 3 6 1 PHY 2 GND + + - - RJ-45 4 TX 5 7 -48V 8 POWER-OVER SPAIR PAIRS DC-DC CONVERTER GND V+ RDISC 25.5kΩ R1* 1 60V 68nF 2 R2* -48V RCL UVLO GND RCLASS 3 GATE 4 VEE PGOOD 8 MAX5014 COUT 7 GND SS_SHDN MAX5940B PGOOD OUT 6 5 CGATE *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR. Figure 4. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs) 10 VREG ______________________________________________________________________________________ LOAD IEEE 802.3af PD Interface Controller For Power-Over-Ethernet Application Circuit 2 the power-over-ethernet. R3 provides the GATE current flow path. The wall adapter power pollutes the discovery signature, preventing PSE from detecting this PD. Diode D1 prevents the power-over-ethernet to back drive the wall adapter. Whenever the wall adapter power is available, the GATE is pulled low to pinch off DC-DC CONVERTER V+ GND RDISC 25.5kΩ 60V 1 UVLO GND 8 COUT MAX5014 VREG R3 10kΩ 68nF 2 RCL RCLASS 3 GATE 4 VEE -48V PGOOD 7 GND SS_SHDN MAX5940B PGOOD OUT 6 LOAD 5 CGATE WALL ADAPTER SUPPLY D1 Figure 5. Adding Wall Adapter Input Supply (Wall Adapter Supply Takes Precedence Over Power-Over-Ethernet) ______________________________________________________________________________________ 11 MAX5940A/MAX5940B Typical Application Circuits (continued) MAX5940A/MAX5940B IEEE 802.3af PD Interface Controller For Power-Over-Ethernet Typical Application Circuits (continued) R4 provides the 10mA minimum power maintenance signature to keep the power-over-ethernet from disconnecting. Application Circuit 3 D2 prevents the wall adapter power from polluting the discovery and classification signatures. The optional DC-DC CONVERTER D2 V+ GND RDISC 25.5kΩ 60V 1 68nF 2 UVLO GND RCLASS PGOOD 8 VREG R4 4kΩ 2W MAX5014 COUT 7 GND RCL 3 GATE 4 VEE -48V MAX5940B PGOOD OUT SS_SHDN LOAD 6 5 CGATE WALL ADAPTER SUPPLY D1 Figure 6. Adding Wall Adapter Input Supply (Wall Adapter Supply And Power-Over-Ethernet Co-Exist, the One with Higher Voltage Provides Power To The Load) 12 ______________________________________________________________________________________ IEEE 802.3af PD Interface Controller For Power-Over-Ethernet fication signatures. If the power-over-ethernet comes up first, it powers the load until taken over by a wall adapter with higher output voltage. Application Circuit 4 If the wall adapter supply comes up first, it provides power to the load and pollute the discovery and classi- DC-DC CONVERTER V+ GND RDISC 25.5kΩ 60V 1 68nF 2 UVLO GND RCLASS PGOOD 8 VREG COUT MAX5014 7 GND RCL 3 GATE 4 VEE -48V SS_SHDN MAX5940B PGOOD OUT LOAD 6 5 CGATE WALL ADAPTER SUPPLY D1 Figure 7. Adding Wall Adapter Input Supply (the One with Higher Voltage Provides Power to the Load) ______________________________________________________________________________________ 13 MAX5940A/MAX5940B Typical Application Circuits (continued) IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B Typical Operating Circuits (continued) D1* DC-DC CONVERTER GND RDISC 25.5kΩ V+ R1** 1 60V 68nF 2 RCL R2** D2* 3 UVLO RCLASS GATE 4 -48V GND VEE PGOOD MAX5940B PGOOD OUT 8 MAX5014 COUT 7 GND SS_SHDN VREG LOAD 6 5 CGATE *OPTIONAL. **R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR. Pin Configurations Chip Information TRANSISTOR COUNT: 3,643 PROCESS: BiCMOS TOP VIEW N.C. 1 8 GND RCLASS 2 7 N.C. 3 6 PGOOD VEE 4 5 OUT 8 GND 7 PGOOD 3 6 PGOOD VEE 4 5 OUT MAX5940A GATE SO UVLO 1 RCLASS 2 MAX5940B GATE SO 14 ______________________________________________________________________________________ IEEE 802.3af PD Interface Controller For Power-Over-Ethernet N E H INCHES MILLIMETERS MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050 MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 SOICN .EPS DIM A A1 B C e E H L 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D MIN 0.189 0.337 0.386 MAX 0.197 0.344 0.394 MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC D C A B e 0 -8 A1 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .150" SOIC APPROVAL DOCUMENT CONTROL NO. 21-0041 REV. B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5940A/MAX5940B Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)