IRF IRF7901D1

PD- 93844B
IRF7901D1
• Co-Pack Dual N-channel HEXFET Power MOSFET
and Schottky Diode
• Ideal for Synchronous Buck DC-DC
Converters Up to 5A Peak Output
• Low Conduction Losses
• Low Switching Losses
• Low Vf Schottky Rectifier
Q1
S ource
Q1
Gate
SO-8
Dual FETKY™
Co-Packaged Dual MOSFET Plus Schottky Diode
Device Ratings (Max.Values)
Q1
1
8
Pwr
Vin
2
7
Pwr
Vin
PGND
3
6
Pwr
Vout
Q2
Gate
4
5
Pwr
Vout
T op View
Q2
and Schottky
VDS
30V
30V
RDS(on)
38 mΩ
32 mΩ
QG
10.5 nC
18.3 nC
Qsw
3.8 nC
9.0 nC
VSD
1.0V
0.52V
Description
The FETKY™ family of Co-Pack HEXFETMOSFETs and Schottky diodes offers the designer an innovative,
board space saving solution for switching regulator and power management applications. Advanced
HEXFETMOSFETs combined with low forward drop Schottky results in an extremely efficient device suitable
for a wide variety of portable electronics applications.
The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple
die capability making it ideal in a variety of power applications. With these improvements, multiple devices can
be used in an application with dramatically reduced board space. Internal connections enable easier board
layout design with reduced stray inductance.
Absolute Maximum Ratings
Parameter
Symbol
IRF7901D1
Drain-Source Voltage
VDS
30
Gate-Source Voltage
VGS
±20
ID
6.2
Continuous Output
TL = 100°C
Units
V
A
Current (VGS ≥ 4.5V)„
IDM
24
PD
2.0
W
TJ, TSTG
–55 to 150
°C
ISM
12
A
Parameter
Maximum Junction-to-Ambientƒ
RθJA
Max.
62.5
Units
°C/W
Maximum Junction-to-Lead…
RθJL
25
°C/W
Pulsed Drain Current
Power Dissipationƒ
TL = 100°C
Junction & Storage Temperature Range
Pulsed Source Current 
Thermal Resistance
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IRF7901D1
Electrical Characteristics
Parameter
Q1 - Control FET
Q2 - Synch FET
& Schottky
Min
Typ
Max
Min
Typ
Max Units
Conditions
Drain-to-Source
Breakdown Voltage*
BVDSS
30
–
–
30
–
–
V
VGS = 0V, ID = 250µA
Static Drain-Source
on Resistance*
RDS(on)
–
28
38
–
23
32
mΩ
VGS = 4.5V, ID = 5A‚
Gate Threshold Voltage* VGS(th)
1.0
–
–
1.0
–
–
V
VDS = VGS, ID = 250µA
–
–
30
–
–
30
µA
VDS = 24V, VGS = 0
–
–
0.15
–
–
4.3
mA
VDS = 24V, VGS = 0, TJ = 125°C
–
–
±100
–
–
±100
nA
VGS = ±20V
QG cont
–
7.6
10.5
–
15.5
21.0
VGS = 5V, VDS = 16V, ID = 5A
VGS = 5V, VDS= 100mV, ID = 5A
Drain-Source Leakage
I DSS
Gate-Source Leakage
Current*
I GSS
Total Gate Charge*
QG synch
–
6.7
9.0
–
13.5
18.3
Pre-Vth
Gate-Source Charge
QGS1
–
2.0
–
–
5.5
–
Post-Vth
Gate-Source Charge
QGS2
–
0.5
–
–
0.9
–
Gate to Drain Charge
QGD
–
1.9
–
–
4.7
–
Switch Charge*
(Qgs2 + Qgd)
Q sw
–
2.4
3.8
–
5.6
9.0
Output Charge*
Q oss
–
13.5
18.0
–
9.0
12.3
Gate Resistance
RG
–
3.4
–
–
4.3
–
Input Capacitance
C iss
–
780
–
–
1810
–
Output Capacitance
C oss
–
430
–
–
310
–
Transfer Capacitance
C rss
–
30
–
–
110
–
Turn-On Delay Time
td(on)
–
7.2
–
–
10.4
–
Rise Time
tr
–
13.8
–
–
16.4
–
Turn-Off Delay Time
td(off)
–
14.7
–
–
14.6
–
Fall Time
tf
–
8
–
–
5.2
–
VDS = 16V, ID = 5A
nC
VDS = 16V, VGS = 0
Ω
pF
VDS = 16V, VGS = 0, f = 1MHz
ns
Clamped inductive load
VDD = 16V, ID = 5A, VGS = 5V
See test diagram Fig 17.
Source-Drain Ratings and Characteristics
Q1
Parameter
Diode Forward
Voltage*k
VSD
Min
–
Typ
0.7
Max
1.0
Reverse Recovery
Charge
Qrr
–
62.3
–

‚
ƒ
Q2 &
parallel Schottky
Min Typ Max Units
Conditions
–
0.48 0.52
V IS = 1A, VGS = 0V
–
m
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width ≤ 300 µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board, t < 10 sec.
…
*
2
8.9
–
nC
dl/dt = 700A/us
VDS = 16V, VGS = 0V, IS = 5A
Combined Q1, Q2 IRMS @ Pwr Vout pins. Calculated continuous
current based on maximum allowable junction temperature;
switching or other losses will decrease RMS current capability
When mounted on IRNBPS2 design kit. Measured as device TJ
to Pwr leads (Vin & Vout)
Devices are 100% tested to these parameters.
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IRF7901D1
Power MOSFET Optimization for DC-DC Converters
Table 1 and Table 2 describes the event during the various charge segments and shows an approximation of losses during
that period.
Table 1 – Control FET Losses
Description
Segment Losses
Conduction Losses associated with MOSFET on time. IRMS is a function of load
2
P COND = I RMS × R DS (on )
current and duty cycle.
Loss
Gate Drive Losses associated with charging and discharging the gate of the
PIN = VG × QG × ƒ
Loss
MOSFET every cycle. Use the control FET QG.
Q
Switching Losses during the drain voltage and drain current transitions for every full
PQGS 2 ≈ VIN × IL × GS 2 × ƒ
Loss
cycle.
IG
Losses occur during the QGS2 and QGD time period and can be simplified by
Q
PQGD ≈ VIN × IL × GD × ƒ
using Qswitch.
IG
PSWITCH ≈ VIN × IL
Output
Loss
Losses associated with the QOSS of the device every cycle when the control
FET turns on. Losses are caused by both FETs, but are dissipated by the
control FET.
POUTPUT =
Q SW
׃
IG
QOSS
× VIN × ƒ
2
Table 2 – Synchronous FET Losses
Conduction
Loss
Gate Drive
Loss
Switching
Loss
Output
Loss
Description
Losses associated with MOSFET on time. IRMS is a function of load current and
duty cycle.
Losses associated with charging and discharging the gate of the MOSFET
every cycle. Use the Sync FET QG.
Generally small enough to ignore except at light loads when the current
reverses in the output inductor. Under these conditions various light load
power saving techniques are employed by the control IC to maintain switching
losses to a negligible level.
Losses associated with the QOSS of the device every cycle when the control FET
turns on. They are caused by the synchronous FET, but are dissipated in the
control FET.
Segment Losses
PCOND = IRMS × RDSon
2
PIN = VG × QG × ƒ
PSWITCH ≈ 0
POUTPUT =
QOSS
× VIN × ƒ
2
Typical Application
The performance of the new Dual FETKYTM has been tested in-circuit using IR’s new IRNBPS2 “Dual Output
Synchronous Buck Design Kit”, operating up to 21Vin and 5A peak output current, with operating voltages from
1Vout to 5Vout.
Pin 1
Q1 Source
Pin 5&6
Pwr Vout
Shaded area = Dual FETKY
Pin 7&8
Pwr Vin
Q1
Vin
Pin 2
Q1 Gate
Q2
Pin 4
Q2 Gate
Vout
Schottky
Pin 3
PGND
Figure 1: Synchronous Buck dc-dc
Topology
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IRF7901D1
Typical Application (Contd.)
The Dual FETKY integrates all the power semiconductor devices for DC-DC conversion within one SO-8
package, as shown on page 1. The high side control MOSFET (Q1) is optimized for low combined Qsw and
RDS(on). The low side synchronous MOSFET (Q2) is optimized for low RDS(on) and high Cdv/dt immunity. The
ultra-low Vf schottky diode is internally connected in parallel with the synchronous MOSFET, for improved
deadtime efficiency. For ease of circuit board layout, the Dual FETKY has been internally configured such that
it represents a functional block for the power device portion of the synchronous buck DC-DC converter. This
helps to minimize the external PCB traces compared to a discrete solution.
In-Circuit Efficiency
The in-circuit efficiency curves for the Dual FETKY are shown in Figure 2 & 3. The Dual FETKY can
achieve up to 96.6% and 94.6% peak efficiency for the 5.0V and 3.3V applications respectively, with
excellent maximum load efficiency.
IRF7901D1 Dual FETKYTM performance in Synchronous Buck
DC-DC for 1.0Vout @ 300kHz, using IRNBPS2 design kit
IRF7901D1 Dual FETKYTM performance in Synchronous Buck
DC-DC for 3.3V out & 5.0V out @ 300kHz, using IRNBPS2 design kit
90%
97%
88%
86%
84%
Efficiency (%)
Efficiency (%)
95%
93%
10.8Vin / 3.3Vout
14Vin / 3.3Vout
21Vin / 3.3Vout
10.8Vin / 5.0Vout
14Vin / 5.0Vout
21Vin / 5.0Vout
91%
82%
80%
78%
76%
8.4Vin / 1.0Vout
74%
14Vin / 1.0Vout
72%
70%
89%
1
1.5
2
2.5
3
3.5
4
4.5
5
1.5
2
2.5
3
Output Current (A)
Figure 2. IRF7901D1 Dual FETKYTM electrical efficiency
at 3.3Vout & 5.0Vout.
Q1 - Control FET
4.5
5
Typical Characteristics
Q2 - Synchronous FET & Schottky
1.50
VGS = 4.5V
1.5
1.0
ID = 5.0A
VGS = 4.5V
1.25
(Normalized)
R DS(on) , Drain-to-Source On Resistance
ID = 5.0A
(Normalized)
R DS(on) , Drain-to-Source On Resistance
4
Figure 3. IRF7901D1 Dual FETKYTM electrical efficiency
at 1.0Vout.
2.0
1.00
0.75
0.5
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Figure 4. Normalized On-Resistance vs Junction
Temperature
4
3.5
Output Current (A)
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Figure 5. Normalized On-Resistance vs Junction
Temperature
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IRF7901D1
Typical Characteristics
Q2 - Synchronous FET & Schottky
Q1 - Control FET
6.0
6.0
ID= 5.0A
VGS, Gate-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
VDS = 16V
4.0
2.0
0.0
ID= 5.0A
VDS = 16V
4.0
2.0
0.0
0.0
2.0
4.0
6.0
8.0
0
4
QG, Total Gate Charge (nC)
0.05
0.04
ID = 5.0A
0.03
0.02
4.0
5.0
6.0
7.0
8.0
9.0
0.025
0.020
ID = 5.0A
0.015
0.010
4.0
10.0
5.0
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
9.0
10.0
VGS
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.0V
BOTTOM 0.0V
TOP
10
0.0V
250µs PULSE WIDTH
Tj = 25°C
0
0.8
1.2
1.6
2.0
VSD
, Source-To-Drain Voltage (V)
DS , Drain-toSource Voltage (V)
Figure 10. Typical Reverse Output Characteristics
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8.0
DS
50
VGS
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.0V
BOTTOM 0.0V
TOP
0.4
7.0
Figure 9. Typical R (on) vs Gate-to-Source Voltage
DS
0.0
6.0
VGS, Gate -to -Source Voltage (V)
Figure 8. Typical R (on) vs Gate-to-Source Voltage
20
16
0.030
VGS, Gate -to -Source Voltage (V)
30
12
Figure 7. Gate-to-Source Voltage vs Typical Gate
Charge
RDS(on) , Drain-to -Source On Resistance (Ω)
RDS(on) , Drain-to -Source On Resistance ( Ω )
Figure 6. Gate-to-Source Voltage vs Typical Gate
Charge
3.0
8
QG, Total Gate Charge (nC)
40
30
20
0.0V
10
250µs PULSE WIDTH
Tj = 25°C
0
0.0
0.4
0.8
1.2
VVSD, Source-To-Drain
Voltage (V)
DS , Drain-toSource Voltage (V)
Figure 11. Typical Reverse Output Characteristics
5
IRF7901D1
Typical Characteristics
Q2 - Synchronous FET & Schottky
Q1 - Control FET
30
50
VGS
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.0V
BOTTOM 0.0V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
20
10
0.0V
250µs PULSE WIDTH
Tj = 150°C
0
0.0
VGS
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.0V
BOTTOM 0.0V
TOP
TOP
0.4
0.8
1.2
1.6
40
30
20
0.0V
10
250µs PULSE WIDTH
Tj = 150°C
0
2.0
0.0
VVSD, Source-To-Drain
Voltage (V)
DS , Drain-toSource Voltage (V)
Figure 12. Typical Reverse Output Characteristics
100.00
0.8
1.2
Figure 13. Typical Reverse Output Characteristics
100.00
ID, Drain-to-Source Current (Α)
ID, Drain-to-Source Current (Α)
0.4
VV
, Source-To-Drain Voltage (V)
SD
DS , Drain-toSource Voltage (V)
T J = 150°C
10.00
1.00
TJ = 25°C
10.00
T J = 150°C
1.00
T J = 25°C
VDS = 10V
250µs PULSE WIDTH
0.10
VDS = 10V
250µs PULSE WIDTH
0.10
2.0
2.5
3.0
3.5
4.0
4.5
2.5
VGS, Gate-to-Source Voltage (V)
3.0
3.5
4.0
4.5
VGS, Gate-to-Source Voltage (V)
Figure 14. Typical Transfer Characteristic
Figure 15. Typical Transfer Characteristic
Thermal Response (Z thJA )
100
D = 0.50
0.20
10
0.10
0.05
PDM
0.02
1
0.01
t1
t2
Notes:
1. Dutyfactor D =
t 1/ t 2
2. PeakT J = P DM x Z thJA + T A
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Figure 16. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
6
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IRF7901D1
Figure 17. Clamped Inductive Load Test Diagram and
Switching waveform.
SO-8
Package
Outline
Part Marking
Information
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7
IRF7901D1
SO-8 Tape & Reel Information
Dimensions are shown in millimeters (inches)
T E R M IN A L N U M B E R 1
1 2.3 ( .4 84 )
1 1.7 ( .4 61 )
8 .1 ( .31 8 )
7 .9 ( .31 2 )
F E E D D IR E C T IO N
33 0.0 0
(12 .9 92 )
MAX.
14 .4 0 ( .5 6 6 )
12 .4 0 ( .4 8 8 )
NOTE S :
1 . C O N T R O L LIN G D IM E N S IO N : M IL L IM E T E R .
2 . O U T L IN E C O N FO R M S T O E IA -48 1 & E IA -54 1.
Data and specifications subject to change without notice.
This product has been designed and qualified for the consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact informatin.9/01
8
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