PD- 95272 • Co-Pack Dual N-channel HEXFET® Power MOSFET and Schottky Diode • Ideal for Synchronous Buck DC-DC Converters Up to 11A Peak Output • Low Conduction Losses Co-Packaged • Low Switching Losses • Low Vf Schottky Rectifier • Lead-Free IRF7335D1PbF Dual FETKY Dual MOSFET Plus Schottky Diode Device Ratings (Typ.Values) Q1 D1 1 14 S1, D2 D1 2 G1 3 13 S1, D2 12 G2 S1, D2 4 11 S1, D2 S2 5 10 S1, D2 S2 6 9 S1, D2 S2 7 8 S1, D2 Q1 Q2 Q2 and Schottky RDS(on) 13.4 mΩ 9.6 mΩ QG 13 nC 18 nC Qsw 5.5 nC 6.4 nC VSD 1.0V 0.43V Description The FETKY™ family of Co-Pack HEXFET®MOSFETs and Schottky diodes offers the designer an innovative, board space saving solution for switching regulator and power management applications. Advanced HEXFET®MOSFETs combined with low forward drop Schottky results in an extremely efficient device suitable for a wide variety of portable electronics applications. The SO-14 has been modified through a customized leadframe for enhanced thermal characteristics and multiple die capability making it ideal in a variety of power applications. With these improvements multiple devices can be used in an application with dramatically reduced board space. Internal connections enable easier board layout design with reduced stray inductance. Absolute Maximum Ratings VDS ID @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C PD @TA = 70°C VGS EAS (6 sigma) TJ TSTG Parameter Max. Units Drain-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 30 10 8.1 81 2.0 1.3 0.02 ± 12 50 -55 to + 150 V A W W/°C V mJ °C 300 (1.6mm from case ) Thermal Resistance Symbol RθJL RθJA Parameter Junction-to-Drain Lead Junction-to-Ambient Typ. Max. Units 20 62.5 °C/W Notes through are on page 12 08/16/06 IRF7335D1PbF Electrical Characteristics Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Tem. Coefficient BVDSS Q1-Control FET Q2-Synch FET & Schottky Min Min Typ Max 30 ∆BVDSS/∆TJ 0.025 Static Drain-Source on Resistance RDS (on) Gate Threshold Voltage V GS(th) Drain-Source Leakage Current IDSS Gate-Source Leakage Current IGSS 13.4 Typ Conditions V VGS = 0V, ID = 250µA 0.033 V Reference to 25°C, ID = 1.0mA 17.5 12.8 mΩ VGS = 4.5V, ID = 10A V VDS = VGS,ID = 250µA 30 30 µA VDS = 24V, VGS = 0 0.3 10 mA VDS = 24V, VGS = 0, Tj = 125°C ±100 ±100 nA VGS = ±12V S VGS=5V, ID=8.0A, VDS=15V 1.0 9.6 1.1 Forward Transconductance gFS Total Gate Charge QG 13 Pre-Vth Gate-Source Charge Post-Vth Gate-Source Charge Q GS1 3.2 5.8 Q GS2 1.4 1.5 Gate to Drain Charge QGD 4.1 4.9 Switch Chg(Qgs2 + Qgd) Qsw 5.5 6.4 Output Charge Qoss 7.7 11 Gate Resistance RG 4.3 Turn-on Delay Time td (on) 6.8 8.8 Rise Time tr 5.9 3.3 Turn-off Delay Time td Fall Time tf Input Capacitance 21 28 20 18 10 2.6 19 17 9.1 7.0 Ciss 1500 2300 Output Capacitance Coss 310 450 Reverse Transfer Capacitance Crss 140 180 (off) Max Units 30 27 VGS=4.5V, ID=8.0A, VDS=15V nC nC 5.0 VDS = 16V, VGS = 0 Ω VDD = 16V, ID = 8.0A ns VGS = 4.5V Clamped Inductive Load pF VDS = 15V, VGS = 0 Source-Drain Rating & Characteristics Parameter Min Typ Max Min Typ Max Units D Continuous Source Current (Body Diode) IS 10 10 Pulse Source Current (Body Diode) ISM 81 81 Diode Forward Voltage VSD 1 V TJ = 25°C, IS = 1.0A,VGS= 0V Reverse Recovery Time trr 28 31 ns TJ = 125°C, IF = 8.0A, VR= 15V Reverse Recovery Charge Reverse Recovery Time Qrr trr 24 29 26 31 nC ns di/dt = 100A/µs TJ = 125°C, I F =8.0A, VR= 15V Reverse Recovery Charge Qrr 26 26 nC di/dt =100A/µs 2 1.25 0.43 0.50 A Conditions MOSFET symbol showing the intergral reverse p-n junction diode G S www.irf.com IRF7335D1PbF Typical Characteristics Q1 - Control FET 1000 Q2 - Synchronous FET & Schottky 1000 VGS 10V 5.0V 4.5V 3.0V 2.7V 2.5V 2.2V BOTTOM 2.0V VGS 12V 10V 8.0V 4.5V 3.5V 3.0V 2.5V BOTTOM 2.25V TOP 100 ID, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) TOP 10 1 2.0V 100 10 1 2.25V 20µs PULSE WIDTH Tj = 25°C 20µs PULSE WIDTH Tj = 25°C 0.1 0.1 0.1 1 10 0.1 100 1 Fig 1. Typical Output Characteristics 1000 100 VGS 10V 5.0V 4.5V 3.0V 2.7V 2.5V 2.2V BOTTOM 2.0V VGS 12V 10V 8.0V 4.5V 3.5V 3.0V 2.5V BOTTOM 2.25V TOP ID , Drain-to-Source Current (A) ID , Drain-to-Source Current (A) 100 Fig 2. Typical Output Characteristics TOP 100 10 VDS, Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) 10 2.0V 1 10 2.25V 20µs PULSE WIDTH Tj = 150°C 20µs PULSE WIDTH Tj = 150°C 1 0.1 0.1 1 10 0.1 100 1 10 100 VDS , Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 3. Typical Output Characteristics Fig 4. Typical Output Characteristics 100.0 100.0 ID , Drain-to-Source Current (Α) ID , Drain-to-Source Current (Α) T J = 150°C 10.0 T J = 25°C 1.0 0.1 VDS = 15V 20µs PULSE WIDTH 0.0 2.0 2.5 3.0 3.5 4.0 VGS , Gate-to-Source Voltage (V) Fig 5. Typical Transfer Characteristics www.irf.com T J = 150°C 10.0 T J = 25°C 1.0 VDS = 15V 20µs PULSE WIDTH 0.1 4.5 2.0 3.0 4.0 VGS , Gate-to-Source Voltage (V) Fig 6. Typical Transfer Characteristics 3 IRF7335D1PbF Typical Characteristics Q2 - Synchronous FET & Schottky Q1 - Control FET 80 80 VGS 7.5V 4.5V 3.5V 2.5V 2.0V 1.5V 1.0V BOTTOM 0.0V 60 TOP 40 BOTTOM 20 VGS 7.5V 4.5V 3.5V 2.5V 2.0V 1.5V 1.0V 0.0V ID Drain-to-Source Current (A) ID Drain-to-Source Current (A) TOP 60 40 20 20µs PULSE WIDTH Tj = 25°C 20µs PULSE WIDTH Tj = 25°C 0 0 0.0 0.4 0.8 1.2 1.6 0.0 2.0 Fig. 7. Typical Reverse Output Characteristics ID Drain-to-Source Current (A) TOP 60 BOTTOM 0.8 80 VGS 7.5V 4.5V 3.5V 2.5V 2.0V 1.5V 1.0V 0.0V 20 20µs PULSE WIDTH Tj = 150°C 60 40 20 20µs PULSE WIDTH Tj = 150°C 0.8 1.2 1.6 0 2.0 0.0 VSD Source-to-Drain Voltage (V) 0.8 1.2 1.6 2.0 Fig. 10. Typical Reverse Output Characteristics 100.0 100.0 ISD, Reverse Drain Current (A) ISD, Reverse Drain Current (A) 0.4 VSD Source-to-Drain Voltage (V) Fig. 9. Typical Reverse Output Characteristics T J = 150°C 10.0 1.0 TJ = 25°C TJ = 150°C 10.0 1.0 TJ = 25°C VGS = 0V VGS = 0V 0.1 0.1 0.0 0.4 0.8 1.2 1.6 2.0 VSD, Source-toDrain Voltage (V) Fig 11. Typical Source-Drain Diode Forward Voltage 4 2.0 VGS 7.5V 4.5V 3.5V 2.5V 2.0V 1.5V 1.0V BOTTOM 0.0V 0 0.4 1.6 TOP 40 0.0 1.2 Fig. 8. Typical Reverse Output Characteristics ID Drain-to-Source Current (A) 80 0.4 VSD Source-to-Drain Voltage (V) VSD Source-to-Drain Voltage (V) 0.0 0.4 0.8 1.2 1.6 VSD, Source-toDrain Voltage (V) Fig 12. Typical Source-Drain Diode Forward Voltage www.irf.com IRF7335D1PbF Typical Characteristics Q1 - Control FET 2500 4000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd , C ds SHORTED Crss Coss = Cgd = Cds + Cgd 1000 C ds Crss = C gd Coss = Cds + Cgd 3000 Ciss 1500 VGS = 0V, f = 1 MHZ C iss = C gs + Cgd , SHORTED 3500 C, Capacitance (pF) 2000 C, Capacitance (pF) Q2 - Synchronous FET & Schottky 2500 Ciss 2000 1500 1000 500 Coss Crss 0 0 1 Coss 500 Crss 10 1 100 10 VDS, Drain-to-Source Voltage (V) Fig 13. Typical Capacitance Vs.Drain-to-Source Voltage Fig 14. Typical Capacitance Vs.Drain-to-Source Voltage 12 12 10 I D= 8.0A VDS = 24V VDS= 15V VGS , Gate-to-Source Voltage (V) VGS , Gate-to-Source Voltage (V) ID= 8.0A 8 6 4 2 0 10 VDS = 24V VDS= 15V 8 6 4 2 0 0 5 10 15 20 25 30 0 Q G Total Gate Charge (nC) 5 10 15 20 25 30 Q G Total Gate Charge (nC) Fig. 15. Gate-to-Source Voltage vs Typical Gate Charge Fig. 16. Gate-to-Source Voltage vs Typical Gate Charge 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS (on) I D, Drain-to-Source Current (A) OPERATION IN THIS AREA LIMITED BY RDS (on) ID, Drain-to-Source Current (A) 100 VDS , Drain-to-Source Voltage (V) 100 100µsec 10 1msec 1 10msec Tc = 25°C Tj = 150°C Single Pulse 0.1 100 100µsec 10 1msec 1 10msec Tc = 25°C Tj = 150°C Single Pulse 0.1 0.1 1.0 10.0 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 17. Maximum Safe Operating Area www.irf.com 0.1 1.0 10.0 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 18. Maximum Safe Operating Area 5 IRF7335D1PbF Typical Characteristics Q2 - Synchronous FET & Schottky Q1 - Control FET 2.0 I D = 10A 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 T J , Junction Temperature (°C) 0.5 V GS = 4.5V 0.0 -60 0.025 0.020 VGS= 4.5V 0.015 0.010 40 60 0 20 40 60 80 100 120 140 160 ( °C) 0.011 VGS = 4.5V 0.010 0.009 80 0 20 40 60 80 100 ID , Drain Current (A) Fig 22. Typical On-Resistance Vs. Drain Current R DS(on) , Drain-to -Source On Resistance ( Ω) Fig 21. Typical On-Resistance Vs. Drain Current R DS(on) , Drain-to -Source On Resistance ( Ω) -20 Fig 20. Normalized On-Resistance Vs. Temperature ID , Drain Current (A) 0.03 0.015 0.02 ID = 10A 0.010 I D = 10A 0.01 0.00 0.005 2.0 4.0 6.0 8.0 10.0 VGS, Gate -to -Source Voltage (V) Fig 23. Typical On-Resistance Vs. Gate Voltage 6 -40 TJ , Junction Temperature R DS (on) , Drain-to-Source On Resistance ( Ω) R DS ( on) , Drain-to-Source On Resistance ( Ω) 0.030 20 1.0 80 100 120 140 160 Fig 19. Normalized On-Resistance Vs. Temperature 0 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance ID = 10A VGS = 4.5V (Normalized) R DS(on) , Drain-to-Source On Resistance 2.0 3.0 3.5 4.0 4.5 VGS, Gate -to -Source Voltage (V) Fig 24. Typical On-Resistance Vs. Gate Voltage www.irf.com IRF7335D1PbF 12 RD VDS ID , Drain Current (A) 10 VGS 8 D.U.T. RG + -VDD 6 V GS 4 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 2 Fig 26a. Switching Time Test Circuit VDS 0 25 50 75 100 125 90% 150 T J , Junction Temperature (°C) Fig 25. Maximum Drain Current Vs.CaseTemperature 10% VGS td(on) tr t d(off) tf Fig 26b. Switching Time Waveforms Current Regulator Same Type as D.U.T. QG VGS 50KΩ .2µF 12V QGS .3µF + V - DS D.U.T. QGD VG VGS 3mA Charge IG ID Current Sampling Resistors Fig 27a&b. Basic Gate Charge Test Circuit and Waveform 100 Thermal Response ( Z thJA ) D = 0.50 10 0.20 0.10 0.05 1 0.02 0.01 0.1 SINGLE PULSE ( THERMAL RESPONSE ) 0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100 t1 , Rectangular Pulse Duration (sec) Fig. 28. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 7 IRF7335D1PbF Schottky Diode Characteristics 100 100000 Reverse Current - I R (µA ) Instantaneous Forward Current - I F ( A ) 10000 10 Tj = 150°C 1000 125°C 100°C 100 75°C 10 50°C 1 25°C 0.1 0 5 10 15 20 25 30 Reverse Voltage - V R (V) T J = 150°C 1 T J = 125°C Fig. 30 - Typical Values of Reverse Current Vs. Reverse Voltage T J = 25°C 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Forward Voltage Drop - V F ( V ) Fig. 29 - Maximum Forward Voltage Drop Characteristics 8 www.irf.com IRF7335D1PbF D.U.T Driver Gate Drive P.W. + + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period V DD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig. 31 Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig. 32 Gate Charge Waveform www.irf.com 9 IRF7335D1PbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgs 2 Qgd ⎞ ⎛ ⎞ +⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ ig ig ⎝ ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 10 www.irf.com IRF7335D1PbF SO-14 Package Details www.irf.com 11 IRF7335D1PbF SO-14 Tape and Reel Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width ≤ 300 µs; duty cycle ≤ 2%. When mounted on 1 inch square copper board. Combined Q1,Q2 IRMS @ Pwr Vout pins. Calculated continuous current based on max allowable junction temperature; switching or other losses will decrease RMS current capability Q1 and Q2 is tested 100% in production to 50mJ to stress and eliminate potentially defective parts. This is not a design for use value. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.08/2006 12 www.irf.com