BU1924 / BU1924F Audio ICs RDS / RBDS decoder BU1924 / BU1924F The BU1924 and BU1924F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption. !Applications RDS / RBDS compatible FM receivers for American and European markets, car stereos, high-fidelity stereo systems and components, and FM pagers. !Features 1) Low current. 2) Two-stage anti-aliasing filter (LPF). 3) 57kHz band-pass filter. 4) DSB demodulation (digital PLL). 5) Quality indication output for demodulated data. !Absolute maximum ratings (Ta = 25°C) Symbol Limits Unit Power supply voltage Parameter VDD −0.3~+7.0 V VDD1 VDD2 Conditions Maximum input voltage VMax. −0.3~VDD+0.3 V All input pins Maximum output voltage IMax. ±4.0 mA All output pins Pd 350∗ mW − Operating temperature Topr −40~+85 °C − Storage temperature Tstg −55~+125 °C − Power dissipation ∗Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. !Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Symbol Min. Typ. Max. Unit VDD1 4.5 − 5.5 V VDD2 4.5 − 5.5 V BU1924 / BU1924F Audio ICs !Block diagram 560p CMP MUX 100kΩ (4) 270p 120kΩ VSS3 100kΩ (8) 8th Switched capacitor filter comparator anti-aliasing filter (3) Vref (7) (16) RCLK 2.2µF VDD1 (5) ∗1 VSS1 (6) VDD2 (12) ∗2 Digital Power supply (1) PLL 57kHZ RDS/ARI Bi-phase decoder PLL 1187.5Hz Differential decoder (2) (11) VSS2 Measurement circuit Reference clock (13) (14) XI (10) (9) XO T2 T1 4.332MHZ XO XI VDD2 VSS2 T1 T2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Vref MUX VDD1 VSS1 VSS3 CMP ∗3 (N.C.) ∗3 ∗1 : VDD1 and VDD2 are separated within the IC. ∗2 : Have VDD2 (digital power supply) of a sufficiently low impedance. ∗3 : Match the capacitor constants with the crystal manufacturer. RDATA 33pF RCLK 33pF QUAL ∗1 Analog Power supply QUAL RDATA BU1924 / BU1924F Audio ICs !Pin descriptions Pin No. Symbol 1 QUAL Pin name Functions 2 RDATA Demodulator data Refer to output data timing 3 Vref Reference voltage 1/2 VDD1 (refer to input/output circuits) Type E Input Composite signal input (refer to input/output circuits) Type D 4 MUX 5 VDD1 6 VSS1 7 VSS3 GND 8 CMP Comparator input 9 T2 10 T1 11 VDD2 12 VSS2 13 XI 14 XO Input/Output type Demodulator quality Good data : High, bad data : Low Type C − − Analog power supply 4.5V to 5.5V − − Test input Digital power supply C-junction (refer to input/output circuits ) Type D Open or connected to ground Type B − 4.5V to 5.5V Connects to 4.332MHz oscillator (refer to input/output circuits) Crystal oscillator 15 (N.C.) − 16 RCLK Demodulator clock Type A − − 1187.5Hz clock (refer to the timing diagram) !Input / Output circuits Type A Type B 10MΩ Type D Type E + + − Type C Type C BU1924 / BU1924F Audio ICs !Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD1 = VDD2 = 5.0V, VSS1 = VSS2 = 0.0V) Parameter Symbol Min. Typ. Max. Unit Conditions Operating current IDD − 4.5 7.0 mA Reference voltage Vref − 1/2VDD1 − V Pin 3 Input current 1 Output current 1 IDD1+IDD2 IIN1 − − 1.0 µA MUX VIN=VDD1 IOUT1 − − 1.0 µA MUX VIN=VDD1 IIN2 − − 1.0 µA XI VIN=VDD2 Output current 2 IOUT2 − − 1.0 µA XI VIN=VDD2 Output high level voltage 1 VOH1 VDD2 −1.0 VDD2 −0.3 − V RCLK RDATA QUAL IO=−1.0mA Output low level voltage 1 VOL1 − 0.2 1.0 V RCLK RDATA QUAL IO=1.0mA FC 56.5 57.0 57.5 kHz Input current 2 〈Filter block〉 Center frequency GA 20 23 26 dB F=57.0kHz Attenuation 1 ATT1 18 22 − dB 57kHz±4kHz Attenuation 2 ATT2 65 80 − dB 38kHz Attenuation 3 ATT3 35 50 − dB 67kHz SN 30 40 − dB 57kHz VIN=3mVrms − − 500 mVrms Gain S / N ratio Maximum input level VMAX1 〈Demodulator〉 RDS detector sensitivity SRDS − 0.5 1.0 mVrms RDS input level MRDS 1.0 − 300 mVrms SARI − 1.5 3.0 mVrms DRATE − 1187.5 − Hz CT − 4.3 − µs ARI detector sensitivity Data rate Clock transient vs. data Not designed for radiation resistance. !Output data timing RCLK RDATA T1 T5 T1=T2=4.3µS T1 T3 T3=T4=421µS T4 T2 T6 T2 T5=T6=416.7µS The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced in synchronous with either the rising or falling or falling edge of the clock. To read the data, you may choose either the rising or falling edge of the clock as the reference. The data is valid for 416.7µs. after the reference clock edge. QUAL pin operation : Indicates the quality of the demodulated data. (1) Good data : HI (2) Poor data : LO BU1924 / BU1924F Audio ICs !Electrical characteristic curves 30 20 FILTER GAIN : G (dB) 10 0 −10 −20 −30 −40 −50 −60 −70 10 20 30 40 50 60 70 80 90 100 FREQUENCY : f (kHz) Fig.1 Band-pass filter characteristics !External dimensions (Units : mm) BU1924 BU1924F 10.0±0.2 19.4±0.3 9 2.54 0.5±0.1 0°~15° 9 1 8 1.27 0.4±0.1 0.15±0.1 6.2±0.3 0.3±0.1 16 4.4±0.2 7.62 1.5±0.1 8 0.51Min. 3.2±0.2 4.25±0.3 1 0.11 6.5±0.3 16 0.3Min. 0.15 DIP16 SOP16