Memory for Plug & Play
I2C BUS3Ports for HDMI Port
Serial EEPROM
No.09002EBT01
BU9883FV-W
● Description
BU9883FV-W is for DDC 3 ports, 2K x 8 bit array 3 BANK EEPROM.
●Features
1) There are 3 BANKs, 1 BANK compose of 256 word address x 8 bit EEPROM
2) There are 3 DDC interface channels, and each channel can access each BANK independently from other ports.
3) 2K bit X 3 BANK memory bits can be accessed from write port (Port0).
4) Operate voltage (3.0V～5.5V)
5) Built in diode for power supply from HDMI ports and system.
6) Automatic erase
7) 8 byte page write mode
8) Low power consumption
Active
( 5.0V ) : 1.2mA (Typ.)
Standby ( 5.0V ) : 100μA(Max.)
9) DATA security
10) Write Protect pin can switch write port
11) Inhibit to WRITE at low VCC
12) Pin package
: SSOP16pin
13) Endurance
: 1,000,000 erase/write cycles
14) Data retention
40 years
15) Filtered inputs in all SCL・SDA for noise suppression
16) Shipment data all address FFh
●Absolute maximum rating (Ta=25℃)
Parameter
Symbol
Rating
Supply Voltage
Unit
VCC
-0.3～6.5
V
Power Dissipation
Pd
400 *1
mW
Storage Temperature
Tstg
-65 ～ 125
℃
Operating Temperature
Topr
Terminal Voltage
-40 ～ 85
-
-0.3～VCC＋0.3
℃
*1
V
*1 Degradation is done at 3.0mW/℃ for operation above 25℃
*2 The Max value of terminal voltage is not over 6.5V
●EEPROM recommended operating condition
Parameter
Symbol
Rating
Supply Voltage
VCC
3.0～5.5
Input Voltage
VIN
0 ～ VCC0～3
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© 2009 ROHM Co., Ltd. All rights reserved.
1/18
Unit
V
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Memory cell characteristics(Ta=25℃, VCC0～3 = 3.0～5.5V)
Specification
Parameter
Min.
Typ.
Max.
Unit
Write/Erase Cycle
*1
1,000,000
-
-
Cycles
Data Retention
*1
40
-
-
Years
*1:Not 100％ TESTED
●Input/output capacity (Ta=25℃, Frequency=5MHz)
Parameter
Symbol
SDA pins (SDA0,1,2,3) *1
SCL pins (SCL0,1,2,3)
*1
Min.
Typ.
Max.
Unit
Cin
-
7
-
pF
Cin2
-
7
-
pF
*1:Not 100％ TESTED
●EEPROM DC operating characteristics (Unless otherwise specified, Ta=-40～85℃, VCC0～3 = 3.0～5.5V)
Specification
Parameter
Symbol
Unit
Test condition
Min.
Typ.
Max.
"H" Input Voltage0
VIH0
0.7xVCC0
-
VCC0+0.5
V
3.0≦VCC0≦5.5V(SCL0, SDA0)
"L" Input Voltage0
VIL0
-0.3
-
0.3xVCC0
V
3.0≦VCC0≦5.5V(SCL0, SDA0)
"H" Input Voltage1
VIH1
0.7xVCC1
-
VCC1+0.5
V
3.0≦VCC1≦5.5V(SCL1, SDA1)
"L" Input Voltage1
VIL1
-0.3
-
0.3xVCC1
V
3.0≦VCC1≦5.5V(SCL1, SDA1)
"H" Input Voltage2
VIH2
0.7xVCC2
-
VCC2+0.5
V
3.0≦VCC2≦5.5V(SCL2, SDA2)
"L" Input Voltage2
VIL2
-0.3
-
0.3xVCC2
V
3.0≦VCC2≦5.5V(SCL2, SDA2)
"H" Input Voltage3
VIH3
0.7xVCC3
-
VCC3+0.5
V
3.0≦VCC3≦5.5V(SCL3, SDA3)
"H" Input Voltage3
VIL3
-0.3
-
0.3xVCC3
V
3.0≦VCC3≦5.5V(SCL3, SDA3)
"L" Output Voltage0
VOL0
-
-
0.4
V
IOL=3.0mA , 3.0V≦VCC0≦5.5V(SDA0)
"L" Output Voltage1
VOL1
-
-
0.4
V
IOL=3.0mA , 3.0V≦VCC1≦5.5V(SDA1)
"L" Output Voltage2
VOL2
-
-
0.4
V
IOL=3.0mA , 3.0V≦VCC2≦5.5V(SDA2)
"L" Output Voltage3
VOL3
-
-
0.4
V
IOL=3.0mA , 3.0V≦VCC3≦5.5V(SDA3)
WP "H" Input Voltage
VIH4
0.7xVCC0
-
VCC0+0.3
V
3.0≦VCC0≦5.5V(WPB)
WP "L" Input Voltage
VIL4
-0.3
-
0.3xVCC
V
3.0≦VCC0≦5.5V(WPB)
Input Leakage Current0
ILI0
-1
-
1
μA
VIN=0～5.5V(SCL0～3)
Input Leakage Current1
ILI1
55
110
230
μA
WPB=5.5V , VCC=5.5V
Output Leakage Current0
ILO0
-1
-
1
μA
ICC1
-
-
2.0
mA
ICC2
-
-
1.0
mA
Standby Current
ISB0
-
-
100
μA
Standby Current
ISB1
-
-
100
μA
Standby Current
ISB2
-
-
100
μA
Standby Current
ISB3
-
-
100
μA
Operating Current
VOUT=0～5.5(SDA0～3)
VCC0=5.5V, fSCL=400kHz，tWR=5ms
Byte Write, Page Write
VCC0～3=5.5V, fSCL=400kHz
Random Read, Current Read,Sequential
Read, (each port operation)
VCC～0=5.5V, SDA0～3=SCL0～3=5.5V,
WPB=GND
VCC1=5.5V, SDA0～3=SCL0～3=5.5V,
WPB=GND
VCC2=5.5V, SDA0～3=SCL0～3=5.5V,
WPB=GND
VCC3=5.5V, SDA0～3=SCL0～3=5.5V,
WPB=GND
○This product is not designed for protection against radioactive rays.
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© 2009 ROHM Co., Ltd. All rights reserved.
2/18
2009.04 - Rev.B
BU9883FV-W
Technical Note
●EEPROM AC operating characteristics (Ta=-40～85℃, VCC0～3 = 3.0～5.5V)
3.0≦VCC0～3≦5.5V
Parameter
Symbol
Min.
Typ.
Max.
Clock Frequency
fSCL
400
Data Clock High Period
tHIGH
0.6
Data Clock Low Period
tLOW
1.2
SDA0~3 and SCL0~3 Rise Time *1
tR
0.3
SDA0~3 and SCL0~3 Fall Time*1
tF
0.3
Start Condition Hold Time
tHD:STA
0.6
Start Condition Setup Time
tSU:STA
0.6
Input Data Hold Time
tHD:DAT
0
Input Data Setup Time
tSU:DAT
100
Output Data Delay Time
tPD
0.1
0.9
Output Data Hold Time
tDH
0.1
Stop Condition Setup Time
tSU:STO
0.6
Bus Free Time
tBUF
1.2
Write Cycle Time
tWR
5
Noise Spike Width (SDA0~3 and SCL0~3)
tI
0.1
WP Hold Time
tHD:WP
0
WP Setup Time
tSU:WP
0.1
WP valid time
tHIGH:WP
1.0
-
Unit
Min.
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
*1 : Not 100% TESETED
●Synchronous data input/output timing
tR
tF
tHIGH
SCL
SCL
tHD:STA
tSU:DAT
tLOW
tSU:STA
tHD:DAT
SDA
(IN)
tHD:STA
tSU:STO
SDA
tBUF
tPD
tDH
START BIT
STOP BIT
SDA
(OUT)
Fig.-1 SYNCHRONOUS DATA TIMING
○SDA data is latched into the chip at the rising edge of the SCL clock. (This is commoness in all port.)
○Output date toggles at the falling edge of the SCL clock. (This is commoness in all port.)
●Characteristic data (The following values are Typ. ones).
6
4
3
SPEC
2
1
6
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
SPEC
2
1
0
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc0［V］
1
2
3
4
5
SUPPLY VOLTAGE : Vcc0［V］
4
SPEC
2
1
0
2
3
4
5
SUPPLY VOLTAGE : Vcc3［V］
Fig.5 'H' Input Voltage3 VIH3
(SCL3,SDA3)
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© 2009 ROHM Co., Ltd. All rights reserved.
1
6
1
2
3
4
5
SUPPLY VOLTAGE : Vcc2［V］
6
Fig.4 'H' Input Voltage2 VIH2
(SCL2,SDA2)
6
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
SPEC
1
5
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
2
SPEC
1
0
0
1
SPEC
2
0
L INPUT VOLTAGE1 : VIL1［V］
L INPUT VOLTAGE0 : VIL0［V］
Ta=-40℃
Ta=25℃
Ta=85℃
0
3
6
6
3
4
Fig.3 'H' Input Voltage1 VIH1
(SCL1,SDA1)
Fig.2 'H' Input Voltage0 VIH0
(SCL0,SDA0)
5
Ta=-40℃
Ta=25℃
Ta=85℃
5
0
0
6
6
H INPUT VOLTAGE3 : VIH3［V］
H INPUT VOLTAGE2 : VIH2［V］
Ta=-40℃
Ta=25℃
Ta=85℃
5
H INPUT VOLTAGE1 : VIH1［V］
H INPUT VOLTAGE0 : VIH0［V］
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc0［V］
Fig.6 'L' Input Voltage0 VIL0
(SCL0,SDA0)
3/18
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc1［V］
6
Fig.7 'L' Input Voltage1 VIL 1
(SCL1,SDA1)
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Characteristic data (The following values are Typ. ones).
6
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
SPEC
1
0
1
2
3
4
5
1
4
5
Fig.8 'L' Input Voltage2 VIL 2
(SCL2,SDA2)
Fig.9 'L' Input Voltage3 VIL 3
(SCL3,SDA3)
0.4
6
0
0.6
SPEC
0.4
0.2
0.8
0.6
SPEC
0.4
0.2
5
0.6
SPEC
0.4
0.2
L OUTPUT CURRENT : IOL［mA］
1
2
3
4
5
L OUTPUT CURRENT : IOL［mA］
Fig.12 'L' Output Voltage2
VOL2-IOL（Vｃｃ2＝3.0V）（SDA2）
Fig.13 'L' Outnput Voltage3
VOL3-IOL（Vｃｃ3＝3.0V）（SDA3）
1
2
3
4
5
0
6
SPEC
3
2
1
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
2
SPEC
1
0
0
0
1
2
3
4
5
6
7
0
8
1
2
L OUTPUT CURRENT : Vcc0［V］
Fig.14 WP 'H' Input Voltage VIH4
3
4
5
6
7
SUPPLYVOLTAGE : Vcc0［V］
0.8
0.4
0.2
0
8
0
2
1.5
100
SPEC
50
SPEC
1
0.5
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc［V］
0
6
Fig.17 Input Leak Current1 ILI1（WPB）
1
2
3
4
SUPPLY VOLTAGE : Vcc［V］
5
SPEC
ｆSCL=400ｋHz
Each port
operation
500
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc0～3[V]
6
Fig.20 Current Consumption at Reading Icc2
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© 2009 ROHM Co., Ltd. All rights reserved.
1
2
3
4
5
SUPPLY VOLTAGE : Vcc0［V］
6
Fig.19 Current Consumption at Reading Icc1
300
Ta=-40℃
Ta=25℃
Ta=85℃
250
200
150
SPEC
100
50
Ta=-40℃
Ta=25℃
Ta=85℃
250
200
150
SPEC
100
50
0
0
0
ｆSCL=400ｋHz
ｔWR=5ms
500
0
STANDBY CURRENT : ISB1[uA]
STANDBY CURRENT : ISB0［uA］
1000
1000
6
300
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
1500
Fig.18 OUTPUT LEAK CURRENT ILO
（SDA0～3）
1500
Ta=-40℃
Ta=25℃
Ta=85℃
2000
0
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc0～3［V］
Fig.16 Input Leak Cuｒｒｅｎｔ0 ILI0(SCL0～3)
2500
Ta=-40℃
Ta=25℃
Ta=85℃
CURRENT CONSUMPTION
AT WRITTING : Icc1［mA］
OUTPUT LEAK CURRENT1 : ILO［uA］
150
SPEC
0.6
2.5
Ta=-40℃
Ta=25℃
Ta=85℃
200
Ta=-40℃
Ta=25℃
Ta=85℃
1
Fig.15 WP 'L'Input Voltage VIL4
250
6
1.2
INPUT LEAK CURRENT0 : ILI0［uA］
Ta=-40℃
Ta=25℃
Ta=85℃
WP L INPUT VOLTAGE : VIL4［V］
5
4
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0
0
6
6
1
Ta=-40℃
Ta=25℃
Ta=85℃
0
1
2
3
4
5
L OUTPUT CURRENT : IOL［mA］
1
2
3
4
5
L OUTPUT CURRENT : IOL［mA］
Fig.10 'L' Output Voltage0
VOL0-IOL（Vcc0=3.0V）
L OUTPUT VOLTAGE3 : VOL3［V］
L OUTPUT VOLTAGE2 : VOL2［V］
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
SPEC
0.2
1
Fig.11 'L' Output Voltage1
VOL1-IOL（Vｃｃ1＝3.0V）（SDA1）
WP H INPUT VOLTAGE : VIH4［V］
3
SUPPLY VOLTAGE : Vcc2［V］
0
INPUT LEAK CURRENT0 : ILI1［uA］
2
SUPPLY VOLTAGE : Vcc3［V］
0
CURRENT CONSUMPTION
AT READING2 : Icc2［mA］
0.6
0
0
6
1
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0
0
L OUTPUT VOLTAGE1 : VOL1［V］
1
L OUTPUT VOLTAGE0 : VOL0［V］
L INPUT VOLTAGE3 : VIL3［V］
L INPUT VOLTAGE2 : VIL2［V］
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc0[V]
Fig.21 Standby Current ISB0
4/18
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc1［V］
6
Fig.22 Standby Current ISB1
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Characteristic data (The following values are Typ. ones).
1000
Ta=-40℃
Ta=25℃
Ta=85℃
150
SPEC
100
50
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc2[V]
250
200
150
SPEC
100
50
DATA CLOCK LOW PERIOD : tLOW［us］
600
SPEC
400
Ta=-40℃
Ta=25℃
Ta=85℃
100
0
0
1
2
3
4
SUPPLY VOLTAGE : Vcc[V]
5
1
200
0
800
600
Ta=-40℃
Ta=25℃
Ta=85℃
400
200
1
0
600
400
200
-20
Ta=-40℃
Ta=25℃
Ta=85℃
-40
-60
-80
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
6
120
SPEC
100
80
60
Ta=-40℃
Ta=25℃
Ta=85℃
40
20
0
0
1
2
3
4
5
SUPPLY VOLATGE : Vcc[V]
6
6
Ta=-40℃
Ta=25℃
Ta=85℃
600
SPEC
400
200
0
0
6
SPEC
Fig.31 Input Data Setup Time ｔSU:DAT
-200
0
6
0
Fig.30 Input Data Hold Time tHD：DAT
SPEC
5
Fig.28 Sｔａｒｔ Condition Hold Time ｔHD:STA
SPEC
6
STOP CONDITION SETUP TIME
: tSU :STO［us］
OUTPUT DATA DELAY TIME : tPD［us］
800
4
200
800
Ta=-40℃
Ta=25℃
Ta=85℃
3
400
6
20
Fig.29 Start Condition Setup
Time tSU:STA
Fig.32 Output Data Delay Time ｔPD
1
2
3
4
5
SUPPLYVOLTAGE : Vcc[V]
6
Fig.33 Stop Condition Setup Time tSU：STO
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
SPEC
3
2
1
0
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc[V]
6
Fig.34 Write Cycle Time tWR
200
400
Ta=-40℃
Ta=25℃
Ta=85℃
300
WP SET UPTIME : tSU : WP［us］
NOISE SPIKE WIDTH
(SDA0～3 and SCL0～3) : tI［us］
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
Ta=-40℃
Ta=25℃
Ta=85℃
600
0
1000
2
Fig.25 Clock Frequency fSCL
SPEC
1000
INPUT DATA HOLD TIME : tHD:DAT［ns］
START CONDITION
SETUP TIME : tSU:STA［us］
Ta=-40℃
Ta=25℃
Ta=85℃
1
SUPPLY VOLTAGE : Vcc[V]
Fig.27 Data Clock Low Period tLOW
600
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
0
6
800
0
SPEC
1
5
1200
6
800
0
2
3
4
SUPPLY VOLTAGE : Vcc3[V]
1400
Fig.26 Data Clock Hｉｇｈ Period tHIGH
400
200
Write Cycle Time TIME : tWR［ms］
DATA CLOCK HIGH PERIOD : tHIGH［us］
700
200
SPEC
400
Fig.24 Standby Current ISB3
800
300
600
0
0
Fig.23 Standby Current2 ISB2
500
Ta=-40℃
Ta=25℃
Ta=85℃
800
0
6
START CONDITION HOLD
TIME : tHD:STA［us］
200
Ta=-40℃
Ta=25℃
Ta=85℃
ＩＮＰＵＴ DATA SETUP TIME : tSU:DAT［ns］
250
CLOCK FREQUENCY : ｆSCL［ｋHz］
300
STANDBY CURRENT : ISB3[uA]
STANDBY CURRENT : ISB2[uA]
300
200
100
SPEC
0
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc[V]
6
Fig.35 Noise Spike Width tI
(SDA0～3 and SCL0～3)
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© 2009 ROHM Co., Ltd. All rights reserved.
Ta=-40℃
Ta=25℃
Ta=85℃
100
SPEC
0
-100
-200
-300
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc[V]
Fig.36 WP Setup Time tSU:WP
5/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Pin configuration
Vcc1
1
16
Vcc2
SCL1
2
15
SCL2
SDA1
3
14
SDA2
WPB
4
13
N.C
VCC OUT
5
12
GND
SDA0
6
11
SDA3
SCL0
7
10
SCL3
Vcc0
8
9
Vcc3
BU9883FV-W
Fig.37 Pin configuration
●PIN NAME
PIN No.
PIN NAME
I/O
1
VCC1
-
2
SCL1
Input
3
SDA1
Input /output
4
WPB
Input
5
VCC OUT
-
6
SDA0
Input /output
7
SCL0
Input
8
VCC0
-
Power Supply
9
VCC3
-
Power Supply
10
SCL3
Input
11
SDA3
Input /output
12
GND
-
13
N.C
-
14
SDA2
Input /output
15
SCL2
Input
16
VCC2
-
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© 2009 ROHM Co., Ltd. All rights reserved.
FUNCTIONS
Power Supply
Serial clock input
Slave and word address, Serial data input serial data output
Write protect terminal(1 : Write enable, 0 : Write disable)
Terminal of diode. Connect Bypass capacitor.
Slave and word address, Serial data input serial data output
Serial clock input
Serial clock input
Slave and word address, Serial data input serial data output
Reference voltage of all input / output
Non connect terminal.
Don’t connect each other.
Slave and word address, Serial data input serial data output
Serial clock input
Power Supply
6/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●BLOCK DIAGRAM
Vcc1
Voltage
Detect
Logic
Vcc2
Vcc3
Vcc0
VCC OUT
LDO
Low Voltage
Logic
WPB
Port １
SCL1
EN
I/O
LEVEL
(PORT1)
Shifter
CONTROL
WR
BANK0
RD
(2Kbit EEPROM)
RD
SDA1
Port 0
Port 2
SCL2
EN
I/O
(PORT2)
LEVEL
WR
BANK1
RD
CONTROL
Shifter
CONTROL
(2Kbit EEPROM)
I/O
Shifter
(PORT0)
SCL0
SCL0
SDA0
RD
SDA2
EN
LEVEL
SDA0
Port ３
SCL3
EN
I/O
LEVEL
(PORT3)
Shifter
WR
BANK2
CONTROL RD
(2Kbit EEPROM)
RD
SDA3
Fig.38
BLOCK DIAGRAM
HDMI Sink
0.1uF
PWR_HDMI1
DDC_SCL1
PWR_SYS
Vcc1
47KΩ
Vcc0
47KΩ
SCL1
μ Controller
0.1uF
SDA1
DDC_SDA1
WPB_OUT
WPB
0.1uF
ROHM Vcc OUT
PWR_HDMI2
DDC_SCL2
I2C_SCL
Vcc2 BU9883FV-W
47KΩ
I2C_SDA
0.1uF
47KΩ
SCL2
SDA2
DDC_SDA2
0.1uF
SCL0
PWR_HDMI3
DDC_SCL3
DDC_SDA3
Vcc3
47KΩ
SDA0
47KΩ
SCL3
GND
SDA3
HDMI
Receiver
SDA3
SCL3
SDA2
HDMI
SCL2
Switch
SDA1
SCL_SINK
DDC_SCL
SDA_SINK
DDC_SDA
SCL1
Fig.39 Application circuit
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© 2009 ROHM Co., Ltd. All rights reserved.
7/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●WRITE CYCLE TIMING
SCL0
SDA0
D0
ACK
tWR
WRITE DATA(n)
STOP CONDITION
START CONDITION
Fig.40 WRITE CYCLE TIMING
●WRITE OPERATION
BU9883FV-W has 2K bit EEPROM in each port, there are three BANKs, 6K bit EEPROM in this device.
Each BANK EEPROM can be written through PORT0.
There is no write operation through PORT1,2,3.
When this device is accessed throgh PORT0, WPB terminal must be set to “HIGH”.
Table1 Access port and write enable BANK
Port0
BANK1～3
Port1
No write operation
Port2
No write operation
Port3
No write operation
●READ OPERATION
Each BANK EEPROM can be read through each port.
The relation ship of access port and access BANK is describe Table2.
Table 2
Table 3
Port0
BANK1～3
Port0
Port1
No write operation
Port1
Port2
No write operation
Port2
Port3
No write operation
Port3
BANK1～3
BANK1
BANK2
BANK3
○When EEPROM access through PORT0, P1, P0 bits in slave address appoint access BANK.
Table 4
P1
P0
P1,P0 bit and access BANK
0
0
No bank selected
0
1
BANK1
1
0
BANK2
1
1
BANK3
Note) When P1=0, P0=0 : this device doesn’t return Acknowlege.
○During PORT0 access, WPB terminal must be set to “HIGH”, then PORT1～3 accesses will be cancelled.
○In accessing from PORT1～3, set WPB termianl to “LOW”
●DEVICE OPERATION
○START CONDITION
・All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA0～3 when SCL0～3 is
HIGH.
・This device continuously monitors the SDA0～3 and SCL0～3 lines for the start condition and will not respond to any
command until this condition has been met.
○STOP CONDITION
・All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA0～3when SCL0
～3 is HIGH.
・The stop condition initiates internal write cycle to write the data into memory array after write sequence.
・The stop condition is also used to place the device into the standby power mode after read sequence.
・A stop condition can only be issued after the transmitting device has released the bus.
○NOTICE ON WRITE COMMAND
・In Write command, after transmit write data, if there are no stop condition, EEPROM data don’t change.
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8/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
○DEVICE ADDRESSING
・Following a START condition, the master output the device address of the slave to be accessed.
The most significant four bits of the slave address are the “device type indentifier,” for this device, this is fixed as “1010.”
The next three bit specify a particular device. For PORT0 access, that are set “0”, “P1”, “P0”, for PORT 1～3 access, that
must be set “000”.
The last bit of the stream determines the operation to be performed.
When set to “1” a read operation is selected ; when set to “0,” a write operation is selected.
R/W set to “0” ･ ･ ･ ･ ･ ･ ･ ･ WRITE
R/W set to “1” ･ ･ ･ ･ ･ ･ ･ ･ READ
○ACKNOWLEDGE
・Acknowledge is a software convention used to indicate successful data transfers.The master or the slave will release the
bus after transmitting eight bits.During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledgethat
the eight bits of data has been received.
・This device will respond with an Acknowledge after recognition of a START condition and its slave address.If both the
device and a write operation have been selected, this device will respond with an Acknowledge, after the receipt of each
subsequent 8-bit word.
・In the READ mode, this device will transmit eight bit of data, release the SDA line, and monitor the line for an
Acknowledge.
・If an Acknowledge is detected, and no STOP condition is generated by the master, this device will continue to transmit
the data.
・If an Acknowledge is not detected, this device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
・This device dosen't return Acknouwedge in internal write cycle.
START CONDITION
(START BIT)
SCL
（Fromμ-COM）
1
8
9
SDA
（μ-COM
OUTPUT DATA)
SDA
（IC OUTPUT DATA）
Acknowledge Signal
(ACK Signal)
Fig.41 ACKNOWLEDGE RESPONSE FROM RECEIVER
●PORT0 access commands
○For PORT0 access, WPB terminal must be set to “HIGH”.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1
0
0
1st WORD
ADDRESS(n)
WA7
P1 P0
R
/
W
S
T
O
P
DATA(n)
WA0
D7
D0
A
C
K
A
C
K
WPB
Fig.42 BYTE WRITE CYCLE TIMING (PORT0)
○This write commands operate EEPROM write sequence at address which is appointed by P1, P0. When the master
generates a STOP condition, this device begins the internal write cycle to the nonvolatile array.
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2009.04 - Rev.B
Technical Note
BU9883FV-W
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1
0
0
1st WORD
ADDRESS(n)
P1 P0
R
/
W
D7
WA0
WA7
A
C
K
S
T
O
P
DATA(n+7)
DATA(n)
D0
D0
A
C
K
A
C
K
A
C
K
WPB
Fig.43 PAGE WRITE CYCLE TIMING (PORT0)
○This device is capable of eight byte page write operation.
○After the receipt of each word, the three low order address bits are internally incremented by one. The most
significant address bits (WA7～WA3) remain constant, if the master transmits more than 8 words.
○The relationship of P1, P0 inputs and access BANK is described as follows.
P1
0
0
1
1
P0
0
1
0
1
BANK
No opearation
BANK1
BANK2
BANK3
○Don't set P1, P0=0, 0. If P1, P0 are set to 0, there is no target bank, so this device doesn't return cknowlege.
○WPB terminal must be set to “HIGH” during Byte Write cycle, and Page Write cycle, and internal Write cycles. If WPB is
set to “LOW” in above condition, programing doesn't work, and during internal Write cycle, WPB terminal set to “LOW”,
this device terminate programing, and the data in programing address is not stored correctly.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1
0 1 0
0
WA7
P1 P0
R
/
W
S
T
A
R
T
1st WORD
ADDRESS(n)
1
WA0
A
C
K
R
E
A
D
SLAVE
ADDRESS
0 1 0
0
A
C
K
D7
P1 P0
S
T
O
P
DATA(n)
D0
A
C
K
R A
/ C
W K
WPB
Fig.44 RANDOM READ CYCLE TIMING（PORT0）
○Random read operation allows the master to access any memory location which is appointed by P1, P0 bit.
This operation involves a two-step process.
First, the master issue a write command which includes the start condition and the slave address field (with R/W set to “0”)
followed by the address of the word be read.
This procedure sets the internal address counter of this device to the desired address. After the word address
acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address
field with R/W the set to “1.” This device will respond with an acknowledge and then transmit the 8-data bits stored at the
addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
1
0
1
0
R
E
A
D
S
T
O
P
DATA
0 P1 P0
D7
D0
R A
/ C
W K
A
C
K
WPB
Fig.45 CURRENT READ CYCLE TIMING（PORT0）
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10/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
○When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including
Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output.
When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output.
○Current Read operation allows the master to access data word stored in internal address counter which is appointed by
P1, P0 bit. This operation involves a two-step process. This device will respond with an acknowledge and then transmit
the 8-data bits stored at the addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
note)If the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address
data, and master can't send stop condition, so master can't discontinues transmission.
To stop read command, the master must send no Acknowledge at after D0 output, and issue stop condition.
S
T
A
R
T
SDA
LIN
R
E
A
D
SLAVE
ADDRESS
DATA(n+x）
DATA(n)
D7
1 0 1 0 0 P1 P0
S
T
O
P
D7
D0
D0
WPB
Fig.46 SEQUENTIAL READ CYCLE TIMING （PORT0）
○During the sequential read operation, the internal address counter of this device automatically increments with each
acknowledge received ensuring the data from address will be followed with the data from n+1. For read operations, all bits
of the address counter are incremented allowing the entire array to be read during a single operation. When the counter
reaches the top of the array, it will “roll over” to the bottom of the array of BANK and continue to transmit the data.
○The sequential read operation can be performed with both current read and random read.
●PORT1,2,3 access commands
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1
0
0 0
WA7
0
R
/
W
S
T
A
R
T
1st WORD
ADDRESS(n)
1 0
WA0
1 0
0 0
A
C
K
A
C
K
R
E
A
D
SLAVE
ADDRESS
D7
0
S
T
O
P
DATA(n)
D0
A
C
K
R A
/ C
W K
WPB
Fig.47 RANDOM READ CYCLE TIMING（PORT1～3）
○Random read operation allows the master to access any memory location of the BANK which is appointed by P1, P0. This
operation involves a two-step process.
First, the master issues a write command which includes the start condition and the slave address field (with R/W set to
“0”) followed by the address of the word be read.
This procedure sets the internal address counter of this device to the desired address.
After the word address acknowledge is received by the master, the master immediately reissues a start condition followed
by the slave address field with R/W the set to “1.”
This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the
master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues
transmission.
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1
0
1 0
0
D7
0 0
R
/
W
S
T
O
P
DATA
A
C
K
D0
A
C
K
WPB
Fig.48 CURRENT READ CYCLE TIMING（PORT1～3）
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11/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
○When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including
Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output.
When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output.
○Random read operation allows the master to access any memory location. The BANK which is appointed by P1, P0. This
operation involves a two-step process.
First, the master issues a write command which includes the start condition and the slave address field (with R/W set to
“0”) followed by the address of the word be read. This procedure sets the internal address counter of this device to the
desired address. After the word address acknowledge is received by the master, the master immediately reissues a
start condition followed by the slave address field with R/W the set to “1.” This device will respond with an acknowledge
and then transmit the 8-data bits stored at the addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
note)If the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address data, and master can't send stop
condition, so master can't discontinues transmission. To stop read command, the master must send no Acknowledge at after D0 output, and issue stop
condition.
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0
0
D7
0 0
※1 R
/
W
A
C
K
S
T
O
P
DATA(n+x)
DATA(n)
D0
D7
A
C
K
A
C
K
D0
A
C
K
WPB
Fig.49 SEQUENTIAL READ CYCLE TIMING （PORT1～3）
○During the sequential read operation, the internal address counter of this device automatically increments with each
acknowledge received ensuring the data from address n will be followed with the data from n+1. For read operations, all
bits of the address counter are incremented allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over to the bottom of the array and continue to transmit the data.
○The sequential read operation can be performed with both current read and random read.
●Access Control of PORT0,1,2,3
WPB terminal controls access enable of each PORT, as follows.
WPB terminal inputs
PORT
0
1
PORT0
not accessible
Read/Write
PORT1
Read
not accessible
PORT2
Read
not accessible
PORT3
Read
not accessible
Table4 WPB terminal and port accesibility
○ When WPB terminal is “HIGH”, PORT0 only can access this device.
In this case, when commands from PORT1, 2, 3 are inputted, these port don't return acknowledge.
○ When WPB terminal is “LOW”, PORT0 access is not valid, but PORT1, 2, 3 can access this device this device.
Commands from PORT1, 2, 3 is performs independently other port.
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2009.04 - Rev.B
Technical Note
BU9883FV-W
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.50(a), Fig.50(b), and Fig.50 (c).) In
dummy clock input area, release the SDA0～3 bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both
'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow,
leading to instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL0～3
2
1
13
Normal command
14
SDA0～3
Normal command
Fig.50-(a) The case of dummy clock +START+START+ command input
Start
SCL0～3
Start
Dummy clock×9
1
2
8
9
Normal command
SDA0～3
Normal command
Fig.50-(b) The case of START +9 dummy clocks +START+ command input
Start×9
SCL0～3
7
3
2
1
8
9
Normal command
SDA0～3
Normal command
Fig.50-(c) START×9+ command input
*Start command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R address
T
S
T Slave
A
R address
T
A
C
K
H
A
C
K
H
tWR
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C Word
K address
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
Fig.51 Case to continuously write by acknowledge polling
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13/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 52.)
However, in ACK output area and during data read, SDA0～3 bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL0～3
SDA0～3
1
0
1
0
Start condition
Fig.52 Case of cancel by start, stop condition during slave address input
Stop condition
●I/O peripheral circuit
○Pull up resistance of SDA0～3 terminal
SDA0～3 is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate
value to this resistance value from microcontroller VIL, IL, and VOL0～3-IOL characteristics of this IC. If RPU is large,
action frequency is limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors. The following VCC, SDA, RPU and IL correspond to them
of each port.
(1)SDA0～3 rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA0～3 should be tR or below.
And AC timing should be satisfied even when SDA0～3 rise time is late.
(2)The bus electric potential ○
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
SDA0～3 bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
recommended noise margin 0.2VCC.
マイコン
Microcontroller
BU9883FV-W
Vcc - ILRPU － 0.2Vcc ≧ VIH
∴
RPU ＝
RPU
0.8Vcc－VIH
A
IL
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
IL
from (2)
RPU ≦
IL
Bus line
バスライン容量
capacity
CBUS
CBUS
0.8×3－0.7×3
10×10
SDA terminal
-6
≦ 300 [kΩ]
Fig.53 I/O circuit diagram
○Minimum value of RPU
The minimum value of RPU is determined by the following factors. The following VCC, VOL, IOL, and RPU correspond to
them of each port.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC－VOL
RPU
≦ IOL
∴
RPU ≦
VC－VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise
margin 0.1VCC.
VOLMAX ≦ VIL-0.1 VCC
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC
from (1)
3－0.4
RPU ≧
≧
3×10
-3
867 [Ω]
And
VOL = 0.4 [V]
VIL = 0.3×3
= 0.9 [V]
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL0～3 terminal
When SCL0～3 control is made at CMOS output port, there is no need, but in the case there is timing where SCL0～3
becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended
in consideration of drive performance of output port of microcontroller.
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14/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Cautions on microcontroller connection
○Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used. The following SCL SDA RPU and RS correspond to them of each port.
ACK
RPU
SCL
RS
SDA
'H' output of microcontroller
Microcontroller
'L' output of EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
EEPROM
Fig.55 Input / output collision timing
Fig.54 I/O circuit diagram
○Maximum value of Rs
The maximum value of Rs is determined by the following relations. The following VCC, VOL, RS, RPU, IOL, and SDA
correspond to them of each port.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should
(2)The bus electric potential ○
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1VCC.
VCC
(VCC －VOL)×R S
RPU +R S
RPU A
RS
+
VOL+0.1VCC ≦VIL
VOL
IOL
∴
RS
VIL－VOL－0.1VCC
1.1VCC －VIL
≦
Bus line
capacity CBUS
×
R PU
Example） When VCC =3V, VIL=0.3VCC, VOL=0.4V, RPU =20kΩ,
VIL
EEPROM
Microcontroller
Fig.56 I/O circuit diagram
from(2),
RS
0.3×3 －0.4－0.1×3
1.1×3 －0.3×3
≦
×
20×10 3
≦ 1.67［kΩ］
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in
set and so forth. Set the over current to EEPROM 10mA or below. The following VCC, RPU, RS, and I correspond to them
of each port.
VCC
≦
RS
RPU
I
'L' output
RS
∴
RS
≧
VCC
I
Over currentⅠ
Example）When VCC =3V, I=10mA
'H' output
Microcontroller
RS
EEPROM
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3
10×10 -3
≧ 300 ［Ω］
Fig.57 I/O circuit diagram
© 2009 ROHM Co., Ltd. All rights reserved.
≧
15/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●I2C BUS input / output circuit
○Input (SCL0～3)
Fig.58 Input pin circuit diagram
○Input / output (SDA0～3)
Fig.59 Input / output pin circuit diagram
○Input (WPB)
Fig.60 Input pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, VCC rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA0～3 = 'H' and SCL0～3 ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
tOFF
Recommended conditions of tR, tOFF,Vbot
Vbot
0
tR
tOFF
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
Fig.60 Rise waveform diagram
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16/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
3. Set SDA0～3 and SCL0～3 so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA0～3 becomes 'L' at power on.
→Control SCL0～3 and SDA0～3 as shown below, to make SCL0～3 and SDA0～3, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.61 When SCL0～3= 'H' and SDA0～3= 'L'
Fig.62 When SCL0～3='L' and SDA0～3='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●VCC noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC VCCOUT and GND. At that moment, attach it as close to IC
as possible. And, it is also recommended to attach a bypass capacitor between board VCCOUT and GND.
●Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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17/18
2009.04 - Rev.B
Technical Note
BU9883FV-W
●Ordering part number
B
U
9
Part No.
8
8
3
F
Part No.
V
-
Package
FV: SSOP-B16
W
E
2
W: Double Cell
Packaging and forming specification
E2: Embossed tape and reel
SSOP-B16
<Tape and Reel information>
5.0±0.2
9
0.3Min.
4.4±0.2
6.4±0.3
16
1
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
8
0.10
1.15±0.1
0.15±0.1
0.1
0.65
1pin
0.22±0.1
Reel
(Unit : mm)
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18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.04 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
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More detail product informations and catalogs are available, please contact us.
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