3.3V 10BIT 0.5MSPS DAC
GENERAL DESCRIPTION
FEATURES
The BW1244X is a CMOS 10Bit D/A converter for
general application. This digital to analog converter has
a R-2R ladder structure.
Its maximum conversion rate is 0.5MSPS.
TYPICAL APPLICATIONS
•
•
•
•
BW1244X
Hard Disk Drive (HDD)
Battery Operated Instruments
Motor Control Systems
General Applications
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•
•
•
•
•
•
•
Resolution : 10Bit
Differential Linearity Error : ± 1.0 LSB
Integral Linearity Error : ± 2.0 LSB
Maximum Conversion Rate : 0.5MSPS
Low Power Consumption : 9.9mW
Power Down Mode
Operation Temperature Range : 0º C ~ 70º C
Power Supply : 3.3V Single
FUNCTIONAL BLOCK DIAGRAM
VDDD
VSSD
VDDA
VSSA
VBBA
D[9:0]
_
R-2R Ladder
+
VRT
VRB
PWRDN
Ver 1.8 (April 2002)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
SAMSUNG ELECTRONICS Co. LTD
OP
AMP
VOUT
BW1244X
3.3V 10BIT 0.5MSPS DAC
CORE PIN DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
D[9:0]
DI
picc_bb
Digital Input Data (10bit)
D[9] : MSB , D[0] : LSB
PWRDN
DI
picc_bb
Power Down (Active Low)
VRT
AB
pia_bb
Voltage Reference Top
VRB
AB
pia_bb
Voltage Reference Bottom
VOUT
AO
poa_bb
Analog Voltage Output
VDDD
DP
vddd
Digital Power (+3.3V)
VSSA
DG
vssd
Digital Ground (0.0V)
VDDA
AP
vdda
Analog Power (+3.3V)
VSSA
AG
vssa
Analog Ground (0.0V)
VBBA
AG
vbba
Analog Sub Bias (0.0V)
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP
DP
AG
DG
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
CORE CONFIGURATION
VDDD
VDDA
VSSA
VBBA
bw1244x
D[9:0]
VRT
SEC ASIC
VSSD
VRB
VOUT
PWRDN
2 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
VDD (VDDA,VDDD)
4.5
V
Analog Output Voltage
VOUT
VSS to VDD
V
Digital Input Voltage
D[9:0]
VSS to VDD
V
Reference Voltage
VRT
VRB
VDD
VSS
V
Operating Temperature Range
Topr
0 to 70
°C
Supply Voltage
NOTES :
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition
value is applied with the other values kept within the following operating conditions and function operation under any
of these conditions is not implied.
2. All voltages are measured with respect to VSS(VSSA or VSSD or VBBA) unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDDA - VSSA
VDDD - VSSD
3.15
3.3
3.45
V
Supply Voltage Difference
VDDA - VDDD
-0.1
0.0
0.1
V
Reference Voltage
VRT
VRB
0.0
-
3.3
-
V
Digital Input 'Low' Voltage
Digital Input 'High' Voltage
VIL
VIH
0.7×VDD
-
0.3×VDD
-
V
Operating Temperature
Topr
0
-
70
°C
NOTE :
It is strongly recommended that to avoid power latch-up all the supply pins(VDDA,VDDD)
be driven from the same source.
SEC ASIC
3 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : VDDA=VDDD=3.3V, VSSA=VSSD=VBBA=0V,
PWRDN=High, Top=25° C, VRT=3.3V, VRB=0.0V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
Bit
-
-
10
Bits
-
Differential Linearity Error
DLE
-
0.3
0.5
LSB
-
Integral Linearity Error
ILE
-
1.5
2.0
LSB
-
Zero Scale Error1
VZSE
-
3
6
mV
Full Scale Voltage Error2
VFSE
-
4
11
mV
Maximum Output Voltage
VoMAX
3.280
3.290
3.297
V
VLSB
3.206
3.220
3.223
mV
Resolution
Conditions
VRT=3.3V , VRB=0.0V
LSB Size
NOTE
VoMAX = VOUT(D[9:0]=High)
VLSB = VoMAX / 1023
1 : VZSE=VOUT(D[9:0]=Low) - VRB
2 : VFSE=VOUT(D[9:0]=High) - {(VRT-VRB) × 1023/1024 + VRB}
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : VDDA=VDDD=3.3V, VSSA=VSSD=VBBA=0V, load cap=25pF
Top=25°C, VRT=3.3V, VRB=0.0V unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Maximum
Conversion Rate
fC
-
-
0.5
Dynamic Supply Current
Ivdd1
-
3
-
Unit
Conditions
MSPS Data Rate = 0.5MHz
mA
Ivdd1 = IVDDA + IVRT + IVDDD
Data Rate = 0.5MHz
Dynamic Supply Current
(Power Down Mode)
Ivdd2
-
-
10
uA
Ivdd2 = IVDDA + IVDDD
Data Rate = 0.5MHz
PWRDN=LOW
Analog Output Delay
Td
90
100
105
ns
Data Rate = 0.5MHz
Data : All LOW → All HIGH
Analog Output Rise Time
Tr
100
107
115
ns
Data Rate = 0.5MHz
Data : All LOW → All HIGH
Analog Output Fall Time
Tf
94
100
107
ns
Data Rate = 0.5MHz
Data : All HIGH → All LOW
Analog Output
Settling Time
Ts
160
240
350
ns
Data Rate = 0.5MHz
Data : All LOW → All HIGH
VRT = VDD/2
Power Down On Time
Ton
50
53
60
ns
PWRDN : HIGH → LOW
Power Down Off Time
Toff
155
165
180
ns
PWRDN : LOW → HIGH
SEC ASIC
4 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
TIMING DIAGRAM
DATA
0000000000
0000000000
1111111111
1111111111
0000000000
90%
VOUT
DATA
50%
10%
Td
Tf
Tr
VOUT
DATA
50%
0000000000
1111111111
0000000000
± 0.5LSB
VOUT
50%
Ts
PWRDN
50%
50%
Toff
Ton
± 0.5LSB
VOUT
± 0.5LSB
0.0V
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The bw1244x has a R-2R Ladder Block for 10bit and an OP amp Block for driving Output.
2. The R-2R Ladder Block generates binary weighted voltage (VRT/21 , VRT/22 , VRT/23 , …VRT/210)
corresponding to Digital Input Data for n-bit DAC and Output total voltage is summing of each values.
VMSB = VRT/21
VLSB = VRT/210
3. In Output voltage,
VOUT =
VRT − VRB
10
2
9
∑ (2
n=0
n
× D[n]) + VRB
4. Output of the R-2R Ladder Block is driven by OP amp.
5. In power down mode, only analog current (IVDDA) is reduced.
SEC ASIC
5 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
CORE EVALUATION GUIDE
HOST
DSP
CORE
10
10
TEST PATH
MUX
10
Cc
Ct
VDDA
VRB
VSSA
Ct
VSSD
Ct
Cc
0.0V
VBBA
GND
bw1244x
Cc
GND
3.3V GND 3.3V GND
Cc
Ct
VDDD
D[9:0]
PWRDN
VRT
3.3V
VOUT
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
VOUT
TESTABILITY
Whether you use MUX or the internal logic for testability, it is required to be able to select
the values of digital inputs ( D[9:0] ).
See above figure. Only if it is, you can check the main function. ( Linearity )
Normal Test Condition : VRT=3.3V , VRB=0.0V , PWRDN=High
SEC ASIC
6 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
PHANTOM CELL INFORMATION
PWRDN
VOUT
VBBA
VSSA
VDDA
VDDD
VSSD
D[9]
VRT
VRB
D[0]
bw1244x
D[8]
D[1]
D[7]
D[2]
D[6]
D[3]
D[5]
D[4]
Pin Name
Property
Pin Usage
D[9:0]
DI
Internal / External
PWRDN
DI
Internal / External
VRT
AB
External
VRB
AB
External
VOUT
AO
Internal / External
VDDA
AP
External
VSSA
AG
External
VDDD
DP
External
VSSD
DG
External
VBBA
AG
External
Pin Layout Guide
1. Digital Input Signal lines must have same length to
reduce propagation delay.
1. Voltage reference lines (VRT and VRB) must be wide metal
to reduce voltage drop of metal lines.
2. VOUT signal should not be crossed by any signals and
should not run next to digital signals to minimize capacitive
coupling between the two signals.
1. It is recommended that you use thick analog power metal.
When connected to PAD, the path should be kept as short
as possible.
2. Digital power and analog power are separately used.
1. When the core block is connected to other blocks, it must be double guard-ring using N-well and
P+ active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
SEC ASIC
7 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
PACKAGE CONFIGURATION
L1
Cc
Ct
+
L2
1
VDDD
VBBA
48
2
VDDD
VBBA
47
3
VSSD
NC
46
4
VSSD
NC
45
5
NC
VSSZ
44
6
NC
VSSZ
43
7
NC
VDDZ
42
D[9]
8
D[9]
VDDZ
41
D[8]
9
D[8]
NC
D[7]
10
D[7]
D[6]
11
D[6]
D[5]
12
D[5]
L3
13
D[4]
D[3]
14
D[3]
D[2]
15
D[2]
D[1]
16
D[0]
BW1244X
D[4]
40 L4
VSSA
39
VSSA
38
VDDA
37
36
NC
35
NC
34
D[1]
NC
33
17
D[0]
NC
32
18
NC
PWRDN
31
19
NC
VOUT
30
20
NC
VOUT
29
21
NC
NC
28
22
NC
NC
27
(0.0V Typ.)
23
VRB
VRT
26
VRB
24
VRB
VRT
25
Cc
Ct
SEC ASIC
(VSS)
0.0V
Ct
+
Cc
VDDA
+
L5
3.3V
(VDD)
(3.3V in normal operation)
PWRDN
VOUT
(3.3V Typ.)
Ct
LOCATION
DESCRIPTION
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
L1~L5
FERRITE BEAD ( 0.1mh )
8 / 11
VRT
+
Cc
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
PACKAGE PIN DESCRIPTION
NAME
PIN NO
I/O TYPE
PIN DESCRIPTION
VDDD
1,2
DP
Digital Power (3.3V)
VSSD
3,4
DG
Digital Ground (0.0V)
D[9:0]
8~17
DI
Digital Input Data
VRB
23,24
AB
Voltage Reference Bottom (0.0V)
VRT
25,26
AB
Voltage Reference Top (3.3V)
VOUT
29,30
AO
Analog Voltage Output
PWRDN
31
DI
Power Down Mode (Low Active)
VDDA
36,37
AP
Analog Power (3.3V)
VSSA
38,39
AG
Analog Ground (0.0V)
VDDZ
41,42
AP
Pad Power (3.3V)
VSSZ
43,44
AG
Pad Ground (0.0V)
VBBA
47,48
AG
Analog Sub Bias (0.0V)
NC
5,6,7,18,19
20,21,22,27
28,32,33,34
35,40,45,46
DO
No Connection
I/O TYPE ABBR.
•
•
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
•
•
•
•
AP
DP
AG
DG
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
SEC ASIC
9 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
PC BOARD LAYOUT CONSIDERATION
1. PC Board Considerations
To minimize noise on the power lines and the ground lines, the digital inputs
need to be shielded and decoupled. This trace length between groups
of VDD (VDDA,VDDD) and VSS (VSSA,VSSD) pins should be as short as possible
so as to minimize inductive ringing.
2. Supply Decoupling and Planes
For the decoupling capacitor between the power line and the ground line, 0.1uF
ceramic capacitor is used in parallel with a 10uF tantalum capacitor.
The digital power plane(VDDD) and analog power plane(VDDA) are connected
through a ferrite bead, and also the digital ground plane(VSSD) and the analog
ground plane(VSSA). This ferrite bead should be located within 3inches of
the BW1244X. The analog power plane supplies power to the BW1244X of
the analog output pin and related devices.
SEC ASIC
10 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
FEEDBACK REQUEST
We appreciate your interest in out products.
If you have further questions, please specify in the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
°C
Output Load Capacitor
pF
Output Load Resistor
kΩ
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
Digital Input Format
V
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
-
Analog Output Maximum Current
mA
Analog Output Maximum Signal Frequency
kHz
Reference Voltage
V
External Resistor for Current Setting(RSET)
Ω
Pipeline Delay
sec
Do you want to Power down mode?
Do you want to Internal Reference Voltage(BGR)?
Which do you want to serial input data type or parallel input data type?
Do you need 5V power supply in your system?
SEC ASIC
11 / 11
ANALOG
BW1244X
3.3V 10BIT 0.5MSPS DAC
HISTORY CARD
Version
Date
Modified Items
Ver 1.6
Version updates
All pictures and texts are modified with dac1236x's datasheet.
00.02.22
The format ant fonts of datasheet are same with dac1236x's
datasheet.
Ver 1.7
Version Updated
01.03.28 page 4 : power down mode current (→10uA)
page 11 : ° C → kΩ (Output Load Resistor)
Ver 1.8
Version Updated
page 5 : functional description is modified.
page 6 : functon → function
02.04.23
page 7 : phantom cell is modified and table is added.
page 8 : VRT pin number is modified (18 → 25)
page 11 : W → Ω
SEC ASIC
Comments
Reference datasheet
DAC1236X
ANALOG