CA3274 Current Limiting Power Switch with Current Limiter Sense Flag April 1994 Features Description • Drive-Current Limiting at Output The CA3274 is a controlled current switch and may be used in general purpose switching applications that require specified maximum levels of current. The functional block diagram of the CA3274 is shown and a typical application circuit is shown in Figure 1. An internal emitter follower has 200mA of source drive output capability. The Control Input is a Schmitt trigger buffer amplifier for noise immunity in the environments typical of industrial and automotive control systems. • Current-Sense Buffer and Reference • 200mA Driver Current Capability • Logic-Level Control Input • Current Limiting Flag Output • 50dB Minimum PSRR Current sensing in the emitter circuit of a power-darlington output stage is fed back from a sampling resistor to the sense input of the CA3274 which has a 335mV typical offset. For the example shown in Figure 1, a sampling resistor of 0.056Ω permits 6.0A (0.335/0.056) of current in the emitter of the output driver. When the current limiter is activated, the flag output changes state conditionally. If the control input is the “0” state, the flag output will remain in a “1” state. If the control input is in the “1” state and the sense input is less than the voltage reference level of 335mV, the flag output will remain in the “1” state. If the control input is the “1” state and the sense input is equal to or greater than the 335mV reference level, the flag output goes to the “0” state. The output flag switch may be used to accurately establish dwell timing in automotive applications. When the control input goes to “0”, the flag is reset to “1”. Noiseimmunity hold-off is used to prevent pre-triggering of the flag output and is noted as tD in the timing diagram of Figure 2. • 5µs Typical Switch Time • Separate Signal and Power Grounds Applications • Solenoid Switch Driver • Relay Driver • Lamp Control Switch • Ignition Coil Pre-Driver • Constant Current Driver • Current Limiting Switch • Fault Output Sense Appliance • Power Supply Fault Mode Control Ordering Information PART NUMBER CA3274E TEMPERATURE RANGE -40oC to +85oC PACKAGE 8 Lead Plastic DIP The flag output may be used for diagnostic feedback via the current sense input to detect a fault mode. In this case the sampled drive current is either from the emitter of the CA3274 internal power transistor or an external output amplifier, such as a darlington power transistor or power-FET output stage. The CA3274 has separate power and signal grounds to minimize transient-loop feedback to the input ground and thus prevent false triggering of the output. Optionally, the output from the CA3274 may be taken from the open collector (DRIVE IN) at pin 6. An external resistor at pin 6 may be used to set the level at which Q2 will saturate, providing additional limiting protection for the maximum forward-drive from the CA3274. Pinout CA3274 (PDIP) TOP VIEW FLAG OUT 1 8 VCC SUPPLY SENSE IN 2 7 CONTROL IN POWER GND 3 6 DRIVE IN SIGNAL GND 4 5 DRIVE OUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 10-40 File Number 2222.2 CA3274 Block Diagram VCC 8 D1 CONTROL IN 7 FLAG OUT 1 R4 RELAY OR SOLENOID LOAD 6 CONTROL LOGIC AND CURRENT LIMITER DRIVE IN Q2 5 DRIVE OUT R3 R2 Q1 LATCH 4 + SENSE IN 2 SIGNAL GROUND SENSE R1 335mV 3 POWER GROUND VCC VCC1 8 LOAD CONTROL IN 6 CONTROL LOGIC & CURRENT LIMITER 7 Q2 6A 5 DRIVE DARLINGTON FLAG OUT 1 4 Q1 LATCH + SENSE IN SIGNAL GROUND 2 0.056Ω 335mV 3 POWER GROUND SENSE LEVEL EQUALS 335mV = 6A 0.056Ω FIGURE 1. TYPICAL APPLICATION AS A POWER SWITCH PRE-DRIVER SWITCH 10-41 Specifications CA3274 Absolute Maximum Ratings Thermal Information Operating Drive Supply, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V Maximum Output Current, IO . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Control, Sense Input. . . . . . . . . . . . . . . . . . . Gnd - 0.5V, VCC + 0.5V Signal, Power Differential Ground Voltage. . . . . . . . . . . . . . . . . . . ±1V Thermal Resistance θJA Plastic DIP Package 8 Lead . . . . . . . . . . . . . . . . . . . . . 130oC/W Power Dissipation, PD Up to 70oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630mW Above 70oC . . . . . . . . . . . . . . . . . . . . Derate linearly at 7.7mW/oC Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range. . . . . . . . . . . . . . . . . . -55oC to +150oC Lead Temperature (During Soldering) At distance 1/16in. (1.59mm ± 0.79mm) from case for 10s Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications At TA = -40oC to +85oC, Unless Otherwise Specified PARAMETERS SYMBOL Power Supply Current: S1 = 2 ICCH ICCL Control Input: S1 = 3 MIN TYP MAX UNITS Control = High (Output On) - - 25 mA Control = Low (Output Off) - - 5 mA VTHDH Thd. Voltage, High - - 3.5 V VTHDL Thd. Voltage, Low 0.9 - - V Hysteresis 0.4 0.65 2.0 V Leakage, 0.0 to 5.5V -20 - +20 µA VTHDH-VTHDL IIL Driver In, Out (Pin 6, 5): S1 = 3 TEST CONDITIONS VSAT Output Saturation Voltage, ICC1 = 200mA, VCONTROL = High - - 0.5 V ILEAK Collector Output Leakage, VCONTROL = Low - - 100 µA Flag Output Low: S1 = 2 VFSAT VSENSE = High, IFLAG = 3mA - - 0.8 V Flag Output High: S1 = 3 VFLEAK Output Leakage, VCC = VFLAG = 10V - - 10 µA Control In to Drive Out - 5 - µs Drive Off to Flag Off - 10 - µs 150 - 600 µs Prop. Delay: S1 = 1 tON, tOFF tFLAG tD Flag Delay from Control In Sense Input Thd. Level: S1 = 1 VSENTHD 310 335 360 mV Power Supply Rejection Ratio PSSR 50 - - dB NOTES: 1. Refer to Figure 3 Test Diagram for electrical test connections. 2. Refer to Figure 2 Timing Diagram for logic switching and prop delay. 3. Unless otherwise specified: VCC = VCC1 = VCC2 = 7V to 10V; VSENSE = “Low”; VCONTROL = “Low”; Control in levels are defined as “Low” equals 0.0V and “High” equals 5.0V. 10-42 CA3274 tFALL tRISE CONTROL IN - PIN 7 tON DELAY tOFF DELAY DRIVE OUT- PIN 5 CURRENT LIMITING ON TIME OUTPUT LOAD CURRENT 3.35mV SENSE LEVEL SYSTEM NOISE SENSE IN - PIN 2 tSENSE FLAG OUT- PIN 1 (NOISE HOLD-OFF DELAY) tD (SEE NOTE) tFLAG DELAY NOTE: For VCC = 7V to 10V; tD (MAX) = 600µS, if Control In = High, Sense In = High; Pin 1, Flag Out can go low only if tSENSE ≥ tD FIGURE 2. CA3274 TIMING DIAGRAM OUTPUT LOAD POWER SUPPLY +VCC1 POWER SUPPLY +VCC ICC 8 51Ω IN (ADJ. FOR 200mA IN VSAT TEST) 6 IN IN VCONTROL 7 CONTROL LOGIC Q2 DRIVER 5 OUT +VCC2 (ADJ. FOR 3mA IN FLAG-OUT VSAT TEST FLAG OUT 1 S1 3 (PSSROUT) 2.1V 10K 1 2 SENSE S1 IN 3 4 Q1 LATCH + 1 2.1V 120Ω SIGNAL GROUND 335mV 3 POWER GROUND FIGURE 3. CA3274 TEST CIRCUIT 10-43 VSENSE 120 CA3274 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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