CA3290, CA3290A DUCT ENT E PRO T E L O L A CE M e r a t P E O BS R e nt DED MMEN al Support C om/tsc COData E R Sheet .c ic O il n N er s e ch ww.int t ou r T contac TERSIL or w IN 1-888® BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output • MOSFET Input Stage - Very High Input Impedance (ZIN) . . . . . . . . 1.7TΩ (Typ) - Very Low Input Current at V+ = 5V. . . . . . . 3.5pA (Typ) - Wide Common Mode Input Voltage Range (VICR) Can Be Swung 1.5V (Typ) Below Negative Supply Voltage Rail - Virtually Eliminates Errors Due to Flow of Input Currents • Output Voltage Compatible with TTL, DTL, ECL, MOS, and CMOS Logic Systems in Most Applications Applications Pinout • • • • • CA3290/A (PDIP) TOP VIEW 8 V+ 7 OUTPUT (A2) -+ A1 +- OUTPUT (A1) 1 NON-INV. INPUT (A1) 3 V- 4 A2 FN1049.4 Features The CA3290A and CA3290 types consist of a dual voltage comparator on a single monolithic chip. The common mode input voltage range includes ground even when operated from a single supply. The low supply current drain makes these comparators suitable for battery operation; their extremely low input currents allow their use in applications that employ sensors with extremely high source impedances. Package options are shown in the table below. INV. INPUT (A1) 2 January 2004 6 INV. INPUT (A2) High Source Impedance Voltage Comparators Long Time Delay Circuits Square Wave Generators A/D Converters Window Comparators Part Number Information 5 NON-INV. INPUT (A2) PART NUMBER TEMP RANGE (oC) PACKAGE PKG. NO. CA3290AE -55 to 125 8 Ld PDIP E8.3 CA3290E -55 to 125 8 Ld PDIP E8.3 Schematic Diagram (ONLY ONE IS SHOWN) BIASING CIRCUIT FOR CURRENT SOURCES V+ COMPARATOR NO. 1 I1 I2 Q9 50µA I3 I4 Q10 100µA TO COMP. NO. 2 50µA D1 Q11 100µA Q12 VO Q13 Q14 D3 Q2 D2 Q3 D4 Q1 Q8 Q4 Q16 Q15 Q17 +VI R1 100kΩ -VI Q7 Q5 Q18 R2 1kΩ Q6 R3 5kΩ C1 5pF V- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA3290, CA3290A Absolute Maximum Ratings Thermal Information Supply Voltage Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+36V Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V Differential Input Voltage . . . . . . . . . . . . . . . . 36V or [(V+ - V-) +5V] (whichever is less) DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V+ +5V to V- -5V Output to V- Short Circuit Duration (Note 1) . . . . . . . . . . Continuous Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 110 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuits from the output to V+ can cause excessive heating and eventual destruction of the device. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Offset Voltage Temperature Coefficient of Input Offset Voltage Input Offset Current Input Current Supply Current Voltage Gain V- = 0V, Unless Otherwise Specified SYMBOL VIO II I+ AOL 2 CA3290 MIN TYP MAX MIN TYP MAX UNITS VCM = VO = 1.4V, V+ = 5V Full - 4.5 - - 8.5 - mV VCM = VO = 0V, V+ = +15V, V- = -15V Full - 8.5 - - 8.5 - mV VCM = VO = 1.4V, V+ = 5V 25 - 4.0 10 - 7.5 20 mV VCM = VO = 0V, V+ = +15V, V- = -15V 25 - 4.0 10 - 7.5 20 mV - 8 - - 8 - µV/oC TEST CONDITIONS ∆VIO/∆T IIO CA3290A TEMP (oC) VCM = 1.4V, V+ = 5V Full - 2 28 - 2 32 nA VCM = 0V, V+ = +15V, V- = 15V Full - 7 28 - 7 32 nA VCM = 1.4V, V+ = 5V 25 - 2 25 - 2 30 pA VCM = 0V, V+ = +15V, V- = -15V 25 - 7 25 - 7 30 pA VCM = 1.4V, V+ = 5V 125 - 2.8 45 - 2.8 55 nA VCM = 0V, V+ = +15V, V- = 15V 125 - 13 45 - 13 55 nA VCM = 1.4V, V+ = 5V 25 - 3.5 40 - 3.5 50 pA VCM = 0V, V+ = +15V, V- = 15V 25 - 12 40 - 12 50 pA RL = ∞, V+ = 5V -55 - 0.85 1.0 - 0.85 1.6 mA RL = ∞, V+ = 30V -55 - 1.62 3.0 - 1.62 3.5 mA RL = ∞, V+ = 5V 25 - 0.8 1.4 - 0.8 1.4 mA RL = ∞, V+ = 30V 25 - 1.35 3.0 - 1.35 3.0 mA RL = 15kΩ, V+ = +15V, V- = -15V Full - 150 - - 150 - V/mV - 103 - - 103 - dB RL = 15kΩ, V+ = +15V, V- = -15V 25 25 800 - 25 800 - V/mV 88 118 - 88 118 - dB CA3290, CA3290A Electrical Specifications PARAMETER V- = 0V, Unless Otherwise Specified (Continued) SYMBOL Saturation Voltage VSAT Output Leakage Current Common Mode Input Voltage Range IOL VICR Common Mode Rejection Ratio CMRR Power Supply Rejection Ratio PSRR Output Sink Current CA3290A CA3290 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS ISINK = 4mA, V+ = 5V, +VI = 0V, -VI = 1V 125 - 0.22 0.7 - 0.22 0.7 V ISINK = 4mA, V+ = 5V, +VI = 0V, -VI = 1V -55 - 0.1 - - 0.1 - V ISINK = 4mA, V+ = 5V, +VI = 0V, -VI = 1V 25 - 0.12 0.4 - 0.12 0.4 V V+ = 15V Full - 65 - - 65 - nA V+ = 36V Full - 130 1k - 130 1k nA V+ = 15V 25 - 100 - - 100 - pA V+ = 36V 25 - 500 - - 500 - pA VO = 1.4V, V+ = 5V 25 V+ -3.5 V- V+ -3.1 V- -1.5 - V+ -3.5 V- V+ -3.1 V- -1.5 - V VO = 0V, V+ = +15V, V- = -15V 25 V+ -3.8 V- V+ -3.4 V- -1.6 - V+ -3.8 V- V+ -3.4 V- -1.6 - V V+ = +15V, V- = -15V 25 - 44 562 - 44 562 µV/V V+ = 5V 25 - 100 562 - 100 562 µV/V V+ = +15V, V- = -15V 25 - 15 316 - 15 316 µV/V VO = 1.4V, V+ = 5V 25 6 30 - 6 30 - mA TEST CONDITIONS Response Time Rising Edge tr RL = 5.1kΩ, V+ = 15V 25 - 1.2 - - 1.2 - µs Response Time Falling Edge tf RL = 5.1kΩ, V+ = 15V 25 - 200 - - 200 - ns RL = 5.1kΩ, V+ = 15V 25 - 500 - - 500 - ns RL = 5.1kΩ, V+ = 5V 25 - 400 - - 400 - ns Large Signal Response Time Test Circuits and Waveforms CC = 2pF +15V +15V 1K + TO 10X SCOPE PROBE VIN - WITH CC 1K Top Trace ≈ 4.5mV/Div. = VIN Bottom Trace = 10V/Div. = VOUT Time Scale = 5µs/Div. -15V WITHOUT CC Top Trace ≈ 4.5mV/Div. Bottom Trace = 10V/Div. Time Scale = 5µs/Div. FIGURE 1. PARASITIC OSCILLATIONS TEST CIRCUIT AND WAVEFORMS 3 CA3290, CA3290A Test Circuits and Waveforms INPUT OVERDRIVE +15V INPUT OVERDRIVE GND GND 5.1K 1K + - INPUT OUTPUT 1K 100mV OVERDRIVE 20mV OVERDRIVE 5mV OVERDRIVE 5mV OVERDRIVE 20mV OVERDRIVE 100mV OVERDRIVE FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS GND GND +15V 5.1K 1K INPUT INPUT OVERDRIVE INPUT OVERDRIVE - + OUTPUT 1K 5mV OVERDRIVE 20mV OVERDRIVE 100mV OVERDRIVE 100mV OVERDRIVE 20mV OVERDRIVE 5mV OVERDRIVE FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS Circuit Description The Basic Comparator Figure 4 shows the basic circuit diagram for one of the two comparators in the CA3290. It is generically similar to the industry type “139” comparators, with PMOS transistors replacing PNP transistors as input stage elements. Transistors Q1 through Q4 comprise the differential input stage, with Q5 and Q6 serving as a mirror connected active load and differential-to-single-ended converter. The differential input at Q1 and Q4 is amplified so as to toggle Q6 in accordance with the input signal polarity. For example, if +VIN is greater than -VIN, Q1, Q2, and current mirror transistors Q5 and Q6 will be turned off; Transistors Q3, Q4, and Q7 will be turned on, causing Q8 to be turned off. The output is pulled positive when a load resistor is connected between the output and V+. In essence, Q1 and Q4 function as source followers to drive Q2 and Q3, respectively, with zener diodes D1 through D4 providing gate oxide protection against input voltage 4 transients (e.g., static electricity). The current flow in Q1 and Q4 is established at approximately 50µA by constant current sources I1 and I3, respectively. Since Q1 and Q4 are operated with a constant current load, their gate-to-source voltage drops will be effectively constant as long as the input voltages are within the common-mode range. As a result, the input offset voltage (VGS(Q1) + VBE(Q2) VBE(Q3) - VGS(Q4)) will not be degraded when a large differential DC voltage is applied to the device for extended periods of time at high temperatures. Additional voltage gain following the first stage is provided by transistors Q7 and Q8. The collector of Q8 is open, offering the user a wide variety of options in applications. An additional discrete transistor can be added if it becomes necessary to boost the output sink current capability. The detailed schematic diagram for one comparator and the common current source biasing is shown on the front page. PMOS transistors Q9 through Q12 are the current source CA3290, CA3290A elements identified in Figure 4 as I1 through I4, respectively. Their gate source potentials (VGS) are supplied by a common bus from the biasing circuit shown in the right hand portion of the Schematic Diagram. The currents supplied by Q10 and Q12 are twice those supplied by Q9 and Q11. The transistor geometries are appropriately scaled to provide the requisite currents with common VGS applied to Q9 through Q12. V+ D1 VI+ I1 I2 I3 50µA 100µA 50µA D2 D3 Q2 QP1 I4 100µA D4 VO Q8 Q3 QP4 Q5 Q6 VIQ7 V- FIGURE 4. BASIC CIRCUIT DIAGRAM FOR ONE OF THE TWO COMPARATORS Operating Considerations oscillations unless certain precautions are observed to minimize the stray capacitive coupling between the input and output terminals. Parasitic oscillations manifest themselves during the output voltage transition intervals as the comparator switches states. For high source impedances, stray capacitance can induce parasitic oscillations. The addition of a small amount (1mV to 10mV) of positive feedback (hysteresis) produces a faster transition, thereby reducing the likelihood of parasitic oscillations. Furthermore, if the input signal is a pulse waveform, with relatively rapid rise and fall times, parasitic tendencies are reduced. When dual comparators, like the CA3290, are packaged in an 8 lead configuration, the output terminal of each comparator is adjacent to an input terminal. The lead-to-lead capacitance is approximately 1pF, which may be sufficient to cause undesirable feedback effects in certain applications. Circuit factors such as impedance levels, supply voltage, switching rate, etc., may increase the possibility of parasitic oscillations. To minimize this potential oscillatory condition, it is recommended that for source impedances greater than 1kΩ a capacitor (≥1pF - 2pF) be connected between the appropriate input terminal and the output terminal. (See Figure 1.) If either comparator is unused, its input terminals should also be tied to either the V+ or V- supply rail. Input Circuit The use of MOS transistors in the input stage of the CA3290 series circuits provides the user with the following features for comparator applications: 1. Ultra high input impedance (≅1.7TΩ); 2. The availability of common mode rejection for input signals at potentials below that of the negative power supply rail; 3. Retention of the in phase relationship of the input and output signals for input signals below the negative rail. Although the CA3290 employs rugged bipolar (zener) diodes for protection of the input circuit, the input terminal currents should not exceed 1mA. Appropriate series connected limiting resistors should be used in circuits where greater current flows might exist, allowing the signal input voltage to be greater than the supply voltage without damaging the circuit. Output Circuit The output of the CA3290 is the open collector of an n-p-n transistor, a feature providing flexibility in a broad range of comparator applications. An output ORing function can be implemented by parallel connection of the open collectors. An output pull-up resistor can be connected to a power supply having a voltage range within the rating of the particular CA3290 in use; the magnitude of this voltage may be set at a value which is independent of that applied to the V+ terminal of the CA3290. Parasitic Oscillations The ideal comparator has, among other features, ultra high input impedance, high gain, and wide bandwidth. These desirable characteristics may, however, produce parasitic 5 Typical Applications Light Controlled One-Shot Timer In Figure 5 one comparator (A1) of the CA3290 is used to sense a change in photo diode current. The other comparator (A2) is configured as a one-shot timer and is triggered by the output of A1. The output of the circuit will switch to a low state for approximately 60 seconds after the light source to the photo diode has been interrupted. The circuit operates at normal room lighting levels. The sensitivity of the circuit may be adjusted by changing the values of R1 and R2. The ratio of R1 to R2 should be CA3290, CA3290A the lower limit (VL) but below the upper limit (VU), as determined by the R1/R2/R3 resistor divider. constant to insure constant reverse voltage bias on the photo diode. R1 1.5MΩ +15V +15V +15V +15V 8 15kΩ 1MΩ 100kΩ 3.3kΩ 1N914 R1 VU 47kΩ +15V 15 kΩ 1.0µF 60MΩ 8 +15V A1 CA3290 2 1 + 5 A2 CA3290 +15V - C30809 140kΩ 7 R2 47kΩ R3 6.8kΩ VL 0.01µF 10kΩ 1N914 5 X 60s TIME CA3290 7 + 4 FIGURE 5. LIGHT CONTROLLED ONE-SHOT TIMER FIGURE 7. WINDOW COMPARATOR Low-Frequency Multivibrator In this application, one half of the CA3290 is used as a conventional multivibrator circuit. Because of the extremely high input impedance of this device, large values of timing resistor (R1) may be used for long time delays with relatively small leakage timing capacitors. The second half of the CA3290 is used as an output buffer to insure that the multivibrator frequency will not be affected by output loading. RP is the parallel combination of the two 1MΩ resistors connected between +15V and GND. +15V +15V +15V 1MΩ RP 1MΩ 3 5 8 C 2 0.36 µF 3.3kΩ 15kΩ R1 20MΩ A1 - CA3290 + A2 CA3290 +15V 6 7 - 1MΩ 1 1MΩ + 4 t = Period = 10s 2R P t = 2R 1 Clog e ------------ + 1 R 2 R2 1MΩ FIGURE 6. LOW FREQUENCY MULTIVIBRATOR Window Comparator Both halves of the CA3290 can be used in a high input impedance window comparator as shown in Figure 7. The LED will be turned “on” whenever the input signal is above 6 670Ω 2N2102 A2 100kΩ 4 1 LED + 6 - 6 A1 CA3290 3 INPUT + 3 R2 2MΩ 3.9kΩ - 2 CA3290, CA3290A Typical Performance Curves 4.0 RL = ∞ V+ = +30V, V- = GND -5 3.0 2.5 -55oC 2.0 25oC 1.5 125oC 1.0 INPUT CURRENT (pA) SUPPLY CURRENT (mA) TA = 25oC 0 3.5 -10 -15 -20 -25 0.5 0 0 5 10 15 20 25 30 35 40 -30 45 0 5 TOTAL SUPPLY VOLTAGE (V) TA = 25oC V+ = +5V, V- = GND INPUT CURRENT (pA) 4.5 4.0 3.5 3.0 2.5 0 1.0 2.0 3.0 4.0 5.0 INPUT COMMON MODE VOLTAGE (V) FIGURE 10. INPUT CURRENT vs INPUT COMMON MODE VOLTAGE 7 20 15 25 30 35 FIGURE 9. INPUT CURRENT vs INPUT COMMON MODE VOLTAGE INPUT EXCURSIONS FROM V+ TERMINAL (V) FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE (BOTH AMPLIFIERS) 10 INPUT COMMON MODE VOLTAGE (V) -1.0 -1.5 125oC -2.0 25oC -55oC -2.5 -3.0 -3.5 -4.0 0 5 10 15 20 25 30 35 40 POSITIVE SUPPLY VOLTAGE (V) FIGURE 11. POSITIVE COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE 45 CA3290, CA3290A (Continued) 10K 1.0 0.5 INPUT CURRENT (pA) INPUT EXCURSIONS FROM V- TERMINAL (V) Typical Performance Curves 125oC 0 -0.5 -1.0 25oC -1.5 -2.0 -2.5 V+ = +15V, V- = -15V VCM = 0V 1K V+ = 5V, V- = 0V VCM = 1.4V 100 10 -55oC 1 0 5 10 15 20 25 30 35 40 0 45 20 FIGURE 12. NEGATIVE COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE OUTPUT SATURATION VOLTAGE 60 125oC 25oC -55oC 1V 125oC 25oC -55oC 10mV 1mV 10µA 100µA 1mA 10mA OUTPUT SINK CURRENT FIGURE 14. OUTPUT SATURATION VOLTAGE vs OUTPUT SINK CURRENT 8 80 100 120 FIGURE 13. INPUT CURRENT vs TEMPERATURE 10V 100mV 40 TEMPERATURE (oC) NEGATIVE SUPPLY VOLTAGE (V) 140 CA3290, CA3290A Metallization Mask Layout 0 10 20 30 40 50 53 90 80 7 6 70 60 10 50 87 - 95 (2.210 - 2.403) 40 11 30 12 20 4 10 1 0 4 - 10 (0.102 - 0.254) 50 - 58 (1.270 - 1.473) 9 2 The photographs and dimensions of each chip represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) NOTE: Numbers in pads are for 8 lead DIP and TO-5 Can and numbers outside of chip are for 14 lead DIP. CA3290, CA3290A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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