廖 R 19 ， 51 8 71 44 QQ : CAT6611 58 5 Single-Link HDMI Transmitter 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 Data Sheet ver. 1.0a, 2006/12/21 CAT6611 Single-Link HDMI Transmitter Data Sheet General Description 51 8 19 ， 廖 R The CAT6611 is a high-performance and low-cost single channel HDMI transmitter, fully compliant with HDMI 1.1, HDCP 1.1 and backward compatible to DVI 1.0 specifications. The CAT6611 serves to provide the most cost-effective HDMI solution for DTV-ready consumer electronics such as settop boxes, DVD players and A/V receivers, as well as DTV-enriched PC products such as notebooks and desktops, without compromising the performance. Its backward compatibility to DVI standard allows connectivity to myriad video displays such as LCD and CRT monitors, in addition to the ever-so-flourishing flatpanel TVs. QQ : 71 44 Aside from the various video output formats supported, the CAT6611 also supports up to 8 channels of I2S digital audio, with sampling rate up to 192kHz and sample size up to 24 bits. CAT6611 also support S/PDIF input of up to 192kHz sampling rate. 66 4 34 1 58 5 By default the CAT6611 comes with integrated HDCP ROMs which are pre-programmed with HDCP keys that ensures secure digital content transmission. CAT6611 also offers external ROM option that works with either bundled pre-programmed HDCP ROMs or with customers' own HDCP ROMs. 18 Features 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: Single channel HDMI transmitter Compliant with HDMI 1.1, HDCP 1.1 and DVI 1.0 specifications Supporting pixel rates from 25MHz to 165MHz DTV resolutions: 480i, 576i, 480p, 576p, 720p, 1080i up to 1080p PC resolutions: VGA, SVGA, XGA, SXGA up to UXGA Various video input interface supporting digital video standards such as: 24-bit RGB/YCbCr 4:4:4 16/20/24-bit YCbCr 4:2:2 8/10/12-bit YCbCr 4:2:2 (CCIR-656) 12-bit double data rate interface Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2 Dithering for conversion from 12-bit component and 8-bit Digital audio input interface supporting audio sample rate: 32~192 kHz sample size: 16~24 bits Up to four I2S interface supporting 8-channel audio S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio transmission at up to 192kHz 2 2 CAT6611 Single-Link HDMI Transmitter Data Sheet 廖 R 19 ， 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 51 8 71 44 Compatible with IEC 60958 and IEC 61937 Audio down-sampling of 2X and 4X Software programmable HDMI output current level of up to +35%, enabling user to optimize the performance for fixed-cable systems or those with pre-defined cable length MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK. Integrated/External pre-programmed HDCP keys at customers' requests Purely hardware HDCP engine increasing the robustness and security of HDCP operation Monitor detection through Hot Plug Detection and Receiver Termination Detection Intelligent, programmable power management 80-pin TQFP package 3 3 CAT6611 Single-Link HDMI Transmitter Data Sheet Pin Diagram 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 41 20 DDCSCL SYSRSTN 42 19 DDCSDA PCSCL 43 18 HPD PCSDA 44 17 INT# IVDD 45 IVSS 46 OVSS 47 OVDD 48 D23 49 D22 50 D21 51 D20 52 D19 53 D18 54 D17 55 D16 56 D15 57 D14 58 IVDD 59 IVSS 60 QQ : 51 8 19 ， PCADR 廖 R 39 71 44 40 CAT6611 63 64 65 66 司 62 67 68 69 70 71 72 73 74 75 76 77 78 79 IVDD 15 IVSS 14 OVSS 13 OVDD 12 SCK 11 WS 10 I2S0 9 I2S1 8 I2S2 7 I2S3 6 MCLK 5 SPDIF 4 IVDD 3 IVSS 2 VSYNC 1 HSYNC 80 Figure 1. CAT6611 pin diagram 合 讯 科 技 有 限 公 61 ， Te l: 18 66 4 34 1 58 5 TQFP-80 Top View 16 市 金 Note: Pin71 & 72 could be left unconnected for CAT6611 with internal HDCP. When using CAT6611 without 深 圳 internal HDCP key, Pin 71 and Pin 72 serve as the master I2C interface for external HDCP ROM connection 4 4 CAT6611 Single-Link HDMI Transmitter Data Sheet Pin Description Pin Name Direction Description D[23:0] Input Digital video input pins. D[23:12] are only used in 24-bit Type Pin No. LVTTL 49-58, single-edged mode. In 12-bit, dual-edged mode D[23:12] 61-65, should be tied to ground. 67-70, DE Input Data enable LVTTL HSYNC Input Horizontal sync. signal LVTTL VSYNC Input Vertical sync. signal LVTTL PCLK Input Input data clock 71 44 2 LVTTL 66 Type Pin No. LVTTL 6 LVTTL 12 LVTTL 11 LVTTL 10 LVTTL 9 LVTTL 8 80 51 8 1 Direction Description MCLK Input Audio master clock input SCK Input I2S serial clock input WS Input I2S word select input I2S0 Input I2S serial data input I2S1 Input I2S serial data input I2S2 Input I2S serial data input I2S3 Input I2S serial data input LVTTL 7 SPDIF Input S/PDIF audio input LVTTL 5 Type Pin No. Interrupt output. Default active-low (5V-tolerant) LVTTL 17 Hardware reset pin. Active LOW (5V-tolerant) 34 1 66 4 18 l: Te ， Output SYSRSTN Input 司 INT# Description 公 Direction 技 有 限 Pin Name I/O 讯 科 DDCSCL 58 5 Pin Name Programming Pins Schmitt 42 2 Schmitt 20 2 I C Clock for DDC (5V-tolerant) I/O I C Data for DDC (5V-tolerant) Schmitt 19 PCSCL Input I2C Clock for chip programming (5V-tolerant) Schmitt 43 合 DDCSDA 2 I/O I C Data for chip programming (5V-tolerant) Schmitt 44 OVSS / Ground / Master I2C Clock for reading external HDCP Key ROM. Ground / 72 ROMSCL Output When using internal HDCP, Pin 72 should be connected to Schmitt 市 金 PCSDA 圳 QQ : Digital Audio Input Pins 深 19 ， 75-79 廖 R Digital Video Input Pins I/O ground (OVSS). OVDD / Power / Master I2C Data for reading external HDCP Key ROM. Power / ROMSDA Input When using internal HDCP, Pin 71 should be connected to Schmitt 71 3.3V I/O power (OVDD). PCADR Input I2C device address select LVTTL 41 HPD Input Hot Plug Detection (5V-tolerant) LVTTL 18 5 5 CAT6611 Single-Link HDMI Transmitter Data Sheet ENTEST Input Must be tied low via a resistor. NC LVTTL Must be left unconnected 21 41 Pin No. TX2P Analog HDMI Channel 2 positive output TMDS 36 TX2M Analog HDMI Channel 2 negative output TMDS 35 TX1P Analog HDMI Channel 1 positive output TMDS 33 TX1M Analog HDMI Channel 1 negative output TMDS TX0P Analog HDMI Channel 0 positive output TMDS 30 TX0M Analog HDMI Channel 0 negative output TMDS 29 TXCP Analog HDMI Clock Channel positive output TMDS 27 TXCM Analog HDMI Clock Channel negative output TMDS 26 REXT Analog External resistor for setting TMDS output level. Default Analog 24 32 58 5 tied to AVCC via a 475-Ohm SMD resistor. IVDD Digital logic power (1.8V) 66 4 Description 18 Pin Name 34 1 Power/Ground Pins I/O Pin ground AVCC 59, 74 Ground 3, 15, 46, 13, 48 Ground 14, 47 HDMI analog frontend power (3.3V) Power 28, 34 AGND HDMI analog frontend ground Ground 25, 31, 37 PVCC1 HDMI core PLL power (3.3V) Power 23 PGND1 HDMI core PLL ground Ground 22 PVCC2 Filter PLL power (3.3V) Power 38 Filter PLL ground Ground 39 司 限 讯 科 深 圳 市 金 合 PGND2 Te OVSS 4, 16, 45, Power ， I/O Pin power (3.3V) Power 公 OVDD Pin No. 60, 73 l: Digital logic ground Type 技 有 IVSS 廖 R Description 51 8 Direction QQ : Pin Name 19 ， Type 71 44 HDMI front-end interface pins 6 6 CAT6611 Single-Link HDMI Transmitter Data Sheet Functional Description 廖 R CAT6611 provides complete solutions for HDMI Source systems by implementing all the required HDMI functions. In addition, advanced processing algorithms are employed to optimize the performance of video processing such as color space conversion and up/down sampling. The following picture is the functional block digram of CAT6611, which describes clearly the data flow. DE D[23:0] MCLK SCK WS I2S[3:0] SPDIF HDCP Cipher & Encryption Enginer Audio Data Capture 51 8 DDCSCL DDCSDA 71 44 Color Space Conversion 4:2:2 4:4:4 Pixel Repeat Video Data Capture & DE Generator I2C Master (HDCP Controller) TX2P/M QQ : PCLK VSYNC HSYNC I2C Master (to HDCP EEPROM) I2C Slave (to host) 58 5 PCADR Configuration Register Blocks TX1P/M TMDS Transmitter (DVI/HDMI) TX0P/M TXCP/M 66 4 34 1 SYSRSTN 19 ， PCSCL PCSDA ROMSCL ROMSDA Interrupt Controller HPD 18 INT ， Video Data Processing Flow Te l: Figure 2. Functional block diagram of CAT6611 限 公 司 Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most of the block enablings and path bypassings are controlled through register programming. Please refer to CAT6611 Programming Guide for detailed and precise descriptions. 合 H/VSYNC 市 金 Clock H/VSYNC 讯 科 DE 技 有 PCLK DE Generator Embedded Ctrl. Signals Extraction DE H/VSYNC Data DE 深 圳 D[23:0] YCbCr422 to YCbCr444 YCbCr (upsampler) (CSC) RGB Dithering 12-to-8 YCbCr444 to YCbCr422 (downsampler) TX2 HDCP TMDS Driver TX1 TX0 TXC Figure 3. Video data processing flow of CAT6611 7 7 CAT6611 Single-Link HDMI Transmitter Data Sheet 廖 R As can be seen from Figure 3, the first step of video data processing is to prepare the video data (Data), data enable signal (DE), video clock (Clock), horizontal sync and vertical sync signals (H/VSYNC). While the video data and video clock are always readily available from input pins, the preparation of the data enable and sync signals require special extraction process (Embedded Ctrl. Signals Extraction & DE Generator) depending on the format of input video data. 71 44 51 8 19 ， All the data then undergo a series of video processing including YCbCr up/down-sampling, color-space conversion and dithering. Depending on the selected input and output video formats, different processing blocks are either enabled or bypassed via register control. For the sake of flexibility, this is all done in software register programming. Therefore, extra care should be taken in keeping the selected input-output format combination and the corresponding video processing block selection. Please refer to the CAT6611 Programming Guide for suggested register setting. 58 5 QQ : Designated as D[23:0], the input video data could take on bus width of 8 bits to 24 bits. This input interface could be configured through register setting to provide various data formats as listed in Table 1. 18 66 4 34 1 Although not explicitly depicted in Figure 3, input video clock (PCLK) can be configured to be multiplied by 0.5, 2 or 4, so as to support special formats such as CCIR-656 and pixel-repeating. This is also enabled by software programming. l: General description of block functions is as follows: 公 司 ， Te Extraction of embedded control signals (Embedded Ctrl. Signals Extraction) Input video formats with only embedded sync signals rely on this block to derive the proper Hsync, Vsync and DE signals. Specifically, CCIR-656 video streams includes Start of Active Video (SAV) and End of Active Video (EAV) that this block uses to extract the required control signals. 讯 科 技 有 限 Generation of data enable signal (DE Generator) DE signal defines the region of active video data. In cases where the video decoders supply no such DE signals to CAT6611, this block is used to generate appropriate DE signal from Hsync, Vsync and Clock. 深 圳 市 金 合 Upsampling (YCbCr422 to YCbCr444) In cases where input signals are in YCbCr 4:2:2 format and output is selected as 4:4:4, this block is enabled to do the upsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during upsampling. Bi-directional Color Space Conversion (YCbCr ↔ RGB) Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order to offer full compatibility between various Source and Sink combination, this block offers bi-directional RGB ↔ YCbCr color space conversion (CSC). To provide maximum flexibility, the maxtrix coefficients of the CSC engine in CAT6611 are fully programmable. Users of CAT6611 could elect to employ their preferred conversion formula. Dithering (Dithering 12-to-8) 8 8 CAT6611 Single-Link HDMI Transmitter Data Sheet All the video processings in CAT6611 are done in 12 bits per channel in order to minimize rounding errors and other computational residuals that occur during processing. For outputing to the 8-bits-per-channel formats, decimation from 12 bits to 8 bits is required. This block performs the necessary dithering for decimation to prevent visible artifacts from appearing. 19 ， 廖 R Downsampling (YCbCr444 to YCbCr422) In cases where input signals are in YCbCr 4:4:4 format and output is selected as YCbCr 4:2:2, this block is enabled to do the downsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during downsampling. 71 44 51 8 HDCP engine (HDCP) The HDCP engine in CAT6611 handles all the processing requried by HDCP mechanism in hardware. Software intervention is not necessary except checking for revocation. Preprogrammed HDCP keys are also embedded in CAT6611. Users need not worry about the purchasing and management of the HDCP keys as Chip Advanced Technology will take care of them. 34 1 58 5 QQ : TMDS driver (TMDS Driver) The final stop of the data processing flow is TMDS serializer. The TMDS driver serializes the input parallel data and drive out the proper electrical signals to the HDMI cable. The output current level is controlled through connecting a precision resistor of proper value to Pin 24 (REXT). 66 4 Supported Input Video Formats 4:4:4 YCbCr Bus Width 24 12 24 12 2 16/20/24 1 8/10/12 公 司 4:2:2 Hsync/ Vsync Seperate Seperate Seperate Seperate Seperate Embedded Seperate Embedded 480i 27 27 27 27 27 27 27 27 480p 27 27 27 27 27 27 54 54 l: 4:4:4 Input Channels 3 1 3 1 Te RGB Video Format ， Color Space 18 Table 1 lists the input video formats supported by CAT6611. Pixel clock frequency (MHz) XGA 720p 1080i SXGA 65 74.25 74.25 108 65 74.25 74.25 74.25 74.25 65 74.25 74.25 74.25 74.25 74.25 74.25 148.5 148.5 1080p 148.5 UXGA 162 148.5 148.5 148.5 限 Table 1. Input video formats supported by CAT6611 市 金 合 讯 科 技 有 Notes: 1. Table cells that are left blanks are those format combinations that are not supported by CAT6611. 2. Input channel number is defined by the way the three color components (either R, G & B or Y, Cb & Cr) are arranged. Refer to Video Data Bus Mappings starting page 16 for better understanding. 3. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY. 4. The original pixel clock of 480i is 13.5MHz. HDMI standard mandates that a 27MHz pixel clock be used and pixel repeating is employed to keep the frequency range of the HDMI link within control. 深 圳 Audio Data Capture and Processing CAT6611 takes in four I2S inputs as well as one S/PDIF input of audio data. The four I2S inputs allow transmission of 8-channel uncompressed audio data at up to 192kHz sample rate. The S/PDIF input allows transmission of uncompressed PCM data (IEC 60958) or compressed multi-channel data (IEC 61937) at up to 192kHz. Note that MCLK input is optional for CAT6611. By default CAT6611 generates the MCLK internally to process the audio. Neither I2S nor S/PDIF inputs requires MCLK input, coherent or not. 9 9 CAT6611 Single-Link HDMI Transmitter Data Sheet However, if the user prefers inputing MCLK from external audio source, such configuration could be enabled through register setting. Refer to CAT6611 Programming Guide for such setting. 176.4kHz → 88.2kHz 96kHz → 48kHz 88.2kHz → 44.1kHz 192kHz → 48kHz 176.4kHz → 44.1kHz 19 ， Down-sampling factor of 4 192kHz → 96kHz 71 44 Table 2. Audio down-samplings supported by CAT6611 51 8 Down-sampling factor of 2 廖 R Audio data can be down sampled to support a wider range of audio DACs. CAT6611 offers audio down-sampling of both a factor of two and a factor of four. Refer to Table 2 for supported down-samplings. Interrupt Generation Te l: 18 66 4 34 1 58 5 QQ : The system micro-controller should take in the interrupt signal output by CAT6611 at PIN 17 (INT). CAT6611 generates an interrupt signal with events involving the following signals or situations: 1. Hot-plug detection (Pin 18, HPD) experiences state changes. 2. Receiver detection circuit reports the presence or absence of an active termination at the TMDS Clock Channel (Register 0Eh[5], RxSENDetect) 3. DDC bus is hanged for any reasons 4. Audio FIFO overflows 5. HDCP authentication fails 6. Video data is stable or not 讯 科 技 有 限 公 司 ， A typical initialization of HDMI link should be based on interrupt signal and appropriate register probing. Recommended flow is detailed in CAT6611 Programming Guide. Simply put, the microcontroller should monitor the HPD status first. Upon valid HPD event, move on to check RxSENDetect register to see if the receiver chip is ready for further handshaking. When RxSENDetect is asserted, start reading EDID data through DDC channels and carry on the rest of the handshaking subsequently. 深 圳 市 金 合 If the micro-controller makes no use of the interrupt signal as well as the above-mentioned status registers, the link establishment might fail. Please do follow the suggested initialization flow recommended in CAT6611 Programming Guide. 10 10 CAT6611 Single-Link HDMI Transmitter Data Sheet Configuration and Function Control 廖 R CAT6611 includes two I2C ports by default (i.e. with embedded HDCP keys): one for interfacing with micro-controller, the other for accessing the DDC channels of HDMI link. If the customer elects to use CAT6611 with external HDCP keys, there's an additional I2C port for interfacing with the HDCP ROM. 51 8 19 ， The I2C interface for interfacing the micro-controller is a slave interface, comprising PCSCL (Pin 43) and PCSDA (Pin 44). The micro-controller uses this interface to monitor all the statuses and control all the functions. Two device addresses are available, depending on the input logic level of PCADR 71 44 (Pin 41). If PCADR is pulled high by the user, the device address is 0x9A. If pulled low, 0x98. 58 5 QQ : The I2C interface for accessing the DDC channels of the HDMI link is a master interface, comprising DDCSCL (Pin 20) and DDCSDA (Pin 19). CAT6611 uses this interface to read the EDID data and perform HDCP authentication protocol with the sink device over the HDMI cable. 66 4 34 1 For temporarily storing the acquired EDID data, CAT6611 includes a 32 bytes dedicated FIFO. The micro-controller may command CAT6611 to acquire 32 bytes of EDID information, read it back and then continue to read the next 32 bytes until getting all neccessary EDID informations. 讯 科 技 有 限 公 司 ， Te l: 18 The HDCP protocol of CAT6611 is completely implemented in hardware. No software intervention is needed except for revocation list checking. Various HDCP-related statuses are stored in HDCP registers for the reference of micro-controller. Refer to CAT6611 Programming Guide for detailed register descriptions. The HDCP Standard also specifies a special message read protocol other than the standard I2C protocol. See Figure 4 for checking HDCP port link integrity. Figure 4. HDCP port link integrity message read 市 金 合 Shall the user opt to purchase CAT6611 with external HDCP ROM, Pin 72 (ROMSCL) and Pin 71 (ROMSDA) form the third I2C port and interface with the external HDCP ROM. This interface is a 深 圳 master one. All I2C interfaces conform to standard I2C transactions and operate at up to 100kHz. 11 11 CAT6611 Single-Link HDMI Transmitter Data Sheet Electrical Specifications Absolute Maximum Ratings Max Unit Core logic supply voltage -0.3 2.5 V OVDD I/O pins supply voltage -0.3 4.0 V AVCC HDMI analog frontend supply voltage -0.3 4.0 V PVCC1 HDMI core PLL supply voltage -0.3 4.0 V PVCC2 Filter PLL supply voltage -0.3 4.0 VI Input voltage -0.3 OVDD+0.3 V VO Output voltage -0.3 OVDD+0.3 V TJ Junction Temperature 125 °C TSTG Storage Temperature 150 °C ESD_HB Human body mode ESD sensitivity 2000 V V QQ : -65 廖 R IVDD Typ 19 ， Min. 51 8 Parameter 71 44 Symbol 34 1 58 5 ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation. Min. Typ Max Unit IVDD Core logic supply voltage 1.71 1.8 1.89 V OVDD I/O pins supply voltage 2.97 3.3 3.63 V AVCC HDMI analog frontend supply voltage 3.135 3.3 3.465 V PVCC1 HDMI core PLL supply voltage 3.135 3.3 3.465 V PVCC2 Filter PLL supply voltage 3.0 3.3 3.6 V VCCNOISE Supply noise 100 mVpp TA Ambient temperature 25 70 °C Junction to ambient thermal resistance Θja Notes: 1. AVCC, PVCC1 and PVCC2 should be regulated. 2. See System Design Consideration at page 23 for supply decoupling and regulation. 40 °C/W 18 Parameter 限 公 司 ， Te l: Symbol 66 4 Functional Operation Conditions 深 圳 市 金 合 讯 科 技 有 0 12 12 CAT6611 Single-Link HDMI Transmitter Data Sheet Operation Supply Current Specification AVCC current under normal operation HDMI-1 24.1 26.6 mA HDMI-2 51.3 56.5 mA HDMI-3 110 130 mA DVI-2 72.9 88.8 mA DVI-1 0.26 0.43 HDMI-1 0.27 0.43 HDMI-2 0.36 HDMI-3 0.56 0.74 mA DVI-2 0.76 0.93 mA DVI-1 10.98 12.3 mA HDMI-1 11.2 12.6 mA HDMI-2 22.7 25.5 mA HDMI-3 38.6 42.6 mA DVI-2 43.2 47.4 mA DVI-1 1.7 1.9 mA HDMI-1 1.8 2 mA HDMI-2 4.5 4.9 mA HDMI-3 9.3 9.9 mA DVI-2 10.3 10.8 mA DVI-1 1.3 1.3 mA HDMI-1 1.4 1.4 mA HDMI-2 3.6 3.8 mA HDMI-3 7.7 8.1 mA DVI-2 8.4 8.9 mA DVI-1 88 106 mW HDMI-1 92 112 mW HDMI-2 195 237 mW HDMI-3 383 478 mW DVI-2 338 421 mW 34 1 66 4 PVCC1 current under normal operation Te l: 18 IPVCC1_OP PVCC2 current under normal operation Total power consumption under normal operation3 深 圳 市 金 合 讯 科 PWTOTAL_OP 技 有 限 公 司 ， IPVCC2_OP 廖 R Unit mA 58 5 IAVCC_OP Max 24.4 19 ， OVDD current under normal operation Typ 22.9 51 8 IOVDD_OP Conditions DVI-1 0.57 71 44 Parameter IVDD current under normal operation QQ : Symbol IIVDD_OP mA mA mA Notes: 1. Typ: OVDD=AVCC=PVCC1=PVCC2=3.3V, IVDD=1.8V Max: OVDD=AVCC=PVCC1=PVCC2=3.6V, IVDD=1.98V 2. DVI-1: VGA with HDCP, 640 x 480@60Hz, PCLK=25MHz DVI-2: UXGA with HDCP, 1600 x 1200@60Hz, PCLK=162MHz HDMI-1: 480p with 8-channel audio, PCLK=27MHz HDMI-2: 720p/1080i with 8-channel audio, PCLK=74.25MHz HDMI-3: 1080p with 8-channel audio, PCLK=148.5MHz 3. PWTOTAL_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items. 13 13 CAT6611 Single-Link HDMI Transmitter Data Sheet DC Electrical Specification Input high voltage1 VIL Input low voltage1 Switching threshold VT- Schmitt trigger negative going Schmitt Schmitt V 1.1 V 1 Input leakage current 1 IOZ Tri-state output leakage current IOL I2C output sink current2 TMDS output single-ended swing 3 IOL=2~16mA LVTTL IOH=-2~-16mA all VIN=5.5V or 0 all VIN=5.5V or 0 Schmitt VOUT=0.2V TMDS RLOAD=50Ω V 0.4 71 44 Output high voltage1 LVTTL 2.0 51 8 1.6 2.4 QQ : VOH Vswing 0.8 V 1.5 1 Output low voltage1 Unit 0.8 1 VOL IIN Max V LVTTL Schmitt trigger positive going threshold voltage Typ 2.0 ±5 µA ±10 µA 4 16 mA 400 600 mA VLOAD VLOAD V -10mV +10mV 58 5 VT+ Min. LVTTL 1 VT threshold voltage Conditions 廖 R VIH Pin Type LVTTL 19 ， Under functional operation conditions Symbol Parameter 34 1 VLOAD=3.3V TMDS 18 VOHTMDS TMDS output high voltage 66 4 REXT=475Ω 3 讯 科 技 有 限 公 司 ， Te l: IOFF Single-ended standby output current3 TMDS VOUT=0 10 µA Notes: 1. Guaranteed by I/O design. 2. The I2C output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In real I2C environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the I2C output ports of CAT6611 are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to CAT6611 Programming Guide for proper register setting. 3. Limits defined by HDMI 1.1 standard 合 Audio AC Timing Specification FS_SPDIF S/PDIF sample rate Conditions Up to 8 channels Min. 32 2 channels 32 Typ Max 192 Unit kHz 192 kHz 深 圳 市 金 Under functional operation conditions Symbol Parameter FS_I2S I2S sample rate 14 14 CAT6611 Single-Link HDMI Transmitter Data Sheet Video AC Timing Specification Single-edged clocking PCLK pixel clock frequency1 2 TCDE PCLK dual-edged clock period FCDE PCLK dual-edged clock frequency2 TPDUTY PCLK clock duty cycle TPJ PCLK worst-case jitter TS Video data setup time3 Unit ns 25 165 MHz 13.47 40 ns 25 74.25 MHz 40% 60% 3 Video data setup time Dual-edged clocking 1.5 0.7 1.5 51 8 Single-edged clocking Video data hold time TSDE Max 40 2.0 3 TH Dual-edged clocking Typ 71 44 Fpixel Min. 6.06 廖 R Conditions 19 ， Under functional operation conditions Symbol Parameter Tpixel PCLK pixel clock period1 ns ns ns ns 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : THDE Video data hold time3 0.7 ns Notes: 1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding pixel frequencies. 2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i. 3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user through register programming. 15 15 CAT6611 Single-Link HDMI Transmitter Data Sheet Video Data Bus Mappings H/Vsync Clocking Table 3 24 Seperate 1X 1 12 Seperate Dual-edged 19 ， 4:4:4 Bus Width 3 24 Seperate 1X 1 12 Seperate Dual-edged 9 2 16/20/24 Seperate 1X 5 Embedded 1X 6 1 8/10/12 Seperate 2X 8 Embedded 2X 7 4:4:4 YCbCr 58 5 4:2:2 4 9 51 8 RGB Input Channels 71 44 Video Format QQ : Color Space 廖 R CAT6611 supports various input data mappings and formats, including those with embedded control signals only. Corresponding register setting is mandatory for any chosen input data mappings. Refer to CAT6611 Programming Guide for detailed instruction. 4 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 Table 3. Input video format supported by CAT6611 16 16 CAT6611 Single-Link HDMI Transmitter Data Sheet RGB 4:4:4 and YCbCr 4:4:4, 24 Bits with Separate Syncs 18 19 ， 51 8 71 44 58 5 QQ : YCbCr Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 HSYNC VSYNC DE 34 1 66 4 RGB B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 HSYNC VSYNC DE l: Te ， Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 廖 R These are the simpliest formats, with a complete definition of every pixel in each clock period. Timing diagram is depicted in Fig. 5 in the example of RGB. The timing of YCbCr 4:4:4 follow suits. 深 圳 市 金 合 讯 科 技 有 限 公 司 Table 4. RGB & YCbCr 4:4:4 Mappings Figure 5. RGB 4:4:4 Timing Diagram 17 17 CAT6611 Single-Link HDMI Transmitter Data Sheet YCbCr 4:2:2 with Separate Syncs QQ : 71 44 51 8 YCbCr 4:2:2 24-bit Pixel#2N Pixel#2N+1 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y10 Y10 Y11 Y11 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 HSYNC HSYNC VSYNC VSYNC DE DE 18 66 4 34 1 58 5 YCbCr 4:2:2 20-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded Y0 Y0 Y1 Y1 grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cb8 Cb9 Cb9 HSYNC HSYNC VSYNC VSYNC DE DE 限 公 司 ， Te l: YCbCr 4:2:2 16-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 HSYNC HSYNC VSYNC VSYNC DE DE 技 有 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 19 ， 廖 R YCbCr 4:2:2 format does not have one complete pixel for every clock period. Luminace channel (Y) is given for every pixel, while the two chroma channels are given alternatively on every other clock period. The average bit amount of Y is twice that of Cb or Cr. Depending on the bus width, each component could take on different lengths. The DE period should contain an even number of clock periods. Figure 6 gives a timing example of 16-bit YCbCr 4:2:2. The 20-bit and 24-bit versions are similar. 讯 科 Table 5. Mappings of YCbCr 4:2:2 with separate syncs 合 blank Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... blank D[23:16] val Cbpix0 [7:0] Crpix0 [7:0] Cbpix2 [7:0] Crpix2 [7:0] Cbpix4 [7:0] Crpix4 [7:0] Cbpix6 [7:0] .... val val val D[15:8] val Ypix0 [7:0] Ypix1 [7:0] Ypix2 [7:0] Ypix3 [7:0] Ypix4 [7:0] Ypix5 [7:0] Ypix6 [7:0] .... val val val 市 金 圳 深 Pixel0 D[7:0] PCLK DE H/VSYNC Figure 6. 16-bit YCbCr 4:2:2 with separate syncs 18 18 CAT6611 Single-Link HDMI Transmitter Data Sheet YCbCr 4:2:2 with Embedded Syncs This is similar to the previous format. The only difference is that the syncs are embedded. Bus width could be 16-bit, 20-bit or 24-bit. Figure 7 gives a timing example of 16-bit YCbCr 4:2:2. The 20-bit and 24-bit versions are similar. 18 66 4 34 1 58 5 Te ， 71 44 51 8 19 ， 廖 R YCbCr 4:2:2 24-bit Pixel#2N Pixel#2N+1 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y10 Y10 Y11 Y11 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 grounded grounded grounded grounded grounded grounded QQ : YCbCr 4:2:2 20-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded Y0 Y0 Y1 Y1 grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cb8 Cb9 Cb9 grounded grounded grounded grounded grounded grounded l: YCbCr 4:2:2 16-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 grounded grounded grounded grounded grounded grounded 司 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE val val val val Cbpix0 [7:0] Crpix0 [7:0] Cbpix2 [7:0] Crpix2 [7:0] Cbpix4 [7:0] Crpix4 [7:0] .... val FF 00 00 XY Ypix0 [7:0] Ypix1 [7:0] Ypix2 [7:0] Ypix3 [7:0] Ypix4 [7:0] Ypix5 [7:0] .... val 讯 科 D[23:16] 技 有 限 公 Table 6. Mappings of YCbCr 4:2:2 with embedded syncs Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 ... blank 合 D[15:8] SAV 深 圳 市 金 D[7:0] PCLK DE H/VSYNC Figure 7. 16-bit YCbCr 4:2:2 with embedded syncs 19 19 CAT6611 Single-Link HDMI Transmitter Data Sheet CCIR-656 Format 18 66 4 34 1 58 5 Te ， 司 公 限 技 有 71 44 51 8 CCIR-656 12-bit Pixel#2N Pixel#2N+1 C0 Y0 C1 Y1 C2 Y2 C3 Y3 grounded grounded grounded grounded grounded grounded grounded grounded C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y9 C9 Y9 C10 Y10 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded QQ : CCIR-656 10-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded C0 Y0 C1 Y1 grounded grounded grounded grounded grounded grounded grounded grounded C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded l: CCIR-656 8-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Table 7. Mappings of CCIR-656 深 圳 市 金 合 讯 科 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 19 ， 廖 R The CCIR-656 format is yet another variation of the YCbCr formats. The bus width is further reduced by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit, 10-bit or 12-bit. To compensate for the halving of data bus, PCLK is doubled. With the double-rate input clock, luminance channel (Y) and chroma channels (Cb or Cr) are alternated. CAT6611 supports CCIR-656 format of up to 720p or 1080i, with the doubled-rate clock running at 148.5MHz. CCIR-656 format supports embedded syncs only. Figure 8 gives an example of 8-bit CCIR-656. 10-bit and 12-bit versions are similar. Figure 8. 8-bit CCIR-656 20 20 CAT6611 Single-Link HDMI Transmitter Data Sheet CCIR-656 + separate syncs This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus separate syncs. QQ : 71 44 51 8 19 ， 廖 R CCIR-656 12-bit Pixel#2N Pixel#2N+1 C0 Y0 C1 Y1 C2 Y2 C3 Y3 grounded grounded grounded grounded grounded grounded grounded grounded C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y9 C9 Y9 C10 Y10 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE 18 66 4 34 1 58 5 CCIR-656 10-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded C0 Y0 C1 Y1 grounded grounded grounded grounded grounded grounded grounded grounded C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE Te l: CCIR-656 8-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE ， Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE D[23:16] 讯 科 D[15:8] 技 有 限 公 司 Table 8. Mappings of CCIR-656 + separate syncs val blank val val Pixel0 val Cbpix0 [7:0] Ypix0 [7:0] Pixel1 Crpix0 [7:0] Ypix1 [7:0] Pixel2 Cbpix2 [7:0] Ypix2 [7:0] ... .... blank val 深 圳 市 金 合 D[7:0] PCLK DE H/VSYNC Figure 9. 8-bit CCIR-656 + separate syncs 21 21 CAT6611 Single-Link HDMI Transmitter Data Sheet 12-bit RGB and YCbCr 4:4:4 Using Dual-Edge Triggering 19 ， 51 8 71 44 QQ : 58 5 66 4 18 l: Te ， YCbCr 1st edge 2nd edge Cb0 Y4 Cb1 Y5 Cb2 Y6 Cb3 Y7 Cb4 Cr0 Cb5 Cr1 Cb6 Cr2 Cb7 Cr3 Y0 Cr4 Y1 Cr5 Y2 Cr6 Y3 Cr7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE 34 1 RGB 1st edge 2nd edge B0 G4 B1 G5 B2 G6 B3 G7 B4 R0 B5 R1 B6 R2 B7 R3 G0 R4 G1 R5 G2 R6 G3 R7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 廖 R This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus separate syncs. 深 圳 市 金 合 讯 科 技 有 限 公 司 Table 9. Mappings of 12-bit 4:4:4 dual-edge triggered Figure 10. 12-bit RGB 4:4:4 dual-edge triggered 22 22 CAT6611 Single-Link HDMI Transmitter Data Sheet System Design Consideration To get the optimum performance of CAT6611, the system designers should follow the guideline below when designing the application circuits and PCB layout. 19 ， 廖 R 1. Pin 23 (PVCC1) should be supplied with clean power: ferrite-decoupled and capacitivelybypassed, since this is the power for the transmitter PLL, which is crucial in determining the TMDS output signal quality . Excess power noise might degrade the system performance. 58 5 QQ : 71 44 51 8 2. The characteristic impedance of all differential PCB traces (TX2P/M, TX1P/M, TX0P/M, TXCP/M) should be kept 100Ω all the way from the HDMI connector to CAT6611. This is very crucial to the system performance at high speeds. When layouting these 4 differential transmission lines (8 single-ended lines in total), the following guidelines should be followed: A. The signals traces should be on the outside layers (e.g. TOP layer) while beneath it there should be a continuous ground plane in order to maintain the called micro-strip structure, giving stable and well-defined characteristic impedances. B. Cornering, through holes, crossing and any irregular signal routing should be avoided so as to 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 prevent from disrupting the EM field and creating discontinuity in characteristic impedance. C. CAT6611 should be placed as close to the HDMI connector as possible. Since the TMDS signal pins of CAT6611 perfectly match the order of the connector pins, it is very convenient to route the signal directly into the chip, without through holes or angling. D. Carefully choose the width and spacing of the differential transmission lines as their characteristic impedance depends on various parameters of the PCB: trace width, trace spacing, copper thickness, dielectric constant, dielectric thickness, etc. Careful 3D EM simulation is the best way to derive a correct dimension that enables a nominal 100Ω differential impedance. Please contact us directly for technical support of this issue. A layout example (without ESD diodes) is as follows: 37 DATA2+ 36 GND 35 DATA2- 34 DATA1+ 33 GND 32 DATA1- 31 DATA0+ 30 GND 29 DATA0- 28 CLOCK+ 27 GND 26 CLOCK- 25 CEC 24 reserved 23 SCL 21 SDA GND +5V HPD Figure 11. PCB layout example of high-speed transmission lines without ESD dioes 23 23 CAT6611 Single-Link HDMI Transmitter Data Sheet 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R 3. Special care should be taken when adding discrete ESD devices to all differential PCB traces (TX2P/M, TX1P/M, TX0P/M, TXCP/M). CAT6611 is designed to provide ESD protection for up to 2kV at these pins. Adding discrete ESD diodes could enhance the ESD capability, but at the same time will inevitably add capacitive loads, therefore degrade the electrical performance at high speeds. If not chosen carefully, these diodes coupled with less-than-optimal layout could prevent the system from passing the SOURCE TMDS Data Eye Diagram test in the HDMI Compliance Test (Test ID 7-10). Besides, most general-purpose ESD diodes are relatively large in size, forcing the high-speed differential lines to corner several times and therefore introducing severe reflection. Carefully choosing an ESD diode that's designed for HDMI signalling could lead to a minimum loading as well as an optimized layout. Commercially available devices such as Semtech's RClamp0514M that take into consideration of all aspects are recommended. (http://semtech.com/ products/product-detail.jsp?navId=RClamp0514M). An layout example using short 140Ω differential transmission lines to compensate for the capacitances of RClamp0514M is as follows, with referenced FR4 PCB structure included: 讯 科 Figure 12. PCB layout guide and example for high-speed transmission lines with RClamp0514 深 圳 市 金 合 4. Pin 24 (REXT) should be connected to AVCC via a 476Ω/1% precision SMD resistor. This resistor is used to calibrate the TMDS output current level to the nominal value of 10mA. The resistor should be placed as close to CAT6611 as possible. 24 24 CAT6611 Single-Link HDMI Transmitter Data Sheet 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R 80-pin TQFP Package Dimensions Figure 13. Package dimensions of TQFP-80 Notes: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 25 25 CAT6611 Single-Link HDMI Transmitter Data Sheet Revision History 0.9 2006/08/14 1.0 2006/12/15 Pages Changes 8, 26 Package updated from LQFP-80 to TQFP-80 12 Junction to ambient thermal resistance changed from 50 廖 R Revision Date to 40°C/W 9 Modify the pixel clock frequencies of the input video formats supported by CAT6611 regarding 720p and 1080i 12 Update operational voltage of IVDD from ±10% to ±5% 19 ， 2006/12/21 32kBytes => 32 bytes 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 1.0a 11 26 26