Revised January 1999 CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches General Description Features The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3STATE CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. There is a common 3-STATE ENABLE input for all four latches. A logic “1” on the ENABLE input connects the latch states to the Q outputs. A logic “0” on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-STATE feature allows common bussing of the outputs. ■ Wide supply voltage range: 3V to 15V ■ Low power: 100 nW (typ.) ■ High noise immunity: 0.45 VDD (typ.) ■ Separate SET and RESET inputs for each latch ■ NOR and NAND configuration ■ 3-STATE output with common output enable Applications • Multiple bus storage • Strobed register • Four bits of independent storage with output enable • General digital logic Ordering Code: Order Number CD4043BCM Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4043BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4044BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4044BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4044BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4043BC Pin Assignments for DIP and SOIC CD4044BC Top View Top View © 1999 Fairchild Semiconductor Corporation DS005967.prf www.fairchildsemi.com CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches October 1987 CD4043BC • CD4044BC Block Diagrams CD4043BC CD4044BC Truth Tables CD4044BC CD4043BC S R E Q S R E Q X X 0 OC X X 0 OC 0 0 1 NC 1 1 1 NC 1 0 1 1 0 1 1 1 0 1 1 0 1 0 1 0 1 1 1 ∆ 0 0 1 ∆∆ OC = 3-STATE NC = No change X = Don’t care ∆ = Dominated by S = 1 input ∆∆ = Dominated by R = 0 input www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +18V Supply Voltage (VDD) (Note 2) −0.5V to VDD +0.5V Input Voltage (VIN) Storage Temperature Range (TS) Supply Voltage (VDD) −65°C to +150°C 3.0V to 15V Input Voltage (VIN) Power Dissipation (PD) 0 to VDD V Operating Temperature Range (TA) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) −40°C to +85°C CD4043BC, CD4044BC Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. 260°C Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics Symbol IDD VOL VOH VIL VIH IOL IOH IIN Parameter (Note 2) −40°C Conditions Min +25°C Max Min +85°C Typ Max Min Max Units Quiescent VDD = 5V, VIN = VDD or VSS 20 0.01 20 150 µA Device Current VDD = 10V, VIN = VDD or VSS 40 0.01 40 300 µA VDD = 15V, VIN = VDD or VSS 80 0.02 80 600 µA LOW Level |IO| ≤ 1 µA, VIL = 0V, VIH = VDD Output Voltage VDD = 5.0V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V HIGH Level |IO| ≤ 1 µA, VIL = 0V, VIH = VDD Output Voltage VDD = 5.0V 4.95 4.95 5.0 4.95 VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V V LOW Level |IO| ≤ 1 µA Input Voltage VDD = 5.0V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V VDD = 10V, VO = 1.0V or 9.0V 3.0 4.5 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V HIGH Level |IO| ≤ 1 µA Input Voltage VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V VDD = 5.0V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11 11 11 V LOW Level VIL = 0V, VIH = VDD Output Current VDD = 5.0V, VO = 0.4V 0.52 0.44 0.88 0.36 mA (Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.2 0.9 mA VDD = 15V, VO = 1.5V 3.6 3.0 6.0 2.4 mA HIGH Level VIL = 0V, VIH = VDD Output Current VDD = 5.0V, VO = 4.6V −0.52 −0.44 −0.32 −0.36 mA (Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −0.8 −0.9 mA VDD = 15V, VO = 13.5V −3.6 −3.0 −2.4 −2.4 Input Current VDD = 15V, VIN = 0V −0.3 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 0.3 1.0 µA mA Note 3: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4043BC • CD4044BC Absolute Maximum Ratings(Note 1) (Note 2) CD4043BC • CD4044BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise noted Symbol tPLH, tPHL tPZH, tPHZ tPZL, tPLZ tTHL, tTLH tWO Parameter Propagation Delay S or R to Q Propagation Delay Enable to Q (HIGH) Propagation Delay Enable to Q (LOW) Transition Time Minimum SET or RESET Pulse Width Typ Max Units VDD = 5.0V Conditions 175 350 ns VDD = 10V 75 175 ns VDD = 15V 60 120 ns VDD = 5.0V 115 230 ns VDD = 10V 55 110 ns VDD = 15V 40 80 ns VDD = 5.0V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns VDD = 5.0V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns VDD = 5.0V 80 160 ns VDD = 10V 40 80 ns VDD = 15V CIN Input Capacitance Min 20 40 ns 5.0 7.5 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Timing Waveforms CD4043B CD4044B Enable Timing www.fairchildsemi.com 4 CD4043BC • CD4044BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.