CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 Dual 1:2 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2102 FEATURES 1 • • • • • • • • • • • • Dual 1:2 Differential Buffer Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz Low Within Bank Output Skew of 15 ps (Max) Universal Inputs Accept LVDS, LVPECL, LVCMOS One Input Dedicated for Two Outputs Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible Clock Frequency up to 800 MHz 2.375–2.625V Device Power Supply LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs Industrial Temperature Range –40°C to 85°C Packaged in 3mm × 3mm 16-Pin QFN (RGT) ESD Protection Exceeds 3 kV HBM, 1 kV CDM APPLICATIONS • • • • • DESCRIPTION The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD2102 is specifically designed for driving 50-Ω transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal. The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package. Telecommunications/Networking Medical Imaging Test and Measurement Equipment Wireless Communications General Purpose Clocking 200 MHz PHY2 DAC2 Clock Generation EN CDCLVD2102 100 MHz ADC2 Figure 1. Application Example 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. VCC VAC_REF Reference Generator INP0 OUTP [0..1] LVDS INN0 OUTN [0..1] INP1 OUTP [2..3] LVDS INN1 OUTN [2..3] VCC 200 kW EN 200 kW GND Figure 2. CDCLVD2102 Block Diagram OUTP2 OUTN1 OUTP1 OUTN0 OUTP0 TOP VIEW 12 11 10 9 13 OUTN2 14 OUTP3 15 3mm x 3mm 16 pin QFN (RGT) 8 VAC_REF 7 INN0 6 INP0 5 VCC Thermal Pad 2 1 2 3 4 EN INP1 INN1 16 GND OUTN3 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 PIN FUNCTIONS PIN NAME TYPE DESCRIPTION NO. VCC GND 5 Power 2.5V supplies for the device Device ground 1 Ground INP0, INN0 6, 7 Input Differential input pair or single ended input INP1, INN1 3, 4 Input Differential redundant input pair or single ended input 8 Output Bias voltage output for capacitive coupled inputs. If used, it is recommended to use a 0.1µF to GND on this pin OUTP0, OUTN0 9, 10 Output Differential LVDS output pair no. 0 OUTP1, OUTN1 11, 12 Output Differential LVDS output pair no. 1 OUTP2, OUTN2 13, 14 Output Differential LVDS output pair no. 2 OUTP3, OUTN3 15, 16 Output Differential LVDS output pair no. 3 2 Input with internal 200kΩ pull-up and pull-down VAC_REF EN Thermal Pad INP0/INN0 is the input INP1/INN1 is the input Control pin – enables or disables the outputs, (See Table 1) See thermal management recommendations Table 1. Output Control Table EN 0 OPEN 1 CLOCK OUTPUTS All outputs disabled (static "0") All outputs enabled OUT0, OUT1 enabled and OUT2, OUT3 disabled (static "0") ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT Supply voltage range, VCC –0.3 to 2.8 V Input voltage, VI –0.2 to (VCC + 0.2) V Output voltage range, VO –0.2 to (VCC + 0.2) V Driver short circuit current, IOSD See Note Electrostatic discharge (HBM, 1.5 kΩ, 100 pF) (1) (2) (2) >3000 V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. The outputs can handle permanent short. RECOMMENDED OPERATING CONDITIONS Device supply voltage, VCC Ambient temperature, TA MIN TYP MAX 2.375 2.5 2.625 –40 85 UNITS V oC Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 3 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com THERMAL INFORMATION CDCLVD2102 THERMAL METRIC (1) RGT UNITS 16 PINS qJA Junction-to-ambient thermal resistance 51.3 qJC(top) Junction-to-case(top) thermal resistance 85.4 qJB Junction-to-board thermal resistance 20.1 yJT Junction-to-top characterization parameter 1.3 yJB Junction-to-board characterization parameter 19.4 qJC(bottom) Junction-to-case(bottom) thermal resistance 6 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS: At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN PIN INPUT CHARACTERISTICS VdI3 3-State VdIH Input high voltage Open VdIL Input low voltage IdIH Input high current VCC = 2.625 V, VIH = 2.625 V IdIL Input low current VCC = 2.625 V, VIL = 0 V Rpull(EN) Input pull-up/ pull-down resistor 0.5×VCC V 0.7×VCC V 0.2×VCC V 30 mA –30 mA 200 kΩ 2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS fIN Input frequency External threshold voltage applied to complementary input Vth Input threshold voltage VIH Input high voltage VIL Input low voltage IIH Input high current VCC = 2.625 V, VIH = 2.625 V IIL Input low current VCC = 2.625 V, VIL = 0 V ΔV/ΔT Input edge rate 20% – 80% CIN Input capacitance 200 MHz 1.5 V Vth + 0.1 VCC V 0 Vth – 0.1 V 10 mA 1.1 –10 1.5 mA V/ns 2.5 pF DIFFERENTIAL INPUT CHARACTERISTICS fIN Input frequency Clock input VIN, Differential input voltage peak-to-peak VICM = 1.25 V VICM Input common-mode voltage range VIN, DIFF, PP > 0.4V IIH Input high current VCC = 2.625 V, VIH = 2.625 V IIL Input low current VCC = 2.625 V, VIL = 0 V ΔV/ΔT Input edge rate 20% to 80% CIN Input capacitance 4 DIFF 800 MHz 0.3 1.6 VP-P 1 VCC – 0.3 V 10 mA –10 mA 0.75 V/ns 2.5 Submit Documentation Feedback pF Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS: (continued) At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250 450 mV –15 15 mV 1.1 1.375 –15 15 LVDS OUTPUT CHARACTERISTICS |VOD| Differential output voltage magnitude ΔVOD Change in differential output voltage magnitude VOC(SS) Steady-state common mode output voltage ΔVOC(SS) Steady-state common mode output voltage VIN, DIFF, PP = 0.6 V,RL = 100 Ω Vring Output overshoot and undershoot Percentage of output amplitude VOD VOS Output ac common mode VIN, DIFF, PP = 0.6 V, RL = 100 Ω IOS Short-circuit output current VOD = 0 V tPD Propagation delay VIN, DIFF, PP = 0.3 V tSK, PP Part-to-part skew tSK, O_WB Within bank output skew tSK,O_BB Bank-to-bank output skew Both inputs are phase aligned tSK,P Pulse skew(with 50% duty cycle input) Crossing-point-to-crossing-point distortion tRJIT Random additive jitter (with 50% duty cycle input) Edge speed = 0.75V/ns, 10 kHz – 20 MHz tR/tF Output rise/fall time 20% to 80%,100 Ω, 5 pF 300 ps ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 27 45 mA ICC100 Supply current All outputs enabled, RL = 100 Ω, f = 100 MHz 49 77 mA ICC800 Supply current All outputs enabled, RL = 100 Ω, f = 800 MHz 76 106 mA 1.25 1.35 V VIN, DIFF, PP = 0.3 V,RL = 100 Ω V mV 10% 25 1.5 –50 70 mVPP ±24 mA 2.5 ns 600 ps 15 ps 100 ps 50 ps 0.3 ps, RMS 50 VAC_REF CHARACTERISTICS VAC_REF Reference output voltage VCC = 2.5 V, Iload = 100 µA 1.1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 5 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com Typical Additive Phase Noise Characteristics for 100 MHz Clock PARAMETER MIN TYP MAX UNIT phn100 Phase noise at 100 Hz offset -132.9 dBc/Hz phn1k Phase noise at 1 kHz offset -138.8 dBc/Hz phn10k Phase noise at 10 kHz offset -147.4 dBc/Hz phn100k Phase noise at 100 kHz offset -153.6 dBc/Hz phn1M Phase noise at 1 MHz offset -155.2 dBc/Hz phn10M Phase noise at 10 MHz offset -156.2 dBc/Hz phn20M Phase noise at 20 MHz offset -156.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS Typical Additive Phase Noise Characteristics for 737.27 MHz Clock PARAMETER phn100 Phase noise at 100 Hz offset phn1k Phase noise at 1 kHz offset phn10k Phase noise at 10 kHz offset phn100k MIN TYP MAX UNIT -80.2 dBc/Hz -114.3 dBc/Hz -138 dBc/Hz Phase noise at 100 kHz offset -143.9 dBc/Hz phn1M Phase noise at 1 MHz offset -145.2 dBc/Hz phn10M Phase noise at 10 MHz offset -146.5 dBc/Hz phn20M Phase noise at 20 MHz offset -146.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES vs FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V) Input clock jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs Figure 3. 100 MHz Input and Output Phase Noise Plot Differential Output Voltage vs Frequency VOD − Differential Output Voltage − mV 350 TA = 25oC 340 2.625V 330 320 2.5V 310 300 2.375V 290 280 270 260 250 0 100 200 300 400 500 600 700 800 Frequency − MHz Figure 4. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 7 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com TEST CONFIGURATIONS Oscilloscope 100 W LVDS Figure 5. LVDS Output DC Configuration During Device Test Phase Noise Analyzer LVDS 50 W Figure 6. LVDS Output AC Configuration During Device Test Figure 7. DC Coupled LVCMOS Input During Device Test VOH OUTNx VOD OUTPx VOL 80% VOUT,DIFF,PP (= 2 x VOD) 20% 0V tr tf Figure 8. Output Voltage and Rise/Fall Time 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 INNx INPx tPLH0 tPHL0 tPLH1 tPHL1 OUTN0 OUTP0 OUTN1 OUTP1 tPLH2 tPHL2 OUTN2 OUTP2 OUTN3 tPLH3 tPHL3 OUTP3 A. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3). B. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, 3). C. Both inputs (IN0 and IN1) are phase aligned. Figure 9. Output Skew and Part-to-Part Skew Vring OUTNx VOD 0V Differential OUTPx Figure 10. Output Overshoot and Undershoot VOS GND Figure 11. Output AC Common Mode Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 9 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com APPLICATION INFORMATION THERMAL MANAGEMENT For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The Thermal Pad must be soldered down to ensure adequate heat conduction to of the package. Figure 12 shows a recommended land and via pattern. Figure 12. Recommended PCB Layout POWER-SUPPLY FILTERING High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is critical to applications. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with very low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. Board Supply Chip Supply Ferrite Bead 1 µF 10 µF 0.1 µF Figure 13. Power-Supply Decoupling 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 LVDS OUTPUT TERMINATION The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage different than the output common mode voltage of the CDCLVD2102, ac-coupling should be used. If the LVDS receiver has internal 100 ohm termination, external termination must be omitted. Unused outputs can be left open without connecting any trace to the output pins. Z = 50 W 100 W CDCLVD2102 LVDS Z = 50 W Figure 14. Output DC Termination 100 nF Z = 50 W 100 W CDCLVD2102 LVDS Z = 50 W 100 nF Figure 15. Output AC Termination With Receiver Internally Biased INPUT TERMINATION The CDCLVD2102 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers. LVDS Driver can be connected to CDCLVD2102 inputs with dc or ac coupling as shown Figure 16 and Figure 17, respectively. Z = 50 W 100 W LVDS CDCLVD2102 Z = 50 W Figure 16. LVDS Clock Driver Connected to CDCLVD2102 Input (DC Coupled) 100 nF Z = 50 W LVDS CDCLVD2102 Z = 50 W 100 nF 50 W 50 W VAC_REF Figure 17. LVDS Clock Driver Connected to CDCLVD2102 Input (AC Coupled) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 11 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com Figure 18 shows how to connect LVPECL inputs to the CDCLVD2102. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP. 75 W 100 nF Z = 50 W CDCLVD2102 LVPECL Z = 50 W 100 nF 75 W 150 W 150 W 50 W 50 W VAC_REF Figure 18. LVPECL Clock Driver Connected to CDCLVD2102 Input Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2102 directly. The series resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs to be limited to VIH ≤ VCC. RS LVCMOS (2.5V) Z = 50 W CDCLVD2102 V V Vth = IH + IL 2 Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD2102 Input If one of the buffers is used, then the other unused buffer should be disabled through the EN pin, and the unused input pins should be grounded by 1kΩ resistors. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 REVISION HISTORY Changes from Original (May 2010) to Revision A Page • Changed Features bullet From: ESD Protection Exceeds 2kV HBM, 500V CDM To: ESD Protection Exceeds 3 kV HBM, 1 kV CDM ................................................................................................................................................................... 1 • Electrostatic discharge was <2000 ....................................................................................................................................... 3 • ΔVOD values, MIN was-50, MAX was 50 .............................................................................................................................. 5 • VOC(SS) MIN value was 1.125 ................................................................................................................................................ 5 • ΔVOC(SS) values, MIN was-50, MAX was 50 .......................................................................................................................... 5 • Vring MAX value was 20% ..................................................................................................................................................... 5 • VOS values, TYP was 30, MAX was 100 ............................................................................................................................... 5 • tPD MAX value was 2 ............................................................................................................................................................. 5 • tSK, PP - deleted the TYP value of 300 ................................................................................................................................... 5 • tR/tF MIN value was 200 ........................................................................................................................................................ 5 • ICCSTAT MAX value was 42 .................................................................................................................................................... 5 • Added new paragraph following Figure 19 ......................................................................................................................... 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 13 PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CDCLVD2102RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples CDCLVD2102RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CDCLVD2102RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 CDCLVD2102RGTT QFN RGT 16 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD2102RGTR QFN RGT 16 3000 338.1 338.1 20.6 CDCLVD2102RGTT QFN RGT 16 250 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated