SONY CXG1121TN

CXG1121TN
SP4T GSM/GPRS Dual-Band Antenna Switch + Logic
Description
The CXG1121TN is one of a range of low insertion
loss, high power MMIC antenna switches for GSM/
GPRS dual-band application. The low insertion loss
on transmit means increased talk time as the Tx
power amplifier can be operated at a lower output
level. On-chip logic reduces component count and
simplifies PWB layout by allowing direct connection
of the switch to digital base band control lines with
CMOS logic levels.
This switch is an SP4T, one antenna can be routed
to either of the 2 Tx or 2 Rx ports. It requires 3 CMOS
control lines (Tx/Rx, GSM900/1800 and Standby).
The Sony GaAs JFET process is used for low
insetion loss. An evaluation PWB is available.
16 pin TSSOP (Plastic)
Features
• Insertion loss (Tx) 0.5dB typical at 34dBm (GSM900)
• 3 CMOS compatible control lines
• Low second harmonic, –40dBm typical, at 34dBm (GSM900)
• Small package size: 16-pin TSSOP (3.9mm × 4.1mm × 1.2mm)
Applications
• Dual-band handsets using combinations of GSM900/GSM1800/GSM1900
• GPRS class 12 handsets
Structure
GaAs J-FET MMIC
Absolute Maximum Ratings (Ta = 25°C)
• Bias voltage
VDD
7
• Control voltage
VCTL
5
• Operating temperature Topr
–20 to +80
V
V
°C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required. The IC will be damaged in
the range from 100 to 200V @200pF 0Ω and below 1000V @100pF 1500Ω.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01661-PS
CXG1121TN
Pin Configuration
9
8
Tx1
GND 10
7
GND
ANT 11
6
Tx2
GND 12
5
GND
VDD 13
4
Rx1
GND 14
3
GND
Band Select 15
2
Rx2
Tx/Rx 16
1
STDBY
GND
Truth Table
On Pass
Band select
Tx (H) / Rx (L)
Standby
ANT – Tx1 DCS1800
H
H
H
ANT – Tx2 GSM900
L
H
H
ANT – Rx1 GSM900/DCS1800
L
L
H
ANT – Rx2 GSM900/DCS1800
H
L
H
OFF
—
—
L
–2–
CXG1121TN
Electrical characteristics
Item
(Ta = 25°C)
Port
Symbol
Insertion loss
IL
Isolation
ISO
VSWR
Unit
0.5
0.7
dB
Tx1 – ANT
∗2
0.6
0.8
dB
ANT – Rx1
∗3
0.55
0.75
dB
ANT – Rx2
∗4
0.7
0.9
dB
ANT – Tx1
∗3
20
dB
ANT – Tx2
∗4
17
dB
Tx2 – Rx1, Rx2
∗1
20
dB
Tx1 – Rx1, Rx2
∗2
20
dB
1.2
2fo
∗1
–40
–36
dBm
∗1
–34
–30
dBm
∗2
DCS Tx – ANT
–40
–36
dBm
∗2
–34
–30
dBm
GSM Tx – ANT
∗1
36
dBm
DCS Tx – ANT
∗2
36
dBm
GSM Tx – ANT
3fo
Harmonics∗
Max.
Tx2 – ANT
VSWR
Min.
Typ.
Condition
∗1
2fo
3fo
P1dB compression input
power
P1dB
Control current
ICTL
VCTL = 3V
80
120
µA
Supply current
IDD
STBY = H
0.5
1.0
mA
Leakage current
IIK
STBY = L
90
µA
Electrical characteristics are measured with all RF ports terminated in 50Ω.
∗ Harmonics measured with Tx inputs harmonically matched. The use of harmonic matching is recommended
to ensure optimum performance.
∗1
∗2
∗3
∗4
Power
Power
Power
Power
incident
incident
incident
incident
on
on
on
on
GSM Tx, Pin = 34dBm, 880 to 915MHz, VDD = 5.0V, GSM Tx enabled
DCS Tx, Pin = 32dBm, 1710 to 1785MHz, VDD = 5.0V, DCS Tx enabled
ANT, Pin = 10dBm, 925 to 960MHz, VDD = 5.0V, GSM Rx enabled
ANT, Pin = 10dBm, 1805 to 1880MHz, VDD = 5.0V, DCS Rx enabled
Supply Voltage Value (VDD)
Mode
Min.
Typ.
Max.
Unit
GSM/DCS Tx
4.5
5
5.7
V
GSM/DCS Rx
2.7
3
4
V
Min.
Typ.
Max.
Unit
High
2.4
2.8
3.2
V
Low
0
0.4
V
CMOS Logic Value
Logic
–3–
CXG1121TN
Recommended Circuit
9
GND
Tx1
8
47pF
10 GND
GND
7
11 ANT
Tx2
6
22pF
47pF
12 GND
GND
5
13 VDD
Rx1
4
100pF
47pF
14 GND
15 Band Select
GND
3
Rx2
2
100pF
22pF
STDBY
16 Tx/Rx
100pF
1
100pF
Note) Capacitors are required on all RF ports for DC blocking (22pF – 47pF). Decoupling capacitors are
required on VDD and on control lines (100pF).
–4–
CXG1121TN
Application Note (1)
Operating from Regulated Supplies between 3V and 2.7V
Logic Lines
8
Tx1
6
Tx2
CXG1121TN
4
Rx1
2
Rx2
11
VDD between
5.7V and 4.5V
during Tx
13
VDD
Additional components
C: 0603 CAP µF∗2
R: 200R
D: Low Turn-on voltage diode
ANT
∗1
C
D
Timeslot
waveform
R
Regulated supply
between 3V and 2.7V
Technique
Allows use of CXG1121TN SP4T in handsets with regulated supplies between 3V and 2.7V.
The CXG1121TN is for 5V nominal battery voltage but works well down to a VDD of 4.5V.
This technique is only necessary for Tx modes.
Fundamentally, the timeslot waveform is added to the supply voltage to give a VDD between 5.7V and 4.5V
(depending on supply) during Tx modes.
This technique is suitable for up to 4 consecutive Tx timeslots (i.e.GPRS Class 12).
∗1 This waveform may be taken from the PA ramping input (or drain supply in case of drain power control) or
via the Tx ON/OFF logic.
∗2 Minimum and recommended value of capacitance C depends on GPRS class and is given by the following
table.
Number of consecutive
Tx timeslots
Minimum and recommended
value of capacitance C (µF)
1
1.0
2
2.0
4
2.0
–5–
CXG1121TN
Application Note (2)
Impedance Matching for Harmonic Minimization
This note outlines the method used to find the source impedance to present to a transmit port at the second
harmonic frequency (2fo) to reduce the second harmonic level at the antenna.
This should be carried out for a set of devices that represent the process variants. This way a compromise can
be found that suits all variants.
The necessary equipment is shown immediately below.
Power Meter
Fundamental, fo
Signal
Generator
B.P.F.
10dB
Coupler
Second Harmonic, 2fo
Diplexer
Load Pull
Tuner
DC Block
D.U.T.
DC Block
Spectrum
Analyzer
The device should be mounted on a PWB with 50Ω tracks running from all RF pins to SMA connectors on the
PWB edge (DUT). All ports should be externally DC blocked and unused ports should be terminated in 50Ω. All
measurements should be performed at the incident powers for which the harmonic levels are specified in this
document.
The 2nd harmonic level at the antenna port is measured using the spectrum analyzer and the vertical and
horizontal position of the load pull stub adjusted such that this level is minimized.
The device should then be removed from the board and an SMA connector mounted such that the source
impedance seen by the transmit port at 2fo can be measured using a VNA.
Measurements should be de-embedded to the end of the SMA center pin.
A network should then be designed to match the impedance of the low pass filter (LPF), which usually comes
in front of the device, to the 2fo source impedance that gives sufficiently reduced 2fo levels for all devices
measured.
The network should be designed to maintain a good match and insertion loss at the fundamental frequency.
–6–
CXG1121TN
Package Outline
Unit: mm
16PIN TSSOP (PLASTIC)
1.2MAX
4.1
S
2.05
A
16
B
0.08 S
X2
9
0.2
S A B
3.9
(3.0)
0.1 ± 0.05
0.25
0.1
2.9
0.1
X
X
8
X4
0.1
0.5
S A B
0.45 ± 0.1
1
0˚ to 8˚
0.08 M S A
0.2 ± 0.02
+ 0.036
0.22 – 0.03
DETAIL B
0.1 ± 0.01
+ 0.026
0.12 – 0.02
B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.03g
TSSOP-16P-L01
SONY CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
–7–
Sony Corporation