SONY CXK77B1840GB 4A/4/45A/45 4Mb Late Write HSTL High Speed Synchronous SRAM (256K x 18 Organization) Description The CXK77B1840 is a high speed BiCMOS synchronous static RAM with common I/O pins, organized as 262,144-words by 18-bits. This synchronous SRAM integrates input registers, high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Four different read protocols - Register-Register (R-R), Register-Latch (R-L), Register-Flow Thru (R-FT), and Dual Clock (DC), and an enhanced write protocol - Late (Delayed) Write (LW), are supported, providing a flexible, high-performance user interface. All input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge of K clock. Read cycles can be controlled in one of four ways - with registered outputs in Register-Register mode, with latched outputs in Register-Latch mode, with flow-through outputs in Register-Flow Thru mode, or with registered outputs using a dedicated output control clock (C clock) in Dual Clock mode. The read protocol is user-selectable through external mode pins M1 and M2. Write cycles follow a Late Write protocol, where data is provided to the SRAM one clock cycle after the address and control signals, eliminating one dead cycle from Read-to-Write transitions. In this scheme, when a write cycle is initiated, the address and data stored in the SRAM’s write buffer during the previous write cycle are directed to the SRAM’s memory core, while, simultaneously, the address and data from the current write cycle are stored in the SRAM’s write buffer. In both Register-Latch and Register-Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tristates the SRAM’s output drivers immediately, allowing consecutive Read-Write-Read operations. The write cycle is internally self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. The output drivers are series terminated, and the output impedance is programmable through an external impedance matching resistor RQ. By connecting RQ between ZQ and V SS, the output impedance of all 18 DQ pins can be precisely controlled. Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol. Features R-R Mode R-L, R-FT Modes • Fast Cycle/Access Time tKHKH / tKHQV tKHKH / tKHQV CXK77B1840 -4A 4.0ns / 2.3ns 4.8ns / 4.8ns -4 4.0ns / 2.3ns 5.3ns / 5.3ns -45A 4.0ns / 2.3ns 5.3ns / 5.3ns -45 5.0ns / 2.5ns 6.5ns / 6.5ns Note: Contact Sony Memory Marketing for availability of DC mode functionality. • 4 synchronous modes of operation, selectable by mode pins: Register-Register; Register-Latch; Register-Flow Thru; Dual Clock • Single +3.3V power supply: 3.3V ± 5% **DC Mode** tKHKH / tKHQV 4.0ns / 5.2ns 4.0ns / 5.2ns 4.5ns / 6.0ns 4.5ns / 6.5ns • Dedicated output supply voltage: VDDQ (1.5V typical) • Inputs and outputs are HSTL / extended HSTL compatible. • Differential clock input (K/K, C/C). • All inputs (except asynchronous G and ZZ) and outputs are registered on a single clock edge. • Byte Write capability. • Late Write scheme to eliminate one dead cycle from Read-to-Write transitions. • Self-timed write cycles. • Sleep (power down) mode. • JTAG boundary scan (subset of IEEE standard 1149.1). • 119 pin (7x17) Plastic Ball Grid Array (PBGA) package. 256Kx18, Sync LW, HSTL, rev 4.6 1 / 27 August 20, 1998 SONY® CXK77B1840GB Pin Configuration (Top View) 1 2 3 4 5 6 7 A VDDQ SA6 SA7 NC SA3 SA2 VDDQ B NC NC SA8 NC SA4 NC NC C NC SA12 SA5 VDD SA0 SA13 NC D DQ0b NC VSS ZQ VSS DQ8a NC E NC DQ1b VSS SS VSS NC DQ7a F VDDQ NC VSS G VSS DQ6a VDDQ G NC DQ2b SBWb C VSS NC DQ5a H DQ3b NC VSS C VSS DQ4a NC J VDDQ VDD VREF VDD VREF VDD VDDQ K NC DQ4b VSS K VSS NC DQ3a L DQ5b NC VSS K SBWa DQ2a NC M VDDQ DQ6b VSS SW VSS NC VDDQ N DQ7b NC VSS SA14 VSS DQ1a NC P NC DQ8b VSS SA11 VSS NC DQ0a R NC SA10 M1 VDD M2 SA15 NC T NC SA17 SA9 NC SA1 SA16 ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Pin Description Symbol Description Symbol Description Symbol Description SA Address Input (0-17) G Async. Output Enable V DDQ Output Power Supply DQ Data I/O (0-8), Bytes a,b ZZ Async. Sleep Mode VSS Ground K,K Differential Input Clocks TCK JTAG Clock (LVTTL) VREF Input Reference Voltage C,C Differential Output Control Clocks TMS JTAG Mode Select (LVTTL) ZQ Output Impedance Control Resistor Input SW Write Enable, Global TDI JTAG Data In (LVTTL) M1,M2 Mode Select SBWx Write Enable, Bytes a,b TDO JTAG Data Out (LVTTL) NC No Connect SS Synchronous Select VDD +3.3V Power Supply 256Kx18, Sync LW, HSTL, rev 4.6 2 / 27 August 20, 1998 SONY® CXK77B1840GB BLOCK DIAGRAM 18 Input Reg. SA 0-17 2:1 Mux Dout ^ Kint Add. Write Store Reg. 256K x 18 Din Output 2:1 Mux latch DQ Write pulse Reg. Read Comp. Reg. SS ^ Kint SW Reg. ^ Kint Self Time Write Logic 4 SBW a-d Reg. ^ Kint Input Clock Kint 2 K/K C/C Output Clock 2 M1 M2 Mode Control G 256Kx18, Sync LW, HSTL, rev 4.6 3 / 27 August 20, 1998 SONY® CXK77B1840GB •Truth Tables Register - Register Mode ZZ SS (tn) SW (tn) SBWx (tn) G DQ0-17 (tn) DQ0-17 (tn+1) VDD Current H X X X X Sleep Mode. Power Down Hi - Z Hi - Z ISB L H X X X Deselect X Hi - Z IDD L L H X H Read Hi - Z Hi - Z IDD L L H X L Read X Q(tn) IDD L L L L X Write All Bytes (Bits 0-17) X D(tn) IDD L L L X X Write Bytes With SBWx=L X D(tn) IDD L L L H X Abort Write X Hi - Z IDD DQ0-17 (tn) DQ0-17 (tn+1) VDD Current Mode Register - Latch and Register - Flow Thru Mode ZZ SS (tn) SW (tn) SBWx (tn) G H X X X X Sleep Mode. Power Down Hi - Z Hi - Z ISB L H X X X Deselect Hi - Z X IDD L L H X H Read Hi - Z Hi - Z IDD L L H X L Read Q(tn) X IDD L L L L X Write All Bytes (Bits 0-17) Hi - Z D(tn) IDD L L L X X Write Bytes With SBWx=L Hi - Z D(tn) IDD L L L H X Abort Write Hi - Z X IDD DQ0-17 (tn) DQ0-17 (tn+1) VDD Current Mode Dual Clock Mode ZZ SS (tn) SW (tn) SBWx (tn) G H X X X X Sleep Mode. Power Down Hi - Z Hi - Z ISB L H X X X Deselect Hi - Z X IDD L L H X H Read Hi - Z Hi - Z IDD L L H X L Read Q(tn) X IDD L L L L X Write All Bytes (Bits 0-17) Hi - Z D(tn) IDD L L L X X Write Bytes With SBWx=L Hi - Z D(tn) IDD L L L H X Abort Write Hi - Z Hi - Z IDD 256Kx18, Sync LW, HSTL, rev 4.6 Mode 4 / 27 August 20, 1998 SONY® CXK77B1840GB •Mode Select This device supports four different JEDEC standard read protocols via mode pins M1 and M2. The mode pins must be set during power-up and cannot change during SRAM operation. Mode Select Truth Table. M1 M2 Register-Register L H Register-Flow Thru L L Register-Latch H L Dual Clock H H •Power-Up Sequence Power supplies must power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ must never exceed VDD. •Absolute Maximum Ratings(1) Item Symbol Rating Unit Supply Voltage VDD -0.5 to +4.6 V Output Supply Voltage VDDQ -0.5 to +4.6 V VIN -0.5 to VDD+0.5 (4.6V max.) V VOUT -0.5 to VDDQ+0.5 (4.6V max.) V Operating Temperature TA 0 to 70 °C Junction Temperature TJ 0 to 110 °C Storage Temperature Tstg -55 to 150 °C Input Voltage Output Voltage (1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 256Kx18, Sync LW, HSTL, rev 4.6 5 / 27 August 20, 1998 SONY® CXK77B1840GB •DC Recommended Operating Conditions. Item (VSS = 0V, TA = 0 to 70oC) Symbol Min Typ Max Unit VDD 3.13 3.3 3.47 V Output Supply Voltage VDDQ 1.4 --- 1.6(3) V Input Reference Voltage VREF 0.5 --- 1.0 V Input High Voltage VIH VREF + 0.2 --- VDDQ + 0.3(1) V Input Low Voltage VIL -0.3(2) --- VREF - 0.2 V Input High Voltage - Test Mode VTIH 2.0 --- VDDQ+0.3 V Input Low Voltage - Test Mode VTIL -0.3 --- 0.8 V Clock Input Signal Voltage VIN -0.3 --- VDDQ+0.3 V Clock Input Differential Voltage VDIF 0.4 --- VDDQ+0.6 V Clock Input Common Mode Voltage VCM 0.5 0.75 1.0 V Clock Input Cross Point Voltage VX 0.5 0.75 1.0 V Output Impedance Control Resistor RQ 175 250 350 Ω Supply Voltage (1) (2) (3) VIH (Max) AC = V DD+1.5 V for pulse width less than 2.0 ns. VIL (Min) AC = -1.5 V for pulse width less than 2.0 ns. Extended VDDQ support up to 2.0V is available - please contact marketing. •I/O Capacitance Item (TA = 25oC, f = 1 MHz) Symbol Test conditions Min Max Unit CIN VIN = 0V --- 6 pF Clock Input Capacitance CCLK VIN = 0V --- 6 pF Output Capacitance COUT VOUT = 0V --- 7 pF Input Capacitance Note: These parameters are sampled and are not 100% tested. •Programmable Impedance Output Drivers This device has programmable impedance output drivers. The output impedance is controlled by an external resistor, RQ, connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor. For output impedance matching within a ±7.5% tolerance, RQ must be in the range of 175Ω to 350Ω. For maximum output drive, the ZQ pin can be connected directly to VSS. For minimum output drive, the ZQ pin can be left open or connected to VDDQ. The output impedance is updated whenever the drivers are in a Hi-Z state. At power up, 8192 clock cycles followed by a write or deselect operation are required to ensure that the output impedance has reached its desired value. After power up, periodic updates of the output impedance, via a write or deselect operation, are also required. 256Kx18, Sync LW, HSTL, rev 4.6 6 / 27 August 20, 1998 SONY® CXK77B1840GB (VDD = 3.3V ± 5%, VSS = 0V, TA = 0 to 70oC) •DC Electrical Characteristics Item Symbol Test Conditions Min Typ Max Unit Input Leakage Current ILI VIN = VSS to VDD -1 --- 1 uA Output Leakage Current ILO VOUT = VSS to VDD G = VIH -10 --- 10 uA Power Supply Operating Current IDD4 Cycle = 6.0ns Duty = 100% IOUT = 0 mA --- 610 --- mA Power Supply Operating Current IDD4 Cycle = 5.0ns Duty = 100% IOUT = 0 mA --- 650 --- mA Power Supply Operating Current IDD4 Cycle = 4.5ns Duty = 100% IOUT = 0 mA --- 670 --- mA Power Supply Operating Current IDD4 Cycle = 4.0ns Duty = 100% IOUT = 0 mA --- 695 --- mA Power Supply Standby Current ISB ΖΖ ≥ VIH --- 60 --- mA Output High Voltage VOH IOH = -6.0 mA RQ=250Ω VDDQ-0.4 --- --- V Output Low Voltage VOL IOL = 6.0 mA RQ = 250Ω --- --- 0.4 V (RQ/5)* 0.925 RQ/5 (RQ/5)* 1.075 Ω Output Driver Impedance ROUT1,2,3 VOH = VDDQ/2 VOL = VDDQ/2 1. RQ needs to be in the range of 175Ω to 350Ω for proper control of the value of ROUT. 1.1 ROUT ≤ 38Ω (1.075 * 175Ω/5) when RQ ≤ 175Ω 1.2 ROUT ≥ 64Ω (0.925 * 350Ω/5) when RQ ≥ 350Ω 2. For maximum output drive, ZQ pin can be tied directly to VSS. The output impedance is as described in note 1.1. 3. For minimum output drive, ZQ pin can be no connect or tied to VDDQ. The output impedance is as described in note 1.2. 4. Typical IDD values measured at VDD = 3.3V and TA = 25oC, with a 75% read / 25% write operation distribution. 256Kx18, Sync LW, HSTL, rev 4.6 7 / 27 August 20, 1998 SONY® CXK77B1840GB •AC Electrical Characteristics (Register-Register Mode) -4A Item -4 -45A -45 Symbol Unit Min Max Min Max Min Max Min Max Cycle Time tKHKH 4.0 --- 4.0 --- 4.0 --- 5.0 --- ns Clock High Pulse Width tKHKL 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns Clock Low Pulse Width tKLKH 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns Address Setup Time tAVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Address Hold Time tKHAX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Write Enables Setup Time tWVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Write Enables Hold Time tKHWX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Synchronous Select Setup Time tSVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Synchronous Select Hold Time tKHSX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Data Input Setup Time tDVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Data Input Hold Time tKHDX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Clock High to Output Valid tKHQV --- 2.3 --- 2.3 --- 2.3 --- 2.5 ns Clock High to Output Hold tKHQX*2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns Clock High to Output Low-Z tKHQX1*2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns Clock High to Output High-Z tKHQZ*2 --- 2.3 --- 2.3 --- 2.3 --- 2.5 ns Output Enable Low to Output Valid tGLQV --- 2.3 --- 2.3 --- 2.3 --- 2.5 ns Output Enable Low to Output Low-Z tGLQX*2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Output Enable High to Output High-Z tGHQZ*2 --- 2.3 --- 2.3 --- 2.3 --- 2.3 ns Sleep Mode Enable Time tZZE*2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns Sleep Mode Recovery Time tZZR*2 20.0 --- 20.0 --- 20.0 --- 20.0 ns 1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested. 256Kx18, Sync LW, HSTL, rev 4.6 8 / 27 August 20, 1998 SONY® CXK77B1840GB •AC Electrical Characteristics (Register-Latch & Register-Flow Thru Modes) -4A Item -4 -45A -45 Symbol Unit Min Max Min Max Min Max Min Max Cycle Time tKHKH 4.8 --- 5.3 --- 5.3 --- 6.5 --- ns Clock High Pulse Width tKHKL 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns Clock Low Pulse Width tKLKH 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns Address Setup Time tAVKH 0.4*3 --- 0.5 --- 0.5 --- 0.5 --- ns Address Hold Time tKHAX 0.8*3 --- 1.0 --- 1.0 --- 1.0 --- ns Write Enables Setup Time tWVKH 0.4*3 --- 0.5 --- 0.5 --- 0.5 --- ns Write Enables Hold Time tKHWX 0.8*3 --- 1.0 --- 1.0 --- 1.0 --- ns Synchronous Select Setup Time tSVKH 0.4*3 --- 0.5 --- 0.5 --- 0.5 --- ns Synchronous Select Hold Time tKHSX 0.8*3 --- 1.0 --- 1.0 --- 1.0 --- ns Data Input Setup Time tDVKH 0.4*3 --- 0.5 --- 0.5 --- 0.5 --- ns Data Input Hold Time tKHDX 0.8*3 --- 1.0 --- 1.0 --- 1.0 --- ns Clock High to Output Valid tKHQV --- 4.8 --- 5.3 --- 5.3 --- 6.5 ns Clock High to Output Hold (R-FT mode only) tKHQX*2 2.0 --- 2.0 --- 2.0 --- 2.0 --- ns Clock High to Output Low-Z (R-FT mode only) tKHQX1*2 2.5 --- 2.5 --- 2.5 --- 3.0 --- ns Clock Low to Output Valid (R-L mode only) tKLQV --- 2.2 --- 2.3 --- 2.5 --- 2.5 ns Clock Low to Output Hold (R-L mode only) tKLQX*2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns Clock Low to Output Low-Z (R-L mode only) tKLQX1*2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns Clock High to Output High-Z tKHQZ*2 --- 2.2 --- 2.3 --- 2.5 --- 2.5 ns Output Enable Low to Output Valid tGLQV --- 2.2 --- 2.3 --- 2.5 --- 2.5 ns Output Enable Low to Output Low-Z tGLQX*2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Output Enable High to Output High-Z tGHQZ*2 --- 2.2 --- 2.3 --- 2.3 --- 2.3 ns Sleep Mode Enable Time tZZE*2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns Sleep Mode Recovery Time tZZR*2 20.0 --- 20.0 --- 20.0 --- 20.0 --- ns 1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested. 3. For -4A, these parameters are measured from valid VIH/VIL levels to the clock mid-point. 4. R-FT mode operation is verified functionally, but associated timing parameters are guaranteed by design only and are not 100% tested. 256Kx18, Sync LW, HSTL, rev 4.6 9 / 27 August 20, 1998 SONY® CXK77B1840GB •AC Electrical Characteristics (Dual Clock Mode) -4A Item -4 -45A -45 Symbol Unit Min Max Min Max Min Max Min Max K Clock Cycle Time tKHKH 4.0 --- 4.0 --- 4.5 --- 4.5 --- ns K Clock High Pulse Width tKHKL 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns K Clock Low Pulse Width tKLKH 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns C Clock Cycle Time tCHCH 4.0 --- 4.0 --- 4.5 --- 4.5 --- ns C Clock High Pulse Width tCHCL 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns C Clock Low Pulse Width tCLCH 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns K to C Clock Delay tKHCH 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns C to K Clock Delay tCHKH 0.8 --- 0.8 --- 0.8 --- 0.8 --- ns Address Setup Time tAVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Address Hold Time tKHAX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Write Enables Setup Time tWVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Write Enables Hold Time tKHWX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Synchronous Select Setup Time tSVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Synchronous Select Hold Time tKHSX 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns Data Input Setup Time tDVKH 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Data Input Hold Time tKHDX 0.8 --- 0.8 --- 1.0 --- 1.0 --- ns K Clock High to Output Valid tKHQV --- 5.2 --- 5.2 --- 6.0 --- 6.5 ns C Clock High to Output Valid tCHQV --- 2.3 --- 2.3 --- 2.5 --- 2.5 ns C Clock High to Output Hold tCHQX*2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns C Clock High to Output Low-Z tCHQX1*2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns C Clock High to Output High-Z tCHQZ*2 --- 2.3 --- 2.3 --- 2.5 --- 2.5 ns Output Enable Low to Output Valid tGLQV --- 2.1 --- 2.1 --- 2.5 --- 2.5 ns Output Enable Low to Output Low-Z tGLQX*2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns Output Enable High to Output High-Z tGHQZ*2 --- 2.0 --- 2.0 --- 2.3 --- 2.3 ns Sleep Mode Enable Time tZZE*2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns Sleep Mode Recovery Time tZZR*2 20.0 --- 20.0 --- 20.0 --- 20.0 --- ns 1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested. 3. Currently, DC mode operation is not verified functionally, and no timing parameters are guaranteed. Contact Sony Memory Marketing for availability. 256Kx18, Sync LW, HSTL, rev 4.6 10 / 27 August 20, 1998 SONY® CXK77B1840GB •AC Test Conditions (VDDQ = 1.5V) (VDD = 3.3V ± 5%, TA = 0 to 70°C) Item Conditions Input Reference Voltage VREF = 0.75V Input High Level VIH = 1.25V Input Low Level VIL = 0.25V Input Rise & Fall Time Clock Notes 1V/ns Input Reference Level K/K cross; C/C cross Input High Voltage 1.25V Input Low Voltage 0.25V Input Rise & Fall Time 1V/ns Output Supply Voltage VDDQ = 1.5V Output Reference Level 0.75V Output Load Conditions Fig.1 RQ = 250Ω Fig. 1: AC Test Output Load (VDDQ = 1.5V) 0.75 V 50 Ω 16.7 Ω 50 Ω 5 pF DQ 16.7 Ω 0.75 V 50 Ω 16.7 Ω 50 Ω 5 pF 256Kx18, Sync LW, HSTL, rev 4.6 11 / 27 August 20, 1998 SONY® CXK77B1840GB •AC Test Conditions (VDDQ = 1.9V) .... for extended HSTL (for R-L mode only) (VDD = 3.3V ± 5%, TA = 0 to 70°C) (VDDQ = 1.9V ± 0.1V, TA = 0 to 70°C) Item Conditions Input Reference Voltage VREF = 0.75V Input High Level (Address / Control) VIHCA = 1.25V Input Low Level (Address / Control) VILCA = 0.25V Input High Level (Data) VIHD = 1.25V Input Low Level (Data) VILD = 0.25V Input Rise & Fall Time 1V/ns Clock Input Reference Level Notes K/K cross PECL Input High Voltage 1.45V PECL Input Low Voltage 0.75V Input Rise & Fall Time 1V/ns Output Supply Voltage VDDQ = 1.9V Output Reference Level 0.95V Output Load Conditions Fig.2 RQ = 250Ω Fig. 2: AC Test Output Load (VDDQ = 1.9V) 0.95 V 50 Ω 16.7 Ω 50 Ω 5 pF DQ 16.7 Ω 0.95 V 50 Ω 16.7 Ω 50 Ω 5 pF 256Kx18, Sync LW, HSTL, rev 4.6 12 / 27 August 20, 1998 SONY® CXK77B1840GB Register - Register Mode Timing Diagram of Read and Deselect Operations K K tKHKH SA tKHKL n tKLKH n+2 n+3 tAVKH tKHAX SW tWVKH tKHWX SS tSVKH tKHSX tGLQV tGLQX G tKHQV tGHQZ tKHQZ tKHQX DQ Qn-2 tKHQX1 Qn Qn-1 Timing Diagram of Write Operations K K SA n n+1 n+2 n+3 Dn Dn+1 Dn+2 SS SW/SBWx G tDVKH tKHDX DQ Dn-1 256Kx18, Sync LW, HSTL, rev 4.6 13 / 27 August 20, 1998 SONY® CXK77B1840GB Register - Register Mode Timing Diagram I of Read-Write-Read Operations (SS Controlled) K K SA n n+2 n+3 n+4 n+5 SS SW/SBWx tKHQZ G = VIL DQ Qn-1 Read n Qn Deselect Dn+2 Write n+2 Qn+3 Read n+3 Read n+4 Timing Diagram II of Read-Write-Read Operations (G Controlled) K K SA n n+2 n+3 n+4 n+5 SS = VIL SW/SBWx G tGHQZ DQ Qn-1 Read n 256Kx18, Sync LW, HSTL, rev 4.6 Qn Dummy Read Dn+2 Write n+2 14 / 27 Read n+3 Qn+3 Read n+4 August 20, 1998 SONY® CXK77B1840GB Register - Latch Mode Timing Diagram of Read and Deselect Operations K K tKHKH SA tKHKL n tKLKH n+1 n+3 tAVKH tKHAX SW tWVKH tKHWX SS tSVKH tKHSX tGLQV tGLQX tKHQV G tKLQV tKLQV tKLQX tGHQZ tKHQZ tKLQX DQ Qn-1 Qn Qn+1 Timing Diagram of Write Operations K K SA n n+1 n+2 n+3 Dn Dn+1 Dn+2 SS SW/SBWx G tDVKH tKHDX DQ Dn-1 256Kx18, Sync LW, HSTL, rev 4.6 15 / 27 August 20, 1998 SONY® CXK77B1840GB Register - Latch Mode Timing Diagram of Read-Write-Read Operations K K SA n n+1 n+2 n+4 n+5 SS SW/SBWx tKHQZ G = VIL DQ Qn Read n 256Kx18, Sync LW, HSTL, rev 4.6 tKHQZ Dn+1 Write n+1 Read n+2 16 / 27 Qn+2 Deselect Qn+4 Read n+4 August 20, 1998 SONY® CXK77B1840GB Register - Flow Thru Mode Timing Diagram of Read and Deselect Operations K K tKHKH SA n tKHKL tKLKH n+1 n+3 tAVKH tKHAX SW tWVKH tKHWX SS tSVKH tKHSX tGLQV tGLQX G tKHQV tGHQZ tKHQZ tKHQX DQ Qn-1 tKHQX Qn Qn+1 Timing Diagram of Write Operations K K SA n n+1 n+2 n+3 Dn Dn+1 Dn+2 SS SW/SBWx G tDVKH tKHDX DQ Dn-1 256Kx18, Sync LW, HSTL, rev 4.6 17 / 27 August 20, 1998 SONY® CXK77B1840GB Register - Flow Thru Mode Timing Diagram of Read-Write-Read Operations K K SA n n+1 n+2 n+4 n+5 SS SW/SBWx tKHQZ G = VIL DQ Qn Read n 256Kx18, Sync LW, HSTL, rev 4.6 tKHQZ Dn+1 Write n+1 Read n+2 18 / 27 Qn+2 Deselect Qn+4 Read n+4 August 20, 1998 SONY® CXK77B1840GB Dual Clock Mode Timing Diagram of Read and Deselect Operations K K tKHKH SA tKHKL n tKLKH n+1 n+3 tAVKH tKHAX SW tWVKH tKHWX SS tSVKH tKHSX G tGLQV tKHQV tCHQV tGLQX tCHQV tCHQX1 tGHQZ tCHQZ tCHQX DQ Qn-1 tCHKH Qn Qn+1 tKHCH C C tCHCH 256Kx18, Sync LW, HSTL, rev 4.6 tCHCL tCLCH 19 / 27 August 20, 1998 SONY® CXK77B1840GB Dual Clock Mode Timing Diagram of Write Operations K K SA n n+1 n+2 n+3 Dn Dn+1 Dn+2 SS SW/SBWx G tDVKH tKHDX DQ Dn-1 Timing Diagram I of Read-Write-Read Operations (SS Controlled) K K SA n n+2 n+3 n+4 n+5 SS SW/SBWx tCHQZ G = VIL DQ Qn Dn+2 Qn+3 Qn+4 C C Read n 256Kx18, Sync LW, HSTL, rev 4.6 Deselect Write n+2 20 / 27 Read n+3 Read n+4 August 20, 1998 SONY® CXK77B1840GB Dual Clock Mode Timing Diagram II of Read-Write-Read Operations (G Controlled) K K SA n n+2 n+3 n+4 n+5 SS = VIL SW/SBWx G ***Note*** (1) tGHQZ DQ Qn Dn+2 Qn+3 Qn+4 C C Read n Dummy Read Write n+2 Read n+3 Read n+4 Note 1: In order to prevent glitches on the data bus during write-read operations, when G is driven active (low) following the rising edge of K, the data bus will remain tri-stated until valid data from the most recent read operation is available. Specifically, the data bus will remain tri-stated for the maximum of the following three times: 1.TKHQV 2.TKHCH + TCHQV 3.(K high to G low) + TGLQV 256Kx18, Sync LW, HSTL, rev 4.6 21 / 27 August 20, 1998 SONY® CXK77B1840GB Test Mode Description Functional Description The CXK77B1840 provides a JTAG boundary scan interface using a limited set of IEEE std. 1149.1 functions. The test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, the CXK77B1840 contains a TAP controller, Instruction register, Boundary scan register and Bypass register. JTAG Inputs/Outputs are LVTTL compatible only. Test Access Port (TAP) 4 pins as defined in the Pin Description table are used to perform JTAG functions. The TDI input pin is used to scan test data serially into one of three registers (Instruction register, Boundary Scan register and Bypass register). TDO is the output pin used to scan test data serially out. The TDI pin sends the data into LSB of the selected register and the MSB of the selected register feeds the data to TDO. The TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI and TMS are registered on the rising edge of TCK clock. The output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift-DR state. TCK, TMS, TDI must be tied low when JTAG is not used. TAP Controller 16 state controller is implemented as specified in IEEE std. 1149.1. The controller enters reset state in one of two ways: 1. Power up. 2. Apply a logic 1 on TMS input pin on 5 consecutive TCK rising edges. Instruction Register (3 bits) The JTAG Instruction register consists of a shift register stage and parallel output latch. The register is 3 bits wide and is encoded as follow: Octal MSB..........LSB Instruction 0 0 0 0 Bypass 1 0 0 1 IDCODE. Read device ID 2 0 1 0 Sample-Z. Sample Inputs and tri-state DQs 3 0 1 1 Bypass 4 1 0 0 Sample. Sample Inputs. 5 1 0 1 Private. Manufacturer use only. 6 1 1 0 Bypass 7 1 1 1 Bypass 256Kx18, Sync LW, HSTL, rev 4.6 22 / 27 August 20, 1998 SONY® CXK77B1840GB Bypass Register (1 bit) The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serial path between TDI and TDO. ID Registers (32 bits) The ID Register is 32 bits wide and is encoded as follows: ID[0} 1 Sony ID ID[11:1] 0000 1110 001 Part Number ID[27:12] 0000 0000 0001 1000 Revision Number ID[31:28] xxxx Boundary Scan Register (51 bits) The Boundary Scan Registers are 51 bits wide and are listed as follows: DQ 18 SA 18 SW, SBWx 3 SS, G 2 K, K, C, C 4 ZZ 1 M1, M2 2 ZQ 1 Place Holder 2 K/K, C/C inputs are sampled through one differential stage and internally inverted to generate internal K/K, C/C signals for scan registers. Place Holder are required for some NC pins to maintain 51 bits Scan Register for different types of the same family SRAM and for density upgrades. All Place Holder Registers are connected to VSS internally regardless of pin connection externally. 256Kx18, Sync LW, HSTL, rev 4.6 23 / 27 August 20, 1998 SONY® CXK77B1840GB Scan Order (Order by exit sequence) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 256Kx18, Sync LW, HSTL, rev 4.6 3B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R SA VSS SA SA SA SA DQb DQb DQb DQb SBWb ZQ SS C C SW DQb DQb DQb DQb DQb SA SA SA SA M1 SA VSS SA SA SA SA DQa DQa DQa DQa DQa G K K SBWa DQa DQa DQa DQa ZZ SA SA SA SA M2 24 / 27 5B 5A 5C 6C 6A 6D 7E 6F 7G 6H 4F 4K 4L 5L 7K 6L 6N 7P 7T 5T 6R 4P 6T 5R 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 August 20, 1998 SONY® CXK77B1840GB Ordering Information. Part Number Speed Register - Register Register - Latch/ Register - Flow Thru **Dual Clock** CXK77B1840GB-4A 4.0ns Cycle / 2.3ns Access 4.8ns Cycle / 4.8ns Access 4.0ns Cycle / 5.2ns Access CXK77B1840GB-4 4.0ns Cycle / 2.3ns Access 5.3ns Cycle / 5.3ns Access 4.0ns Cycle / 5.2ns Access CXK77B1840GB-45A 4.0ns Cycle / 2.3ns Access 5.3ns Cycle / 5.3ns Access 4.5ns Cycle / 6.0ns Access CXK77B1840GB-45 5.0ns Cycle / 2.5ns Access 6.5ns Cycle / 6.5ns Access 4.5ns Cycle / 6.5ns Access Note: Contact Sony Memory Marketing for availability of Dual Clock mode functionality. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 256Kx18, Sync LW, HSTL, rev 4.6 25 / 27 August 20, 1998 SONY® CXK77B1840GB Revision History Rev. # Rev. date Changes / Modifications to Data-Sheet rev 4.0 8/22/97 Initial version, based on TS-2 evaluation rev 4.2 11/21/97 Modified AC Electrical Characteristics: R-R Mode: -4.5+ TKHKH -4.5 TGHQZ -4.5 TGHQZ R-L, R-FT Modes: -4 TKHKH -4.5+ TKHQV TGHQZ -4.5 TGHQZ -5 TKHKH DC Mode: -4 TKHQV TKHDX TGLQV TGHQZ -4.5+ TKHQV TGHQZ -4.5 TGHQZ Renamed “-4” bin to “-40” bin in all modes. Renamed “-4.5+” bin to “-45H” bin in all modes. Renamed “-4.5” bin to “-45” bin in all modes. Renamed “-5” bin to “-50” bin in all modes. 5.0ns to 4.5ns 2.5ns to 2.3ns 2.5ns to 2.3ns 5.5ns to 5.0ns 6.5ns to 5.5ns 2.5ns to 2.3ns 2.5ns to 2.3ns 5.5ns to 6.0ns 5.5ns to 5.3ns 1.0ns to 0.8ns 2.3ns to 2.1ns 2.3ns to 2.0ns 6.2ns to 6.0ns 2.5ns to 2.3ns 2.5ns to 2.3ns Modified DC Recommended Operating Conditions (page-6) VREF + 0.1 to VREF + 0.2 VIH min VIL max VREF - 0.1 to VREF - 0.2 VDIF min 0.2V to 0.4V Added extended HSTL AC Test Conditions (page-12) Provided IDD & ISB typical values (page-7) rev 4.3 01/15/98 Modified AC Electrical Characteristics: Added “-40A” bin to all modes. Deleted “-40” bin from all modes. Deleted “-50” bin from all modes. Renamed “-45H” bin to “-45A” bin in all modes. Modified extended HSTL AC Test Conditions (page-12) 256Kx18, Sync LW, HSTL, rev 4.6 26 / 27 August 20, 1998 SONY® Rev. # rev 4.4 CXK77B1840GB Rev. date 04/14/98 Changes / Modifications to Data-Sheet Modified AC Electrical Characteristics Deleted “-45” bin from all modes. Renamed “-40A” bin to “-4A” bin in all modes. R-R Mode: -4A TKHKH 4.5ns to 4.0ns -45A TKHKH 4.5ns to 4.0ns TKHQV 2.5ns to 2.3ns TKHQZ 2.5ns to 2.3ns TGLQV 2.5ns to 2.3ns R-L, R-FT Modes: Added “R-FT timing parameters guaranteed by design only” note for all bins. Removed TKHQZ1 from all bins. -4A TGHQZ 2.3ns to 2.2ns DC Mode: Added “DC operation not functionally verified” note for all bins. Removed TKHQX and TKHQX1 from all bins. -4A TKHQV 5.3ns to 5.2ns Modified DC Recommended Operating Conditions (page-6) RQ min 200Ω to 175Ω Modified DC Electrical Characteristics (page-7) ROUT min (RQ/5)*0.9Ω to (RQ/5)*0.925Ω (RQ/5)*1.1Ω to (RQ/5)*1.075Ω ROUT max Updated all timing diagrams (page-13 through page-21). Added “Contact Sony Memory Marketing for DC model availability” note (page-1 and page-25). Removed “Preliminary” from the data sheet rev 4.5 rev 4.6 08/12/98 08/20/98 256Kx18, Sync LW, HSTL, rev 4.6 Modified AC Electrical Characteristics R-L, R-FT Modes: -4A TKHKH TKHQV -45A TKHKH TKHQV 5.0ns to 4.8ns 5.0ns to 4.8ns 5.5ns to 5.3ns 5.5ns to 5.3ns Modified AC Electrical Characteristics Added “-4” bin to all modes. Added “-45” bin to all modes. 27 / 27 August 20, 1998