FastEdge™ Series CY2PP3115 PRELIMINARY 1:15 Differential Fanout Buffer Features Description • Fifteen ECL/PECL differential outputs grouped in four banks • Two ECL/PECLdifferential inputs • Hot-swappable/-insertable • 50-ps output-to-output skew • < 200-ps device-to-device skew • Less than 2-pS intrinsic jitter • < 500-ps propagation delay (typical) • Operation up to 1.5 GHz • PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V • ECL mode supply range: VEE = –2.375V to –3.465V with VCC = 0V • Industrial temperature range: –40°C to 85°C • 52-pin 1.4mm TQFP package • Temperature compensation like 100K ECL The CY2PP3115 is a low-skew, low propagation delay 1-to-15 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths which are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2PP3115 may function not only as a differential clock buffer but also as a signal level translator and fanout on ECL/PECL single-ended signal to 15 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-µF capacitor. Since the CY2PP3115 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP3115 delivers consistent, guaranteed performance over differing platforms. Block Diagram Pin Configuration FSELA CLK0 CLK0# VCC QA0 QA0# QA1 QA1# VCC QB0 QB0# QB1 QB1# QB2 QB2# VCC 1 QAO QA1 /1 52 51 50 49 48 47 46 45 44 43 42 41 40 QBO 0 0 VCC 1 39 VCC MR 2 38 QC0 FSELA 3 37 QC0# FSELB 4 36 QC1 CLK0 5 35 QC1# CLK0# 6 34 QC2 CLK_SEL 7 33 QC2# CLK1 8 32 QC3 CLK1# 9 31 QC3# VBB 10 30 VCC FSELC 11 29 NC FSELD 12 28 NC VEE 13 27 VCC QB1 VCC VEE 1 1 /2 CLK1 CLK1# QB2 QC0 VEE CLK_SEL 0 QC1 VEE 1 FSELB FSELC QC2 QC3 QD0 VEE VEE 0 QD2 1 QD3 VCC QD5# QD5 QD4# QD4 QD3# QD3 QD2# QD2 QD1# QD1 QD0# QD0 QD1 MR CY2PP3115 14 15 16 17 18 19 20 21 22 23 24 25 26 0 VEE VCC QD4 FSELD VEE QD5 VBB Cypress Semiconductor Corporation Document #: 38-07502 Rev.*A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 18, 2003 FastEdge™ Series CY2PP3115 PRELIMINARY Pin Description Name[2,3] Pin No. 1,14,27, 30, 39, 40, 47, VCC 52 I/O[1] Type +PWR POWER Description Power Supply, positive connection 2 MR I,PD ECL/PECL Reset 3,4,11,12 FSEL(A,B,C,D) I,PD ECL/PECL Output Divider Selects 5,8 CLK(0:1) I,PD ECL/PECL Differential Clock Inputs – TRUE 6,9 CLK(0:1)# I,PC ECL/PECL Differential Clock Inputs – COMPLIMENT 10 VBB O Bias DC Bias Source 13 VEE –PWR POWER Power Supply, Negative Connection 28,29 NC 7 CLK_SEL I,PD ECL/PECL No Connect. Pad Only Clock Input Select 26,24,22,20,18,16 QD(0:5) O,OE ECL/PECL Bank D True Output 25,23,21,19,17,15 QD(0:5)# O,OE ECL/PECL Bank D Compliment Output 38,36,34,32 QC(0:3) O,OE ECL/PECL Bank C True Output 37,35,33,31 QC(0:3)# O,OE ECL/PECL Bank C Compliment Output 46,44,42 QB(0:2) O,OE ECL/PECL Bank B True Output 45,43,41 QB(0:2)# O,OE ECL/PECL Bank B Compliment Output 51,49 QA(0:1) O,OE ECL/PECL Bank A True Output 50,48 QA(0:1)# O,OE ECL/PECL Bank A Compliment Output Table 1. Function Table Control Pin 0 1 FSELA (Asynchronous) ÷1 ÷2 FSELB (Asynchronous) ÷1 ÷2 FSELC (Asynchronous) ÷1 ÷2 FSELD (Asynchronous) ÷1 ÷2 CLK_SEL (Asynchronous) CLK0 CLK1 MR (Asynchronous) Active Reset (QX = L and QX# = H) Governing Agencies The following agencies provide specifications that apply to the CY2PP3115. The agency name and relevant specification is listed below. Agency Name Specification JEDEC JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–A (skew,jitter) IEEE 1596.3 (Jitter specs) UL 94 (Flammability Grading) Mil–Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-down, PU for Pull-up, PC for Pull Center, O for output, OE for open emitter and PWR for Power. 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V. Document #: 38-07502 Rev.*A Page 2 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY Absolute Maximum Conditions . Parameter Description VCC Supply Voltage VCC Operating Voltage VBB Output Reference Voltage IBB VTT VIN VOUT LUI TS TA ØJc ØJa ESDh MSL GATES UL–FLM Output Reference Current Output Termination Voltage Input Voltage Output Voltage Latch-up Immunity Temperature, Storage Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Flammability Rating Condition Non-Functional Functional Relative to VCC Relative to VBB Relative to VCC Relative to VCC Relative to VCC Functional Non-functional Functional Functional Functional Min. –0.3 2.5 – 5% VCC–1.620 Max. 4.6 3.3 + 5% Vcc–1.220 Unit VDC VDC VDC –0.3 –0.3 200 VCC–2 VCC+0.3 VCC+0.3 uA VDC VDC VDC mA °C °C °C/W °C/W 300 –65 –40 40 40 +150 +85 60 100 2000 3 50 V–0 Assembled Die @ 1/8 in. V N.A. Ea. N.A. PECL DC Electrical Specifications Parameter Description Condition Control (FSEL(A,B,C),CLK_SEL, MR and FSELD) (PECL Single-ended) VCC2.5V 2.5 Operating Voltage 2.5V ± 5%, VEE = 0.0V VCC3.3V VIL VIH IIN 3.3 Operating Voltage Input Voltage, Low Input Voltage, High Input Current[4] 3.3V ± 5%, VEE = 0.0V Min. Max. Unit 2.625 3.465 VCC–1.625 VCC–0.880 V V V V I150I uA 1.3 VCC I150I V V uA VCC–0.7 VCC–1.5 VCC–1.3 V VCC–1.945 VCC –1.945 – 200 mA VCC–1.620 – – VCC–1.220 2.0 1.0 V pF nH 2.375 3.135 VCC–1.945 VCC–1.165 VIL = VILmin. or VIH = VIHmax at VCC = 3.6V Clock input pair CLK0, CLK0#,CLK1,CLK1# (PECL Differential Signals) Differential input voltage[5] Differential operation VPP [6] VCMR Differential cross point voltage Differential operation IIN Input Current[4] VIL = VILmin. or VIH = VIHmax at VCC = 3.6V 0.1 1.2 PECL Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#)(PECL Differential Signals) VOH Output High Voltage IOH = –30 mA[7] VCC–1.2 VOL Output Low Voltage VCC = 3.3V ± 5%, VCC = 2.5V ± 5% Supply Current and VBB Maximum Quiescent Supply Current IEE without output termination current[8] [9] VBB Output reference voltage CIN LIN Input pin capacitance Pin Inductance IOL = –5 ma[7] VEE pin IBB = 200 uA[12] V Notes: 4. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. Equivalent to a termination of 50 Ω to VTT. 8. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE orICC = (number of differential output pairs used) x (VOH–VTT)/Rload + (VOL–-VTT)/Rload +IEE. 9. VBB is limited to VCC of 3.3V only. See note 17. Document #: 38-07502 Rev.*A Page 3 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY ECL DC Electrical Specifications Parameter Description Condition Min. Max. Unit –2.625 V Control (FSEL(A,B,C),CLK_SEL, MR and FSELD) (ECL single-ended) VEE2.5 –2.5 Negative Power Supply –2.5V ± 5%, VEE = 0.0V –2.375 VEE3.3 –3.3 Negative Power Supply –3.3V ± 5%, VEE = 0.0V –33.135 –3.465 V VIL Input Voltage, Low –1.945 –1.625 V VIH Input Voltage, High –1.165 –0.880 V IIN Input Current[10] I150I uA 1.3 V VIN = VIL or VIN = VIH Clock input pair CLK0, CLK0#,CLK1,CLK1# (ECL differential signals) VPP Differential input voltage[11] [12] Differential operation 0.1 VEE+1.2 VCMR Differential cross point voltage Differential operation IIN Input Current[10] VIN = VIL or VIN = VIH –0.5 V I150I uA ECL Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#)(ECL differential signals) VOH Output High Voltage IOH = –30 mA[13] VOL Output Low Voltage VEE = –3.3V ± 5%,VEE = –2.5V ± 5% IOL = –5 ma[13] –1.2 –0.7 V –1.945 –1.945 –1.5 –1.3 V – 180 mA –1.620 –1.220 V Supply current and VBB IEE Maximum Quiescent Supply Current without output termination current[14] VEE pin VBB Output reference voltage IBB = 200 uA AC Electrical Specifications Parameter Description Condition Min. Max. Unit Differential operation 0.1 1.3 V Differential operation VEE + 1.2 0 V 1500 MHz 1200 ps Clock input pair CLK0, CLK0#,CLK1,CLK1#(PECL or ECL differential signals) VPP VCMR Differential input voltage[16] Differential cross point voltage[17] Frequency[18] FCLK Input TPD Propagation Delay CLK0 or CLK1 to QA(0:1),QB(0:2),QC(0:3),QD(0:5) pair 50% duty cycle Standard load 660 MHz 50% duty cycle Standard load Differential Operation. See Table 2 600 ECL/PECL Clock Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#) (differential) Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz fo < 1.5 GHz V Vo(P-P) Differential output voltage (peak-to-peak) VMCR Common Voltage Range tsk(O) Output-to-output skew 660 MHz 50% duty cycle Standard load Differential Operation – 50 ps tsk(O) Output-to-output skew (different frequency) 660 MHz 50% duty cycle Standard load Differential Operation – 60 ps 0.45 0.4 0.375 0.3 VCC–1.425 ps Notes: 10. Input have internal pullup / pulldown or biasing resistors which affect the input current. 11. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 12. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 13. Equivalent to a termination of 50 Ω to VTT. 14. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH –VTT)/Rload + (VOL –VTT)/Rload +IEE. 15. AC characteristics apply for parallel output termination of 50 Ω to VTT. 16. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 17. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 18. The CY2PP3115 is fully operation up to 1.5 GHz. Document #: 38-07502 Rev.*A Page 4 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY AC Electrical Specifications Parameter Description Condition Min. Max. Unit tsk(PP) Output-to-output skew (part-to-part) 50% duty cycle Standard load Differential Operation – 200 ps TJIT(CC) Output cycle-to-cycle jitter (deterministic/Intrinsic) All outputs /1 500 MHz 50% duty cycle Standard load Differential Operation – 2 ps Output cycle-to-cycle jitter (deterministic/Intrinsic) All outputs /2 660 MHz 50% duty cycle Standard load Differential Operation – 2 ps Output cycle-to-cycle jitter (determin660 MHz 50% duty cycle Standard load Differistic/Intrinsic) ential Operation All outputs Bank(A and C)/1, Bank(B and D)/2 – 2 ps 660 MHz 50% duty cycle Standard load DifferOutput cycle-to-cycle jitter (determinential Operation istic/Intrinsic) All outputs Bank A/1, Bank(B,C and D)/2 – 2 ps tsk(P) Output pulse skew [19] 660 MHz 50% duty cycle Standard load Differential Operation – 75 ps TR,TF Output Rise / Fall time 660 MHz 50% duty cycle Differential 20% to 80% – 0.3 ns TTB Total Timing Budget 500 MHz 50% duty cycle Standard load – 250 ps Table 2. TPD–Propagation Delay 66-MHz 50% Duty Cycle CLK_SEL TPD FSELA FSELB FSELC FSELD 0 1 Unit 0 0.900 0.974 ns 1 0.979 0.982 ns 0 0.951 0.974 ns 1 0.962 0.966 ns 0 0.952 0.974 ns 1 1.019 1.021 ns 0 0.986 0.980 ns 1 1.018 1.022 ns Timing Definitions VCC VCC = 2.5V or 3.3V VCM R M ax = VCC VIH VPP VPP range 0.1V - 1.3V VCM R VIL VCM R M in = 1.2V VEE VEE = 0.0V Figure 1. PECL Waveform Definitions Note: 19. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07502 Rev.*A Page 5 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY VCC V C C = 0 .0 V VCM R m ax = 0 V IH VPP VCMR V P P r a n g e = 0 .1 to 1 .3 V V IL V C M R m in = V E E - 1 .2 V VEE V E E = - 2 .5 V o r - 3 .3 V Figure 2. ECL Differential Waveform Definitions tr, tf, 20-80% VO(p-p) Figure 3. ECL/LVPECL Output VPP / VDIF TPD VOD Figure 4. TPD Propagation Delay of Both CLKA or CLKB to Q0–Q9 Pair PECL/ECL to PECL/ECL Document #: 38-07502 Rev.*A Page 6 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY VPP / VDIF tPLH tPHL VO(P-P) tsk(P) Output pulse skew = | tPLH - tPHL | Figure 5. Output Pulse Skew VPP / VDIF Qn VO(P-P) tsk(0) Qn+m VO(P-P) Figure 6. Output-to-output Skew Document #: 38-07502 Rev.*A Page 7 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY Test Configurations Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm Pulse Generator Z = 50 ohm 5" Zo = 50 ohm Zo = 50 ohm 5" R T = 50 ohm DUT CY2PP3115 R T = 50 ohm VTT VTT Figure 7. CY2PP3115 AC Test Reference Applications Information Termination Examples C Y2PP3115 1 .3 V V C C = 3 .3 V RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm 1 .3 V VEE = 0V Figure 8. Standard LVPECL – PECL Output Termination C Y2PP3115 -2 V V C C = 0 .0 V RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm -2 V V E E = -3 .3 V Figure 9. Standard ECL Output Termination Document #: 38-07502 Rev.*A Page 8 of 12 FastEdge™ Series CY2PP3115 PRELIMINARY C Y2PP3115 VTT RT = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm VBB VEE Figure 10. Driving a PECL/ECL Single-ended Input C Y2PP3115 3 .3 V V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V VEE = 0V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS Figure 11. Low-voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface Document #: 38-07502 Rev.*A Page 9 of 12 PRELIMINARY FastEdge™ Series CY2PP3115 Evaluation Material Figure 12. Demonstration PCB Part Number Package Type Product Flow CY2PP3115AI 52-Pin TQFP Industrial, –40° to 85°C CY2PP3115AIT 52-Pin TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07502 Rev.*A Page 10 of 12 PRELIMINARY FastEdge™ Series CY2PP3115 Package Drawing and Dimensions 52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A52 51-85131-** FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07502 Rev.*A Page 11 of 12 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. FastEdge™ Series CY2PP3115 PRELIMINARY Document History Page Document Title: CY2PP3115 FastEdge™ Series 1:15 Differential Fanout Buffer Document Number: 38-07502 Orig. of Change REV. ECN NO. Issue Date ** 122042 02/12/03 RGL New Data Sheet *A 131090 11/21/03 RGL Supplied numbers for all specs with TBD after characterization Document #: 38-07502 Rev.*A Description of Change Page 12 of 12