Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT2543T 8-Bit Latched Transceiver SCCS042 - September 1994 - Revised March 2000 Features Functional Description • Function and pinout compatible with FCT and F logic • FCT-C speed at 5.3 ns max. FCT-A speed at 6.5 ns max. • 25Ω output series resistors to reduce transmission line reflection noise • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • Matched rise and fall times • Fully compatible with TTL input and output logic levels • Sink current 12 mA Source current 15 mA • Separation controls for data flow in each direction • Back to back latches for storage • ESD > 2000V • Extended commercial temp. range of –40˚C to +85˚C Functional Block Diagram The FCT2543T Octal Latched Tranceiver contains two sets of eight D-type latches. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) permits each latch set to have independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW to enter data from A or to take data from B, as indicated in the truth table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their output no longer change with the A inputs. With CEAB and OEAB both LOW, the three-state B output buffers are active and reflect data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs. On-chip termination resistors have been added to the outputs to reduce system noise caused by reflections. The FCT2543T can be used to replace the FCT543T to reduce noise in an existing design. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Pin Configurations Detail A SOIC/QSOP Top View B0 D Q LE A0 Q D LE LEBA 1 24 VCC OEBA 2 23 CEBA A0 3 22 B0 A1 4 21 B1 A1 B1 A2 5 20 B2 A2 B2 A3 6 19 B3 A3 B3 A4 7 18 B4 A4 B4 A5 8 17 B5 B5 A6 9 16 B6 A7 10 15 B7 CEAB 11 14 LEAB GND 12 13 OEAB A5 A6 A7 Detail A x 7 B6 B7 OEBA FCT2543T–3 OEAB CEBA CEAB LEBA LEAB FCT2543T–1 Copyright © 2000, Texas Instruments Incorporated CY74FCT2543T Maximum Ratings[4,5] Pin Description Name (Above which the useful life may be impaired. For user guidelines, not tested.) Description OEAB A-to-B Output Enable Input (Active LOW) Storage Temperature ..................................... −65°C to +150°C OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) Ambient Temperature with Power Applied .................................................. −65°C to +135°C CEBA B-to-A Enable Input (Active LOW) Supply Voltage to Ground Potential..................−0.5V to +7.0V LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A A-to-B Data Inputs or B-to-A Three-State Outputs B B-to-A Data Inputs or A-to-B Three-State Outputs DC Input Voltage .................................................−0.5V to +7.0V DC Output Voltage ..............................................−0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Power Dissipation .......................................................... 0.5W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Function Table[1,2] Operating Range Inputs Latch Outputs CEAB LEAB OEAB A-to-B[3] B H X X Storing High Z X H X Storing X X X H X High Z L L L Transparent Current A Inputs L H L Storing Previous A Inputs Range Commercial Ambient Temperature VCC −40°C to +85°C 5V ± 5% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ.[7] 2.4 3.3 VOH Output HIGH Voltage VCC=Min., IOH=−15 mA VOL Output LOW Voltage VCC=Min., IOL=12 mA ROUT Output Resistance VCC=Min., IOL=12 mA VIH Input HIGH Voltage VIL Input LOW Voltage VH Hysteresis[8] All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 IIH Input HIGH Current IIH Input HIGH Current IIL 20 Max. Unit V 0.3 0.55 V 25 40 Ω 2.0 V 0.8 V V −1.2 V VCC=Max., VIN=VCC 5 µA VCC=Max., VIN=2.7V ±1 µA Input LOW Current VCC=Max., VIN=0.5V ±1 µA IOZH Off State HIGH-Level Output Current VCC=Max., VOUT=2.7V 15 µA IOZL Off State LOW-Level Output Current VCC=Max., VOUT=0.5V −15 µA IOS Output Short Circuit Current[9] VCC=Max., VOUT=0.0V −225 mA IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1 µA Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. 2. A-to-B data flow shown: B-to-A is the same, except using CEBA, LEBA, and OEBA. 3. Before LEAB LOW-to-HIGH transition. 4. Unless otherwise noted, these limits are over the operating free-air temperature range. 5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 6. TA is the “instant on” case temperature. 2 −60 −120 CY74FCT2543T Capacitance[8] Parameter Description Test Conditions Typ.[7] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Typ.[7] Max. Unit 0.1 0.2 mA Power Supply Characteristics Parameter ICC Description Test Conditions Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC−0.2V ∆ICC Quiescent Power Supply Current (TTL inputs) VCC=Max., VIN=3.4V, f1=0, Outputs Open 0.5 2.0 mA ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, CEAB and OEAB=LOW, CEBA=HIGH, VIN≤0.2V or VIN≥VCC−0.2V 0.06 1.2 mA/ MHz IC Total Power Supply Current[12] VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB =10 MHz, VIN≤0.2V or VIN≥VCC−0.2V 0.7 1.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB =10 MHz, VIN=3.4V or VIN=GND 1.2 3.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB =10 MHz, VIN≤0.2V or VIN≥VCC−0.2V 2.8 5.6[13] mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB =10 MHz, VIN=3.4V or VIN=GND 5.1 14.6[13] mA [10] Notes: 7. Typical values are at VCC=5.0V, TA=+25˚C ambient. 8. This parameter is specified but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter tests, IOS tests should be performed last. 10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 12. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 3 CY74FCT2543T Switching Characteristics Over the Operating Range[14] CY74FCT2543T Parameter Description CY74FCT2543AT CY74FCT2543CT Min. Max. Min. Max. Min. Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Transparent Mode A to B or B to A 2.5 8.5 2.5 6.5 2.5 5.5 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A LEAB to B 2.5 12.5 2.5 8.0 2.5 7.0 ns 1, 5 tPZH tPZL Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 2.0 12.0 2.0 9.0 2.0 8.0 ns 1, 7, 8 tPZH tPZL Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 2.0 9.0 2.0 7.5 2.0 6.5 ns 1, 7, 8 tS Set-Up Time HIGH or LOW, A or B to LEBA or LEAB 2.0 2.0 2.0 ns 9 tH Hold Time HIGH or LOW, A or B to LEBA or LEAB 2.0 2.0 2.0 ns 9 tW Pulse Width LOW LEBA or LEAB 5.0 5.0 5.0 ns 5 Ordering Information Speed (ns) 5.3 6.5 8.5 Ordering Code CY74FCT2543CTQCT Package Name Package Type Q13 24-Lead (150-Mil) QSOP CY74FCT2543CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT2543ATQCT Q13 24-Lead (150-Mil) QSOP CY74FCT2543ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT2543TQCT Q13 24-Lead (150-Mil) QSOP Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. See “Parameter Measurement Information” in the General Information section. Document #: 38−00348−A 4 Operating Range Commercial Commercial Commercial CY74FCT2543T Package Diagrams 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated