ETC CY7C1371AV25

25
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
512Kx36/1Mx18 Flow-Thru SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT devices
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• Common I/O architecture
• Single 2.5V power supply
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device).
Write operations are controlled by the Byte Write Selects
(BWSa,b,c,d
for
CY7C1371AV25
and
BWSa,b for
CY7C1373AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
— 9.0 ns (for 83-MHz device)
— 10.0 ns (for 66-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability - linear or interleaved burst order
•
•
•
•
respectively designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1371AV25/CY7C1373AV25 is equipped
with the advanced No Bus Latency™ (NoBL) logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions.The
CY7C1371AV25/CY7C1373AV25 is pin compatible and functionally equivalent to ZBT devices.
Synchronous Chip Enable (CE1, CE2, CE3 on the TQFP, CE1
on the BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In
order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Functional Description
The CY7C1371AV25 and CY7C1373AV25 are 2.5V, 512K by
36 and 1M by 18 Synchronous-Flow-Through Burst SRAMs,
Logic Block Diagram
CLK
CE
D
Data-In REG.
Q
ADV/LD
Ax
CY7C1373
AX
CY7C1371
X = 18:0
DQX
X= a, b, c, d X = a, b
X = 19:0
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
CEN
CE1
CE2
CE3
WE
BWSx
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
DQx
DPx
Mode
OE
.Introduction
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Com’l
Maximum CMOS Standby Current (mA)
117 MHz
100 MHz
83 MHz
66 MHz
7.5
8.5
9.0
10.0
250
230
215
180
30
30
30
30
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 6, 2000
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1373AV25
(1M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
DNU
DNU
VSS
VDD
2
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DNU
DNU
A
A
A
A
A
A
CY7C1371AV25
(512K x 36)
NC
DPb
NC
DQb
DQb
NC
VDDQ V DDQ
VSS
V SS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
V
DDQ
VDDQ
DQb
DQb
DQb
DQb
Vss
VSS
V DD
VDD
V DD
VDD
VSS
NC
DQb
DQa
DQa
DQb
VDDQ V DDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa
DPb
DQa
NC
VSS
V SS
VDDQ VDDQ
DQa
NC
DQa
NC
NC
DPa
DNU
DNU
A
A
A
A
A
A
A
DQc
DQc
V SS
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DNU
DNU
VSS
VDD
DPc
DQc
DQc
VDDQ
A
A
A
A
CE 1
CE 2
NC
NC
BWSb
BWSa
CE 3
V DD
V SS
CLK
WE
CEN
OE
ADV/LD
NC
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE 1
CE 2
BWSd
BWSc
BWSb
BWSa
CE 3
V DD
V SS
CLK
WE
CEN
OE
ADV/LD
NC
A
100-Pin TQFP Packages
A
NC
NC
VDDQ
VSS
NC
DPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
VDD
VDD
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Pin Configurations (continued)
119-Ball Bump BGA
CY7C1371AV25 (512K x 36) - 7 x 17 BGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
4
5
6
7
VDDQ
A
A
16M
A
A
VDDQ
NC
NC
A
ADV/LD
A
NC
NC
NC
A
A
VDD
A
A
NC
DQc
DPc
VSS
NC
VSS
DPb
DQb
DQc
DQc
VSS
CE1
VSS
DQb
DQb
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
DQc
DQc
DQc
DQc
BWSc
VSS
A
WE
BWSb
VSS
DQb
DQb
DQb
DQb
VDDQ
VDD
VSS(1)
VDD
VSS(1)
VDD
VDDQ
DQd
DQd
VSS
CLK
VSS
DQa
DQa
DQd
DQd
BWSd
NC
BWSa
DQa
DQa
VDDQ
DQd
VSS
CEN
VSS
DQa
VDDQ
DQd
DQd
VSS
A1
VSS
DQa
DQa
DQd
DPd
VSS
A0
V SS
DPa
DQa
NC
A
MODE
VDD
VSS
A
NC
NC
64M
A
A
A
32M
NC
VDDQ
TMS
TDI
TCK
TDO
DNU
VDDQ
CY7C1373AV25 (1M x 18) - 7 x 17 BGA
1
2
3
4
5
6
7
A
V DDQ
A
A
16M
A
A
VDDQ
B
C
D
E
F
NC
NC
A
ADV/LD
A
NC
NC
NC
A
A
VDD
A
A
DQb
NC
VSS
NC
VSS
VSS
DPa
NC
NC
NC
DQa
VSS
DQa
VDDQ
G
H
J
K
L
M
NC
DQb
VSS
CE1
V DDQ
NC
VSS
NC
DQb
DQb
OE
A
WE
VDD
VSS
VSS
VSS(1)
NC
DQa
VDD
DQa
NC
VDDQ
V DDQ
VDD
BWSb
VSS
VSS(1)
NC
DQb
VSS
CLK
VSS
NC
DQa
DQb
NC
VSS
NC
DQb
VSS
CEN
BWSa
VSS
DQa
VDDQ
NC
V DDQ
N
P
DQb
NC
VSS
A1
VSS
DQa
NC
NC
DPb
VSS
A0
VSS
NC
DQa
R
T
U
NC
A
MODE
V DD
Vss
A
NC
64M
A
A
32M
A
A
NC
VDDQ
TMS
TDI
TCK
TDO
DNU
VDDQ
NC
3
NC
PRELIMINARY
CY7C1371AV25
CY7C1373AV25
Pin Definitions (100-Pin TQFP)
x18 Pin Location
x36 Pin Location
37, 36, 32–35,
44–50, 80–83, 99,
100
37, 36, 32–35,
44–50, 81–83, 99,
100
93, 94
Name
I/O Type
Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the 266,144 address
locations. Sampled at the rising edge of the CLK.
93, 94, 95, 96
BWSa
BWSb
BWSc
BWSd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
88
88
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
85
85
ADV/LD
InputSynchronous
Advance/Load input used to advance the on-chip address
counter or load a new address. When HIGH (and CEN is
asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device
for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
89
89
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the
device. CLK is qualified with CEN. CLK is only recognized
if CEN is active LOW.
98
98
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2 and CE3 to
select/deselect the device.
97
97
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
92
92
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
86
86
OE
InputOutput Enable, active LOW. Combined with the synchroAsynchronous nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
87
87
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the
clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to
extend the previous cycle when required.
(a)58, 59, 62, 63,
68, 69, 72–74,
(b)8, 9, 12, 13, 18,
19, 22–24
(a)52, 53, 56–59,
62, 63,
(b)68, 69, 72–75,
78, 79,
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
DQa
DQb
DQc
DQd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A[17:0] during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
4
PRELIMINARY
CY7C1371AV25
CY7C1373AV25
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
74, 24
51, 80, 1, 30
DPa
DPb
DPc
DPd
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences,
DPa is controlled by BWSa, DPb is controlled by BWSb,
DPc is controlled by BWSc, and DPd is controlled by
BWSd.
31
31
MODE
Input
Strap pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an interleaved burst order.
15, 41, 65, 66, 91
15, 41, 65, 66, 91
VDD
Power Supply
Power supply inputs to the core of the device.
4, 11, 20, 27, 54,
61, 70, 77
4, 11, 20, 27, 54,
61, 70, 77
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
5, 10, 14, 17, 21,
26, 40, 55, 60, 67,
71, 76, 90
5, 10, 14,17, 21, 26,
40, 55, 60, 67, 71,
76, 90
VSS
Ground
Ground for the device. Should be connected to ground of
the system.
64, 84
1-3, 6, 7, 25, 28-30,
51-53, 64, 75, 78,
79
NC
-
No connects. Reserved for address expansion to 512K
depths.
38, 39, 42, 43
38, 39, 42, 43
DNU
-
Do Not Use pins. These pins should be left floating.
5
PRELIMINARY
CY7C1371AV25
CY7C1373AV25
Pin Definitions (119 BGA)
x18 Pin Location
x36 Pin Location
Name
I/O Type
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5, C6, G4, R2, R6,
T2, T3, T5, T6
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5 C6, R2, R6, G4,
T3, T4, T5
A0
A1
A
InputSynchronous
Address Inputs used to select one of the 266,144 address locations. Sampled at the rising edge of the CLK.
L5, G3
L5, G5, G3, L3
BWSa
BWSb
BWSc
BWSd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
H4
H4
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
B4
B4
ADV/LD InputSynchronous
Advance/Local Input used to advance the on-chip address counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into
the device for an access. After being deselected,
ADV/LD should be driven LOW in order to load a new
address.
K4
K4
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
E4
E4
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK.
F4
F4
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
M4
M4
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
(a)P7, N6, L6, K7,
H6, G7, F6, E7
(b)N1, M2, L1, K2,
H1, G2, E2, D1
(a)P7, N7, N6, M6,
L7, L6, K7, K6
(b)D7, E7, E6, F6,
G7, G6, H7, H6
(c)D1, E1, E2, F2,
G1, G2, H1, H2
(d)P1, N1, N2, M2,
L1, L2, K1, K2
DQa
DQb
DQc
DQd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A[x:0] during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
D6, P2
P6, D6, D2, P2
DPa
DPb
DPc
DPd
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these
signals are identical to DQa–DQd. During write sequences, DPa is controlled by BWSa, DPb is controlled by
BWSb, DPc is controlled by BWSc, and DPd is controlled
by BWSd.
6
Description
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Pin Definitions (119 BGA) (continued)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
R3
R3
MODE
Input
Strap Pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will
default HIGH, to an interleaved burst order.
C4, J2, J4, J6, R4
C4, J2, J4, J6, R4
VDD
Power Supply
Power supply inputs to the core of the device.
A1, A7, F1, F7, J1,
J7, M1, M7, U1, U7
A1, A7, F1, F7, J1 VDDQ
J7, M1, M7, U1, U7
I/O Power
Supply
Power supply for the I/O circuitry.
D3, D5, E3, E5, F3,
F5, H3, H5, K3, K5,
M3, M5, N3, N5, P3,
P5, R5
D3, D5, E3, E5, F3,
F5, H3, H5, K3, K5,
M3, M5, N3, N5,
P3, P5, R5
VSS
Ground
Ground for the device. Should be connected to ground
of the system.
J3, J5
J3, J5
VSS(1)
U5
U5
TDO
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK.
U3
U3
TDI
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK.
U2
U2
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine.
Sampled on the rising edge of TCK.
U4
U4
TCK
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK.
A4, T6, T1
A4, T4, T2
16M,
32M
64M
-
No connects. Reserved for address expansion.
B1, B2, B7, C1, C7,
D2, D4, D7, E1, E6,
F2, G1, G5, G6, H2,
H7, J3, J5, K1, K6,
L2, L3, L4, M6, N2,
N7, P1, P6, R1, R7,
T7
B2, B7, C7, D4, J3,
J5, L4, R1, R7, T1,
T7
NC
-
No connects.
U6
U6
DNU
-
Do not use pin.
These pins have to be tied to a voltage level < VIL. They
need not be tied to VSS.
Functional Overview
Byte Write Selects can be used to conduct byte write operations.
The CY7C1371AV25/CY7C1373AV25 is a Synchronous
Flow-Through Burst NoBL SRAM designed specifically to
eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the
rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry
Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP,
CE 1 on the BGA) and an asynchronous Output Enable (OE)
simplify depth expansion. All operations (Reads, Writes, and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Accesses can be initiated by asserting Chip Enable(s) (CE1,
CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising
edge of the clock. If Clock Enable (CEN) is active LOW and
ADV/LD is asserted LOW, the address presented to the device
will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE).
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
7
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
On the next clock rise the data presented to DQ and DP (or a
subset for byte write operations, see Write Cycle Description
table for details) inputs is latched into the device and the write
is complete. Additional accesses (Read/Write/Deselect) can
be initiated on this cycle.
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate
to the output buffers. The data is available within 6.5 ns
(133-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
The data written during the Write operation is controlled by
Byte Write Select signals. The CY7C1371AV25/
CY7C1373AV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included
in order to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Burst Read Accesses
The CY7C1371AV25/CY7C1373AV25 has an on-chip burst
counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Because the CY7C1371AV25/CY7C1373AV25 are common
I/O devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DP inputs. Doing
so will three-state the output drivers. As a safety precaution,
DQ and DP are automatically three-stated during the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1371AV25/CY7C1373AV25 has an on-chip burst
counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and
CE 3) and WE inputs are ignored and the burst counter is incremented. The correct BWS a,b,c,d/BWS a,b inputs must be
driven in each cycle of the burst write in order to write the
correct bytes of data.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip Enable(s) asserted active, and (3) the write signal WE is asserted
LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block.
The data lines are automatically three-stated regardless of the
state of the OE input signal. This allows the external logic to
present the data on DQ and DP.
8
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Address
used
Operation
CE
CEN
ADV/
LD
WE
BWSx
Deselected
External
1
0
0
X
X
L-H
I/Os three-state following next recognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations suspended.
Begin Read
External
0
0
0
1
X
L-H
Address latched.
Begin Write
External
0
0
0
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst READ
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous access was a Read operation. Addresses incremented internally in
conjunction with the state of
MODE.
Burst WRITE
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous access was a Write operation. Addresses incremented internally in
conjunction with the state of
MODE. Bytes written are determined by BWSa,b,c,d/BWS a,b.
Second
Address
Third
Address
Comments
Linear Burst Sequence
Interleaved Burst Sequence
First
Address
CLK
First
Address
Fourth
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables. CE = 0 stands for ALL Chip Enables are active.
2. Write is defined by WE and BWSx. BWSx = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
9
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Write Cycle Description[1]
Function (CY7C1371AV25)
WE
BWSd
BWSc
BWSb
BWSa
Read
1
X
X
X
X
Write – No Bytes Written
0
1
1
1
1
Write Byte 0 − (DQa and DPa)
0
1
1
1
0
Write Byte 1 − (DQb and DPb)
0
1
1
0
1
Write Bytes 1, 0
0
1
1
0
0
Write Byte 2 − (DQc and DPc)
0
1
0
1
1
Write Bytes 2, 0
0
1
0
1
0
Write Bytes 2, 1
0
1
0
0
1
Write Bytes 2, 1, 0
0
1
0
0
0
Write Byte 3 − (DQb and DPd)
0
0
1
1
1
Write Bytes 3, 0
0
0
1
1
0
Write Bytes 3, 1
0
0
1
0
1
Write Bytes 3, 1, 0
0
0
1
0
0
Write Bytes 3, 2
0
0
0
1
1
Write Bytes 3, 2, 0
0
0
0
1
0
Write Bytes 3, 2, 1
0
0
0
0
1
Write All Bytes
0
0
0
0
0
WE
BWSb
BWSa
Read
1
x
x
Write – No Bytes Written
0
1
1
Write Byte 0 – (DQa and DPa)
0
1
0
Write Byte 1 – (DQb and DPc)
0
0
1
Write Both Bytes
0
0
0
Function (CY7C1373AV25)
10
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1371AV25/CY7C1373AV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block diagram. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation of the device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port (TAP) - Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (See TAP Controller State diagram). The output changes on the falling edge of TCK. TDO is
connected to the Least Significant Bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions
are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the
SRAM and cannot preload the Input or Output buffers. The
Test Data Out (TDO)
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the
11
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE / PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible
that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE / PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command.
Bypass
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE / PRELOAD
Reserved
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE Z
12
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
SHIFT-IR
0
1
0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-IR
EXIT2-DR
1
1
UPDATE-DR
1
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
13
UPDATE-IR
1
0
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[7, 8]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.7
V
VOH2
Output HIGH Voltage
IOH = −100 µA
2.1
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.7
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
1.7
VDD+0.3
V
VIL
Input LOW Voltage
−0.3
0.7
V
IX
Input Load Current
−5
5
µA
GND ≤ V I ≤ VDDQ
Notes:
7. All Voltage referenced to Ground.
8. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot:VIL (AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ <1.4V for t<200 ms.
14
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Description
Min.
Max
100
Unit
tTCYC
TCK Clock Cycle Time
ns
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
10
MHz
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
Notes:
9. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
15
ns
ns
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z0 = 50Ω
1.25V
CL = 20 pF
0V
GND
(a)
(b)
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
16
tTDOV
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Identification Register Definitions
Instruction Field
Value
Description
Revision Number
(31:28)
TBD
Reserved for version number.
Device Depth
(27:23)
TBD
Defines depth of SRAM.
Device Width
(22:18)
TBD
Defines with of the SRAM.
Cypress Device ID
(17:12)
TBD
Reserved for future use.
Cypress JEDEC ID
(11:1)
TBD
Allows unique identification of SRAM vendor.
ID Register Presence
(0)
TBD
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
TBD
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
17
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Boundary Scan Order
Signal Name
Bit #
Signal Name
7C1371AV25
7C1373AV25
Bump ID
Bit #
7C1371AV25
7C1373AV25
1
CE3
CE3
B6
35
A0
A0
2
BWSa
BWSa
L5
36
A
A
3
BWSb
BWSb
G5 for 1354
37
A
A
G3 for 1356
38
A
A
Bump ID
P4
4
BWSc
NC
G3
39
A
A
5
BWSd
NC
L3
40
A
A
6
CE2
CE2
B2
41
A
A
7
CE1
CE1
E4
42
A
A
8
A
A
43
DPa
NC
9
A
A
44
DQa
NC
10
DPc
NC
45
DQa
NC
11
DQc
NC
46
DQa
NC
12
DQc
NC
47
DQa
NC
13
DQc
NC
48
DQa
DQa
14
DQc
NC
49
DQa
DQa
15
DQc
DQb
50
DQa
DQa
16
DQc
DQb
51
DQa
DQa
17
DQc
DQb
52
Vss
Vss
18
DQc
DQb
53
DQb
DQa
19
Vss
Vss
54
DQb
DQa
20
DQd
DQb
55
DQb
DQa
21
DQd
DQb
56
DQb
DQa
22
DQd
DQb
57
DQb
DPa
23
DQd
DQb
58
DQb
NC
24
DQd
DPb
59
DQb
NC
25
DQd
NC
60
DQb
NC
26
DQd
NC
61
DPb
A
27
DQd
NC
62
A
A
28
DPd
NC
P2
63
A
A
29
Mode
Mode
R3
64
A
A
G4
30
A
A
65
ADV/LD
ADV/LD
B4
31
A
A
66
OE
OE
F4
32
A
A
67
CEN
CEN
M4
33
A
A
68
GW
GW
H4
34
A1
A1
69
CLK
CLK
K4
D2
R5
N4
18
P6
T7
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND .........−0.5V to +3.6V
Range
DC Voltage Applied to Outputs
in High Z State[12]....................................−0.5V to VDDQ + 0.5V
Com’l
Ambient
Temperature[11]
VDD/VDDQ
0°C to +70°C
2.5V ± 5%
DC Input Voltage[12] ................................−0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
Test Conditions
Output HIGH Voltage
VDD = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[12]
IX
Input Load Current
VOH
[13]
Unit
V
2.375
2.625
V
2.0
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
V
0.2
V
1.7
VDD +
0.3V
V
−0.3
0.7
V
−5
5
µA
−30
30
µA
−5
5
µA
10-ns cycle, 117 MHz
250
mA
12-ns cycle, 100 MHz
230
mA
15-ns cycle, 83MHz
215
mA
15-ns cycle, 66MHz
180
mA
10- ns cycle, 117 MHz
90
mA
12-ns cycle, 100 MHz
80
mA
15-ns cycle, 83MHz
75
mA
15-ns cycle, 66MHz
65
mA
GND ≤ VI ≤ VDDQ
IOZ
Automatic CE
Power-Down
Current—TTL Inputs
Max.
2.625
[13]
Input Current of MODE
ISB1
Min.
2.375
ISB2
Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or V IN > VDDQ − 0.3V,
f=0
All speed grades
30
mA
ISB3
Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
f = fMAX = 1/tCYC
10- ns cycle, 117 MHz
85
mA
12-ns cycle, 100 MHz
70
mA
15-ns cycle, 83MHz
65
mA
15-ns cycle, 66MHz
55
mA
All speed grades
40
mA
ISB4
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Notes:
11. TA is the case temperature.
12. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
13. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads.
19
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Capacitance[14]
Parameter
Description
Test Conditions
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = VDDQ = 2.5V
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Max.
Unit
4
pF
4
pF
4
pF
AC Test Loads and Waveforms
R=1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 =50Ω
RL =50Ω
2.5V
10%
5 pF
R=1538Ω
VL = 1.25V
(a)
INCLUDING
JIG AND
SCOPE
[15]
90%
10%
90%
GND
≤ 2.0 ns
≤ 2.0 ns
(c)
(b)
Thermal Resistance[14]
Description
Test Conditions
Symbol
TQFP Typ.
Units
Thermal Resistance (Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board.
ΘJA
TBD
°C/W
ΘJC
TBD
°C/W
Thermal Resistance (Junction to Case)
Notes:
14. Tested initially and after any design or process change that may affect these parameters.
15. Input waveform should have a slew rate of > 1 V/ns.
20
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Switching Characteristics Over the Operating Range[16]
117
Parameter
Description
Min.
100
Max.
Min.
83
Max.
Min.
66
Max.
Min.
Max.
Unit
Clock
tCYC
Clock Cycle Time
8.5
10.0
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
3.0
3.0
3.0
3.0
ns
tCL
Clock LOW
3.0
3.0
3.0
3.0
ns
117
12.0
100
15.0
83
ns
66
MHz
Output Times
tCDV
Data Output Valid After CLK Rise
[14, 19]
tEOV
OE LOW to Output Valid
tDOH
Data Output Hold After CLK Rise
1.5
tCHZ
Clock to High-Z[17, 18, 19]
1.5
tCLZ
[17, 18, 19]
tEOHZ
tEOLZ
Clock to Low-Z
8.5
9.0
10.0
ns
3.5
4.0
4.0
4.0
ns
1.5
5.0
3
OE HIGH to Output High-Z
OE LOW to Output Low-Z
7.5
5.0
3
[17, 18, 19]
[17, 18, 19]
1.5
1.5
4.0
1.5
1.5
5.0
3
4.0
1.5
ns
5.0
3
4.0
ns
ns
4.0
ns
0
0
0
0
ns
Set-up Times
tAS
Address Set-Up Before CLK Rise
2.0
2.0
2.0
2.0
ns
tDS
Data Input Set-Up Before CLK Rise
2.0
2.0
2.0
2.0
ns
tCENS
CEN Set-Up Before CLK Rise
2.0
2.0
2.0
2.0
ns
tWES
WE, BWSx Set-Up Before CLK Rise
2.0
2.0
2.0
2.0
ns
tALS
ADV/LD Set-Up Before CLK Rise
2.0
2.0
2.0
2.0
ns
tCES
Chip Select Set-Up
2.0
2.0
2.0
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
Hold Times
Shaded areas contain advance information.
Notes:
16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I OL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
17. t CHZ, tCLZ, tOEV, tEOLZ, and t EOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
18. At any given voltage and temperature, t EOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
21
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Switching Waveforms
DESELECT
DESELECT
Suspend
Read
Read
Write
Read
DESELECT
Read
Read
Write
Read/Write/Deselect Sequence
CLK
tCENH
tCENS
tCH tCL
tCENH
tCENS
tCYC
CEN
tAS
ADDRESS
WA2
RA1
RA3
WA5
RA4
RA6
RA7
tAH
WE
tWES
tCES
tWEH
tCEH
CE
tCLZ
tCHZ
tDOH
Data
In/Out
Q1
Out
tCHZ
D2
In
Q4
Out
Q3
Out
D5
In
Device
tCDV
originally
deselected
Q6
Out
Q7
Out
tDOH
WE is the combination of WE & BWSx(x=a, b, c, d) to define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select
the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
22
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Switching Waveforms (continued)
Burst Read
Burst Read
Begin Read
Burst Write
Burst Write
Burst Write
Begin Write
Burst Read
Burst Read
Burst Read
Begin Read
Burst Sequences
CLK
tALH
tALS
tCH tCL
tCYC
ADV/LD
tAS tAH
ADDRESS
RA1
WA2
RA3
WE
tWEH
tWES
tWS tWH
BWSx
tCES tCEH
CE
tCLZ
Data
In/Out
tCHZ
tDOH
Q11a
Out
Q1+1
Out
Q1+2
Out
Q1+3
Out
D2
In
tCDV
t
DeviceCDV
originally deselected
tCLZ
tDH
D2+1
In
D2+2
In
D2+3
In
Q3
Out
tDS
The combination of WE & BWS x(x=a, b, c, d) define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
23
Q3+1
Out
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/O’s
tEOLZ
Ordering Information
Speed
(MHz)
117
Ordering Code
CY7C1371AV25-117AC/
CY7C1373AV25-117AC
CY7C1371AV25-117BGC/
CY7C1373AV25-117BGC
100
CY7C1371AV25-100AC/
CY7C1373AV25-100AC
CY7C1371AV25-100BGC/
CY7C1373AV25-100BGC
83
CY7C1371AV25-83AC/
CY7C1373AV25-83AC
CY7C1371AV25-83BGC/
CY7C1373AV25-83BGC
66
CY7C1371AV25-66AC/
CY7C1373AV25-66AC
CY7C1371AV25-66BGC/
CY7C1373AV25-66BGC
Package
Name
Package Type
Operating
Range
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
BG119
A101
BG119
A101
BG119
A101
BG119
7 x 17 BGA
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
7 x 17 BGA
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
7 x 17 BGA
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
7 x 17 BGA
Shaded areas contain advance information.
Document #: 38-01005-A
24
PRELIMINARY
CY7C1371AV25
CY7C1373AV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
25
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Revision History
Document Title: CY7C1371AV25/CY7C1373AV25
Document Number: 38-01005
REV.
ECN NO.
ISSUE DATE
ORIG. OF
CHANGE
**
3027
4/28/2000
CXV
1. New Data sheet
*A
3090
6/15/00
CXV
1. Correct pin ID, pin #43, B2
DESCRIPTION OF CHANGE
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.