31 CYM1831 64K x 32 Static RAM Module Features • High-density 2-Mbit SRAM module • 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 • High-speed CMOS SRAMs — Access time of 15 ns • Low active power — 5.3W (max.) • SMD technology • TTL-compatible inputs and outputs • Low profile — Max. height of 0.50 in. • Small PCB footprint — 1.2 sq. in. Functional Description The CYM1831 is a high-performance 2-Mbit static RAM module organized as 64K words by 32 bits. This module is constructed from eight 64K x 4 SRAMs in SOJ packages mounted on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Selects (CSN) and Write Enable (WE) inputs are both LOW. Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Selects (CSN) LOW and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/OX). The data input/output pins stay in the high-impedance state when Write Enable (WE) is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. Logic Block Diagram A0 –A15 OE WE Pin Configuration PD0 - OPEN PD1 - GND 16 64K x 4 SRAM 4 64K x 4 SRAM 4 I/O0 – I/O3 64K x 4 SRAM 4 I/O8 – I/O11 64K x 4 SRAM 4 I/O4– I/O7 CS1 I/O12– I/O15 CS2 64K x 4 SRAM 4 64K x 4 SRAM 4 I/O16 – I/O19 64K x 4 SRAM 4 I/O24 – I/O27 64K x 4 SRAM 4 I/O20– I/O23 CS3 I/O28– I/O31 CS4 Cypress Semiconductor Corporation Document #: 38-05270 Rev. ** • 3901 North First Street • San Jose • ZIP/SIMM Top View PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 CS3 NC GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 CA 95134 • 408-943-2600 Revised March 15, 2002 CYM1831 Selection Guide 1831-15 1831-20 1831-25 1831-30 1831-35 1831-45 15 20 25 30 35 45 Maximum Operating Current (mA) 1120 960 720 720 720 720 Maximum Standby Current (mA) 160 160 160 160 160 160 Maximum Access Time (ns) Maximum Ratings Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Output Current into Outputs (LOW) .............................20 mA Electrical Characteristics Over the Operating Range 1831-15 Parameter Description Test Conditions Min. Max. 2.4 1831-20 Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC 2.2 VCC VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 IIX Input Load Current GND < VI < VCC –20 +20 –20 +20 IOZ Output Leakage Current GND < VO < VCC, Output Disabled –20 +20 –20 +20 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CSN < VIL 1120 ISB1 Automatic CS Power-Down Current[1] VCC = Max., CSN > VIH, Min. Duty Cycle = 100% ISB2 Automatic CS Power-Down Current[1] VCC = Max., CSN > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0.4 1831-25, 30, 35, 45 Min. Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC V –0.5 0.8 V –20 +20 µA –20 +20 µA 960 720 mA 320 320 320 mA 160 160 160 mA Capacitance[2] Parameter Description CINA Input Capacitance (A0–A15, WE, OE) CINB Input Capacitance (CS) COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 80 pF 15 pF 20 pF Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. Document #: 38-05270 Rev. ** Page 2 of 8 CYM1831 AC Test Loads and Waveforms R1 481 Ω R1 481 Ω 5V ALL INPUT PULSES 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE 3.0V 90% OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) R2 255Ω 90% 10% 10% GND < 5 ns < 5 ns (b) Equivalent to: THÉ VENIN EQUIVALENT 167Ω 1.73V OUTPUT Switching Characteristics Over the Operating Range[3] 1831-15 Parameter Description 1831-20 1831-25 1831-30 1831-35 1831-45 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 15 20 tOHA Data Hold from Address Change tACS CS LOW to Data Valid 15 20 25 30 35 45 ns tDOE OE LOW to Data Valid 8 10 15 20 20 30 ns tLZOE OE LOW to Low Z tHZOE OE LOW to High Z 15 3 3 0 CS LOW to Low Z tHZCS CS HIGH to High Z[4, 5] 30 25 3 0 8 [4] tLZCS 25 20 3 0 10 0 35 30 3 0 15 3 45 35 3 0 15 3 ns 45 ns 0 20 3 ns ns 20 3 ns ns 0 6 8 13 15 20 20 ns [6] WRITE CYCLE tWC Write Cycle Time 15 20 25 30 35 45 ns tSCS CS LOW to Write End 10 15 20 25 30 40 ns tAW Address Set-Up to Write End 10 15 20 25 30 40 ns tHA Address Hold from Write End 2 2 2 2 2 2 ns tSA Address Set-Up to Write Start 2 2 2 2 2 2 ns tPWE WE Pulse Width 10 15 20 25 25 30 ns tSD Data Set-Up to Write End 8 12 15 15 20 20 ns tHD Data Hold from Write End 2 2 2 2 2 2 ns tLZWE WE HIGH to Low Z 3 tHZWE WE LOW to High Z[5] 0 3 7 0 3 10 0 3 13 0 3 15 0 3 20 0 ns 20 ns Note: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05270 Rev. ** Page 3 of 8 CYM1831 Switching Waveforms Read Cycle No. 1 [7, 8] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No . 2[7, 9] tRC CS tACS OE tHZOE tHZCS tDOE tLZOE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE ICC 50% 50% ISB Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL and OE= VIL. 9. Address valid prior to or coincident with CS transition LOW. Document #: 38-05270 Rev. ** Page 4 of 8 CYM1831 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[6] tWC ADDRESS tSCS CS tAW tSA tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED Write Cycle No. 2 (CS Controlled)[6, 10] tWC ADDRESS tSCS tSA CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CSN WE OE Inputs/Outputs Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Document #: 38-05270 Rev. ** Page 5 of 8 CYM1831 Ordering Information Speed 15 20 25 35 45 Ordering Code Package Name Package Type CYM1831PM–15C PM01 64-Pin Plastic SIMM Module CYM1831PN–15C PN01 64-Pin Plastic Angled SIMM Module CYM1831PY–15C PM01 64-Pin Gold SIMM Module CYM1831PZ–15C PZ01 64-Pin Plastic ZIP Module CYM1831PM–20C PM01 64-Pin Plastic SIMM Module CYM1831PN–20C PN01 64-Pin Plastic Angled SIMM Module CYM1831PY–20C PM01 64-Pin Gold SIMM Module CYM1831PZ–20C PZ01 64-Pin Plastic ZIP Module CYM1831PM–25C PM01 64-Pin Plastic SIMM Module CYM1831PN–25C PN01 64-Pin Plastic Angled SIMM Module CYM1831PY–25C PM01 64-Pin Gold SIMM Module CYM1831PZ–25C PZ01 64-Pin Plastic ZIP Module CYM1831PM–35C PM01 64-Pin Plastic SIMM Module CYM1831PN–35C PN01 64-Pin Plastic Angled SIMM Module CYM1831PY–35C PM01 64-Pin Gold SIMM Module CYM1831PZ–35C PZ01 64-Pin Plastic ZIP Module CYM1831PM–45C PM01 64-Pin Plastic SIMM Module CYM1831PN–45C PN01 64-Pin Plastic Angled SIMM Module CYM1831PY–45C PM01 64-Pin Gold SIMM Module CYM1831PZ–45C PZ01 64-Pin Plastic ZIP Module Document #: 38-05270 Rev. ** Operating Range Commercial Commercial Commercial Commercial Commercial Page 6 of 8 CYM1831 Package Diagrams 64-Pin Plastic SIMM Module PM01 0.125 DIA. + 0.001 2 PLCS 3.845 3.855 3.580 3.588 0.330 MAX 0.525 MAX 0.400 0.250 0.050 TYP PIN 1 0.080 0.145 REF 0.62 R + 0.001 0.250 PIN 64 3.35 (64 PINS) 0.250 64-Pin Plastic Angled SIMM Module PN01 3.845/3.855 .330MAX C9 C8 U4 C10 C7 U3 C6 U2 C4 C2 U1 .397/.403 .245/.255 C5 C3 C1 3.580/3.588 .590/.600 .061/.063R PIN1 .249/.251 .075/.085 .245/.255 3.348/3.352 64-Pin Plastic ZIP Module PZ01 Bottom View 0.330 MAX 3.640 3.660 0.050 0.050 0.500 MAX 0.120 0.150 0.008 0.014 0.135 0.165 0.015 0.025 0.250 TYP 0.100 TYP 0.050 TYP 0.100 TYP Pin 1 DIMENSIONS IN INCHES MIN. MAX. Document #: 38-05270 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1831 Document Title: CYM1831 64K x 32 Static RAM Module Document Number: 38-05270 REV. ECN NO. Issue Date Orig. of Change ** 114171 3/19/02 DSG Document #: 38-05270 Rev. ** Description of Change Change from Spec number: 38-M-00018 to 38-05270 Page 8 of 8