MICRONAS Edition July 23, 1999 6251-109-4E 6251-467-1DS DAC 3550A Stereo Audio DAC MICRONAS DAC 3550A Contents Page Section Title 3 3 1. 1.1. Introduction Main Features 5 5 6 6 6 6 6 6 7 7 8 8 8 9 9 9 9 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.10.1. 2.10.2. 2.11. 2.12. 2.13. 2.14. Functional Description I2S Interface Interpolation Filter Variable Sample and Hold 3rd-order Noise Shaper and Multibit DAC Analog Low-pass Input Select and Mixing Matrix Postfilter Op Amps, Deemphasis Op Amps, and Line-Out Analog Volume Headphone Amplifier Clock System Standard Mode MPEG Mode I2C Bus Interface Registers Chip Select Reduced Feature Mode 10 10 10 12 12 12 12 13 13 14 15 17 17 18 20 3. 3.1. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.4. 3.5. 3.6. 3.7. 3.7.1. 3.7.2. 3.7.3. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Oscillator and Clock Pins Other Pins Pin Configuration Pin Circuits Control Registers Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics 25 25 25 26 26 27 27 27 28 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.5.1. 4.5.2. 4.6. Applications Line Output Details Recommended Low-Pass Filters for Analog Outputs Recommendations for Filters and Deemphasis Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass Power-up/down Sequence Power-up Sequence Power-down Sequence Typical Applications 32 5. Data Sheet History 2 Micronas DAC 3550A Stereo Audio DAC 1.1. Main Features – no master main input clock required 1. Introduction – integrated stereo headphone amplifier and mono speaker amplifier The DAC 3550A is a single-chip, high-precision, dual digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With Micronas’ unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio has been achieved. The DAC 3550A is controlled via I2C bus. – SNR of 103 dBA – I2C bus, I2S bus – internal clock oscillator – full-feature mode by I2C control (three selectable subaddresses) – reduced feature mode for non-I2C applications Digital audio input data is received by a versatile I2S interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3550A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported. – continuous sample rates from 8 kHz to 50 kHz – analog deemphasis for 44.1 kHz – analog volume and balance: +18…−75 dB and mute – oversampling and multibit noise-shaping technique – THD better than 0.01 % The DAC 3550A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, etc. The DAC 3550A ideally complements the MPEG 1/2 layer 2/3 audio decoder MAS 3507D. – two additional analog stereo inputs (AUX) with source selection and mixing – supply range: 2.7 V…5.5 V – low-power mode No crystal required for standard applications with sample rates from 32 to 48 kHz. Crystal required only for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10), and use of clock output CLKOUT. – additional line-out – on-chip op amps for cost-effective external analog sound processing Analog Inputs WSI CLI I2S DRI Interpolation Filter Input Select and Mixing DAC Volume and Headphone Amplifier OUTL OUTR Fig. 1–1: Block diagram of the DAC 3550A demand signal Host (PC, Controller) MPEG clock MAS MPEG bit stream 3507D I2S DAC 3550A line out 14.725 MHz ROM, CD-ROM, CLKOUT RAM, Flash Mem. .. Fig. 1–2: Typical application: MPEG Layer 3 Player Micronas 3 DAC 3550A CLI DAI WSI 23 24 25 I 2S Sample Rate Detection Digital Supply Interpolation Filter Analog Supply PLL Variable S & H 14 XTO 13 XTI 12 3rd-order Noise Shaper & Multibit DAC Osc. AUX2L 29 AUX1L 31 DEEML 34 FOPL 38 FOUTL 37 FINL 39 I C Control Analog Low-pass Filter Input Select Switch Matrix Postfilter Op Amps Deemphasis Op Amps Line-Out Vdd 17 Vss 9 AVDD0 10 AVDD1 3 AVSS0 2 AVSS1 44 VREF 1 2 CLKOUT 18 AGNDC 16 SDA 15 SCL 27 TESTEN 26 PORQ 21 DEECTRL 19 MCS1 20 MCS2 32 AUX1R 30 AUX2R 35 DEEMR 42 FOPR 41 FOUTR 43 FINR Analog Volume Headphone Amplifier 5 7 OUTL OUTR Fig. 1–3: Block diagram of the DAC 3550A 4 Micronas DAC 3550A 2. Functional Description 2.1. I2S Interface The I2S interface is the digital audio interface between the DAC 3550A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I2S-compatible formats. Automatic Detection No I2C control is required to switch between 16- and 32-bit mode. It is recommended to switch the DAC 3550A into mute position during changing between 16- and 32-bit mode. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available). All modes have two common features: 1. The MSB is left justified to an I2S frame identification (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode In this case, the bit clock is 32 × fsaudio. Maximum word length is 16 bit. 32-bit mode In this case, the bit clock is 64 × fsaudio. Maximum word length is 32 bit. Left-Right Selection Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. However, I2C control allows changing the polarity of WSI. Delay Bit Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2C control. Vh CLI Vl Vh DAI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vl programmable delay bit WSI Vh Vl left 16-bit audio sample right 16-bit audio sample Fig. 2–1: I2S 16-bit mode (LR_SEL=0) Vh CLI Vl Vh DAI 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 Vl programmable delay bit WSI Vh Vl left 32-bit audio sample Fig. 2–2: I2S 32-bit mode (LR_SEL=0) Micronas right 32-bit audio sample Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks. 5 DAC 3550A 2.2. Interpolation Filter 2.6. Input Select and Mixing Matrix The interpolation filter increases the sampling rate by a factor of 8. The characteristic for fsaudio = 48 kHz is shown in Fig. 2–3. This block is used to switch between or mix the auxiliary inputs and the signals coming from the DAC. A switch matrix allows to select between mono and stereo mode as shown in Fig. 2–4. dB 0 DAD DAI WSI -0.02 -0.04 FOUTL D/A FOUTR 24.576 MHz -0.06 -0.08 AUX1L - -0.1 AUX1R - -0.12 AUX2L - AUX2R - -0.14 0 5000 10000 15000 20000 f/Hz Fig. 2–3: 1→8 Interpolation filter; frequency range: 0...22 kHz AUX_MS INSEL_AUX2 INSEL_AUX1 INSEL_DAC Fig. 2–4: Switch matrix 2.3. Variable Sample and Hold The advantage of this system is that even at low sample frequencies the out-of-band noise is not scaled down to audible frequencies. Mono mode is realized by adding left and right channel. 2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out 2.4. 3rd-order Noise Shaper and Multibit DAC The 3rd-order noise shaper converts the oversampled audio signal into a 5-bit noise-shaping signal at a high sampling rate. This technique results in extremely low quantization noise in the audio band. This block contains the active components for the analog postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 2–5. 2.5. Analog Low-pass The analog low-pass is a first order filter with a cut-off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal. 6 Micronas DAC 3550A AGNDC + For external components, see section “Applications” 3.3 µF/100 nF + OUTL VREF FOUTL DEEML FOPL FOUTR DEEMR FOPR - Speaker 1.5 kΩ 150 µF AVSS AVOL_R optional line-out 32 Ω 47 Ω FINL from switch matrix 16-32 Ω 47 Ω FINR - Headphones 150 µF - IRPA AVOL_L + For external components, see section “Applications” AVDD 1.5 kΩ OUTR to µC (HP-switch) Fig. 2–5: Postfilter op amps, deemphasis op amps, and line-out 2.8. Analog Volume Table 2–1: Volume Control The analog volume control covers a range from +18 dB to −75 dB. The lowest step is the mute position. Volume/dB AVOL 18.0 111000 Step size is split into a 3-dB and a 1.5-dB range: 16.5 110111 −75 dB...−54 dB: 3 dB step size −54 dB...+18 dB: 1.5 dB step size 15.0 110110 13.5 110101 2.9. Headphone Amplifier − − The headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or a mono loudspeaker. The stereo headphones require external 47-Ω serial resistors in both channels. If a loudspeaker is connected to these outputs, the power amplifier for the right channel must be switched to inverse polarity. In order to optimize the available power, the source of the two output amplifiers should be identical, i.e. a monaural signal. 0.0 101100 (default) −1.5 101011 − − −54.0 001000 −57.0 000111 − − −75 000001 Mute 000000 Please note, that if a speaker is connected, it should strictly be connected as shown in Fig. 2–5. Never use a separate connector for the speaker, because electrostatic discharge could damage the output transistors. Micronas 7 DAC 3550A 2.10. Clock System 2.10.1. Standard Mode The advantage of the DAC 3550A clock system is that no external master clock is needed. Most DACs need 256 × fsaudio, 384 × fsaudio, or at least an asynchronous clock. All internal clocks are generated by a PLL circuit, which locks to the I2S bit clock (CLI). If no I2S clock is present, the PLL runs free, and it is guaranteed that there is always a clock to keep the IC controllable by I2C. The device can be set to two different modes: – Standard mode – MPEG mode In the standard mode, I2C subaddressing is possible (ADR0, ADR1, ADR2). MPEG mode always uses ADR3. To select the modes, the MCS1/MCS2 pins must be set according to Table 2–2. – without I2C In standard mode, sample rates from 48 kHz to 32 kHz are handled without I2C control automatically. The setting for this range is the default setting. – with I2C Sample rates below 32 kHz require an I2C control to set the PLL divider. This ensures that even at low sample rates, the DAC 3550A runs at a high clock rate. This avoids audible effects due to the noiseshaping technique of the DAC 3550A. Sample rate range is continuous from 8 to 50 kHz. The I2C setting of low sample rates must follow according to Section 3.6. “Control Registers” on page 15. An additional mode allows automatic sample rate detection. In this case, the clock oscillator is required and must run at frequencies between 13.3 MHz to 17 MHz. This mode, however, does not support continuous sample rates. Only the following sample rates are allowed: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz The sample rate detection allows a tolerance of ±200 ppm at WSI. Table 2–2: Operation Modes MCS1 MCS2 Mode Subaddress Default Sample Rate 0 0 Standard ADR0 32–48 kHz If the oscillator is not used for automatic sample rate detection, it can be used as a general-purpose clock for the application. The frequency range in this case is 10 MHz to 25 MHz. 0 1 Standard ADR1 32–48 kHz 2.10.2. MPEG Mode 1 0 Standard ADR2 32–48 kHz 1 1 MPEG ADR3 Automatic This mode should be used in conjunction with MAS 3507D in MPEG player applications. In this case a 14.725 MHz signal is needed to provide a clock for the MAS 3507D and to allow an automatic sample rate detection in the DAC 3550A. All MPEG sample rates from 8 to 48 kHz can be detected. The internal processing and the DAC itself are automatically adjusted to keep constant performance throughout the entire range. I2C control for sample rate adjustment is not needed in this case. Register SR_REG[0:2] is locked to SRC_A; see Section 3.6. “Control Registers” on page 15. The MPEG sample rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz As in standard mode, the sample rate detection allows a tolerance of ±200 ppm at WSI. Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3550A can run in MPEG mode. 8 Micronas DAC 3550A 2.11. I2C Bus Interface The DAC 3550A is equipped with an I2C bus slave interface. The I2C bus interface uses one level of subaddressing: The I2C bus address is used to address the IC. The subaddress allows chip select in multi DAC applications and selects one of the three internal registers. The registers are write-only. The I2C bus chip address is given below. The registers of the DAC 3550A have 8- or 16-bit data size; 16-bit registers are accessed by writing two 8-bit data words. A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 1 1 0 1 0 dev_write = $9A. S S dev_write Ack sub_adr Ack 1 byte data Ack P dev_write Ack sub_adr Ack 1 byte data Ack SDA SCL 1 0 S 8-bit I2C write access 1 byte data Ack W R Ack Nak S P P 16-bit I2C write access P = = = = = = 0 1 0 1 Start Stop Fig. 2–6: I2C bus protocols for write operations 2.12. Registers 2.13. Chip Select In Section 3.6. “Control Registers” on page 15, a definition of the DAC 3550A control registers is shown. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in the table. Chip select allows to connect up to four DAC 3550A to an I2C control bus. The chip subaddresses are defined by the MCS1/MCS2 (Mode and Chip Select) pins. Only in standard mode, chip select is possible. MPEG mode always uses chip subaddress 3. All registers are write-only. Register address and chip select are mapped into the subaddress field in Table 2–4. The register address is coded by 3 bits (RA1, RA0) according to Table 2–3. 2.14. Reduced Feature Mode Table 2–3: I2C Register Address RA1 RA0 Mnemonics 0 1 SR_REG 1 0 AVOL 1 1 GCFG If I2C control is not used, the IC is in the default mode (see Section 3.6. “Control Registers” on page 15) after start-up. Default Volume setting is 0 dB and digital audio input is set to standard I2S. Sample rates from 32 kHz to 48 kHz are supported in this mode. Applications with no need for volume control or analog input could use this mode. Table 2–4: I2C Subaddress The mnemonics used in the DAC 3550A demo software of Micronas are given in the last column. Micronas 7 6 MCS2 MCS1 5 4 3 2 1 0 RA1 RA0 9 DAC 3550A 3. Specifications 3.1. Outline Dimensions 10 x 0.8 = 8 0.8 0.17 33 23 1.75 0.8 10 x 0.8 = 8 1.3 10 0.375 22 13.2 34 12 44 1 11 1.75 2.0 13.2 10 0.1 2.15 D0024/2E Fig. 3–1: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approximately 0.4 g Dimensions in mm 3.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant VSS = if not used, connect to VSS = obligatory; connect as described in application diagram VDD = connect to VDD Pin No. Pin Name 1 AGNDC IN/OUT X Analog reference Voltage 2 AVSS1 IN X VSS 1 for audio back-end 3 AVSS0 IN X VSS 0 for audio output amplifiers 4 NC LV Not connected 5 OUTL LV Audio Output: Headphone left or Speaker + 6 NC LV Not connected 7 OUTR LV Audio Output: Headphone right or Speaker − 8 NC LV Not connected 9 AVDD0 IN X VDD 0 for audio output amplifiers 10 AVDD1 IN X VDD 1 for audio back-end 11 NC LV Not connected 12 XTI IN X Quartz oscillator pin 1 13 XTO IN/OUT X Quartz oscillator pin 2 14 CLKOUT OUT LV Clock Output 15 SCL IN/OUT LV I2C clock 10 Type X Connection Short Description (if not used) OUT OUT Micronas DAC 3550A Pin No. Pin Name 16 SDA IN/OUT LV I2C data 17 VSS IN X Digital VSS 18 VDD IN X Digital VDD 19 MCS1 IN X I2C Chip Select 1 20 MCS2 IN X I2C Chip Select 2 21 DEECTRL IN VSS Deemphasis on/off Control 22 NC LV Not connected 23 CLI VSS I2S Bit Clock 24 DAI IN VSS I2S Data 25 WSI IN VSS I2S Frame Identification 26 PORQ IN VDD Power-On Reset, active-low 27 TESTEN IN X Test Enable 28 NC LV Not connected 29 AUX2L IN LV AUX2 left input for external analog signals (e.g. tape) 30 AUX2R IN LV AUX2 right input for external analog signals (e.g. tape) 31 AUX1L IN LV AUX1 left input for external analog signals (e.g. FM) 32 AUX1R IN LV AUX1 right input for external analog signals (e.g. FM) 33 NC LV Not connected 34 DEEML OUT LV Deemphasis Network Left 35 DEEMR OUT LV Deemphasis Network Right 36 NC LV Not connected 37 FOUTL OUT X Output to left external filter 38 FOPL IN/OUT X Filter op amp inverting input, left 39 FINL IN/OUT X Input for FOUTL or filter op amp output (line out) 40 NC LV Not connected 41 FOUTR OUT X Output to right external filter 42 FOPR IN/OUT X Right Filter op amp inverting input 43 FINR IN/OUT X Input for FOUTR or filter op amp output (line out) 44 VREF IN X Analog reference Ground Micronas Type Connection Short Description (if not used) 11 DAC 3550A 3.3. Pin Descriptions 3.3.1. Power Supply Pins The DAC 3550A combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD (18) VSS (17) The VDD and VSS power supply pair are connected internally with all digital parts of the DAC 3550A. AVDD0 (9) AVSS0 (3) AVDD0 and AVSS0 are separate power supply pins that are exclusively used for the on-chip headphone/ loudspeaker amplifiers. AVDD1 (10) AVSS1 (2) The AVDD1 and AVSS1 pins supply the analog audio processing parts, except for the headphone/loudspeaker amplifiers. 3.3.2. Analog Audio Pins AGNDC (1) Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against VREF with a 3.3 µF capacitor. Note: The pin has a typical DC-level of 1.5/2.25 V. It can be used as reference input for external op amps when no current load is applied. VREF (44) Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential. Any external distortions on this pin will affect the analog performance of the DAC 3550A. AUX1L (31) AUX1R (32) AUX2L (29) AUX2R (30) The AUX pins provide two analog stereo inputs. Auxiliary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected with these inputs. The input signals have to be connected by capacitive coupling. FOUTL (37) FOPL (38) FINL (39) FOUTR (41) FOPR (42) FINR (43) Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R-pins are directly connected with the inverting inputs of the filter op amps. The FINL/R pins are connected with the outputs of the op amps. The driving capability of the FOUTL/R pins is not sufficient for standard line output signals. Only the FINL/R pins are suitable for line output. OUTL (5) OUTR (7) The OUTL/R pins are connected to the internal output amplifiers. They can be used for either stereo headphones or a mono loudspeaker. The signal of the right channel amplifier can be inverted for mono loudspeaker operation. Caution: A short circuit at these pins for more than a momentary period may result in destruction of the internal circuits. 3.3.3. Oscillator and Clock Pins XTI (12) XTO (13) The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram). CLKOUT (14) The CLKOUT pin provides a buffered output of the crystal oscillator. Caution: Power dissipation limit may be exceeded in case of short to VSS or VDD. CLI (23) DAI (24) WSI (25) These three pins are inputs for the digital audio data DAI, frame indication signal WSI, and bit clock CLI. The digital audio data is transmitted in an I2S-compatible format. Audio word lengths of 16 and 32 bits are supported, as well as SONY and Philips I2S protocol. SCL (15) SDA (16) SCL (serial clock) and SDA (serial data) provide the connection to the serial control interface (I2C). 12 Micronas DAC 3550A 3.3.4. Other Pins 3.4. Pin Configuration TESTEN (27) Test enable. This pin is for test purposes only and must always be connected to VSS. NC AUX2L TESTEN AUX2R PORQ (26) This pin may be used to reset the chip. If not used, this pin must be connected to VDD. DEEML (34) DEEMR (35) These pins connect an external analog deemphasis network to the signal path in the analog back-end. This connection can be switched on and off by an internal switch which is controlled either by I2C or the DEECTRL-pin. DEECTRL (21) If no I2C-control is used, deemphasis can be switched on and off with this pin. WSI AUX1R DAI NC CLI 33 32 31 30 29 28 27 26 25 24 23 DEEML 34 22 NC DEEMR 35 21 DEECTRL NC 36 20 MCS2 FOUTL 37 19 MCS1 FOPL 38 18 VDD FINL 39 17 VSS NC 40 16 SDA FOUTR 41 15 SCL FOPR 42 14 CLKOUT FINR 43 13 XTO VREF 44 12 XTI DAC 3550A 1 MCS1 (19) MCS2 (20) Mode select pins to select MPEG, Standard Mode, and I2C subaddress. PORQ AUX1L 2 3 4 5 6 7 8 9 10 11 AGNDC NC AVSS1 AVDD1 AVSS0 AVDD0 NC NC OUTL OUTR NC Fig. 3–2: 44-pin PMQFP package Micronas 13 DAC 3550A 3.5. Pin Circuits VDD FOUTn AGNDC N VSS Fig. 3–8: Output Pins FOUTL, FOUTR Fig. 3–3: Input/Output Pins SDA, SCL XTO 500 k Fig. 3–4: Input Pins DAI, WSI, PORQ, CLI XTI Fig. 3–9: Input/Output Pins XTI, XTO VDD P sel/nonsel AUXnL N VSS mono/stereo AGNDC Fig. 3–5: Output Pin CLKOUT AGNDC mono/stereo ext. filter network FOUTn DEEM FOPn AUXnR sel/nonsel FINn Fig. 3–10: Input Pins AUX1R, AUX1L, AUX2R, AUX2L, AGNDC (DEEMCTRL) AGNDC Fig. 3–6: Pins FINR, FOPR, FINL, FOPL, DEEML, DEEMR OUTn AGNDC Fig. 3–11: Output Pins OUTL, OUTR AGNDC 125 k VDD VREF AVSS0/1 VSS Fig. 3–7: Pins AGNDC, VREF Fig. 3–12: Input Pins MCS1, MCS2, DEECTRL 14 Micronas DAC 3550A 3.6. Control Registers I2C Subaddress (hex) Number of Bits Mode Function Default Values (hex) Name SAMPLE RATE CONTROL SR_REG 01 8 w sample rate control 0H bit[7:5] not used, set to 0 bit[4] L/R-bit 0 (WSI = 0 → left channel)1) 1 (WSI = 0 → right channel)1) LR_SEL bit[3] Delay-Bit 0 No Delay 1 1 bit Delay SP_SEL bit[2:0] sample rate control 000 32−48 kHz 001 26−32 kHz 010 20−26 kHz 011 14−20 kHz 100 10−14 kHz 101 8−10 kHz 11x2) autoselect SRC_48 SRC_32 SRC_24 SRC_16 SRC_12 SRC_8 SRC_A ANALOG VOLUME AVOL 02 16 w audio volume control bit[15] not used, set to 0 bit[14] deemphasis on/off 0 deemphasis off 1 deemphasis on bit[13:8] analog audio volume level left: 000000 mute −75 dB 000001 101100 +0 dB (default) 111000 +18 dB bit[7:6] not used, set to 0 bit[5:0] analog audio volume level right 000000 mute −75 dB 000001 101100 +0 dB (default) 111000 +18 dB 1) see Fig. 2–1 and Fig. 2–2 on page 5 2) don’t care Micronas 2C2CH DEEM AVOL_L AVOL_R 15 DAC 3550A I2C Subaddress (hex) Number of Bits Mode Function Default Values (hex) Name Global Configuration GCFG 03 16 8 w global configuration 4H bit[7] not used, set to 0 bit[6] select 3V-5 V mode 0 3V 1 5V SEL_53V bit[5] power-mode 0 normal 1 low power PWMD bit[4] AUX2 select 0 AUX2 off 1 AUX2 on INSEL_AUX2 bit[3] AUX1 select 0 AUX1 off 1 AUX1 on INSEL_AUX1 bit[2] DAC select 0 DAC off 1 DAC on (default) INSEL_DAC bit[1] aux-mono/stereo 0 stereo 1 mono AUX_MS bit[0] invert right power amplifier 0 not inverted 1 inverted IRPA Micronas DAC 3550A 3.7. Electrical Characteristics 3.7.1. Absolute Maximum Ratings Symbol Parameter TA Min. Max. Unit Ambient Operating Temperature1) 0 70 °C TS Storage Temperature −40 125 °C Pmax Power Dissipation 500 mW VSUPA Analog Supply Voltage2) AVDD0/1 −0.3 6 V VSUPD Digital Supply Voltage VDD −0.3 6 V VIdig1 Input Voltage, digital inputs MCS1, MCS2, DEECTRL −0.3 VSUPD + 0.3 V VIdig2 Input Voltage, digital inputs WSI, CLI, DAI, PORQ, SCL, SDA −0.3 6 V IIdig Input Current, all digital inputs −5 +5 mA VIana Input Voltage, all analog inputs −0.3 VSUPA + 0.3 V IIana Input Current, all analog inputs −5 +5 mA IOaudio Output Current, audio output3) −0.2 0.2 A IOdig Output Current, all digital outputs4) −10 10 mA 1) 2) 3) 4) Pin Name OUTL/R =standard temperature range, DAC 3550A tested in extended temperature range on request Both have to be connected together! These pins are NOT short-circuit proof! Total chip power dissipation must not exceed absolute maximum rating Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Micronas 17 DAC 3550A 3.7.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit 70 °C Temperature Ranges and Supply Voltages TA Ambient Temperature Range1) VSUPA1 Analog Audio Supply Voltage AVDD0/1 3.02) 3.3 5.5 V VSUPD Digital Supply Voltage VDD 2.7 3.3 5.5 V AVDD0/1 VSUPD −0.25 V 1.0 0 Relative Supply Voltages VSUPA Analog Audio Supply Voltage in relation to the Digital Supply Voltage 5.5 V Analog Reference 3.3 µF AGNDC 10 nF CAGNDC1 Analog Reference Capacitor AGNDC CAGNDC2 Analog Reference Capacitor Analog Audio Inputs VAI Analog Input Voltage AC, SEL_53V = 0 AUXnL/R3) 0.35 0.7 Vrms VAI Analog Input Voltage AC, SEL_53V = 1 AUXnL/R3) 0.525 1.05 Vrms 6 kΩ pF 7.5 kΩ pF 1.0 kΩ nF Analog Filter Input and Output ZAFLO ZAFLI Analog Filter Load Output4) Analog Filter Load Input4) FOUTL/R FINL/R 7.5 5.0 Analog Audio Output Audio Line Output5) (680 Ω Series Resistor required) FINL/R ZAOL_HP Analog Output Load HP (47 Ω Series Resistor required) OUTL/R 32 400 Ω pF ZAOL_SP Analog Output Load SP (bridged) OUTL/R 32 50 Ω pF 16 100 Ω pF ZLO Analog Output Load SP (Stereo) 1) 2) 3) 4) 5) 18 10 =standard temperature range, DAC 3550A tested in extended temperature range on request typically operable down to 2.7 V, without loss in performance n = 1 or 2 Please refer to Section 4.2. “Recommended Low-Pass Filters for Analog Outputs” on page 25. Please refer to Section 4.1. “Line Output Details” on page 25. Micronas DAC 3550A Symbol Parameter Pin Name fI2C1 I2C Clock Frequency, I2S active SCL fI2C2 I2C Clock Frequency, I2S inactive Min. Typ. Max. Unit I2C Input 400 kHz 100 kHz Digital Inputs VIH Input High Voltage VIL Input Low Voltage CLI, WSI, DAI, PORQ, SCL, SDA 0.5× VDD V 0.2× VDD V 14.725 17 MHz Quartz Characteristics FP Load Resonance Frequency at Cl = 20 pF REQ Equivalent Series Resistance 12 30 Ω C0 Shunt (parallel) Capacitance 3 5 pF 50 pF 13.3 Load at CLKOUT Output Cload 1) 2) 3) 4) 5) Capacitance CLKOUT 0 =standard temperature range, DAC 3550A tested in extended temperature range on request typically operable down to 2.7 V, without loss in performance n = 1 or 2 Please refer to Section 4.2. “Recommended Low-Pass Filters for Analog Outputs” on page 25. Please refer to Section 4.1. “Line Output Details” on page 25. Micronas 19 DAC 3550A 3.7.3. Characteristics At TA = 0 to 70 °C*, VSUPD = 2.7 to 5.5 V, VSUPA = 3.0 to 5.5 V; typical values at TJ = 27 °C, VSUPD = VSUPA = 3.3 V, quartz frequency = 14.725 MHz, duty cycle = 50 %, positive current flows into the IC Symbol Parameter Pin Name IVDD Current Consumption VDD IVDD Current Consumption VDD Min. Typ. Max. Unit Test Conditions 5 mA VSUPD =3 V 8 mA VSUPD =5 V µA VGND ≤ VI ≤ VSUP V no load at output Digital Supply Digital Input Pin – Leakage II Input Leakage Current ±1 CLI, WSI, DAI, TESTEN, PORQ, DEECTRL, MCS1/2 Digital Output Pin – Clock Out VOH Output High Voltage VOL Output Low Voltage CLKOUT VSUPD − 0.3 0.3 V 60 Ω Iload = 5 mA, VSUPD = 2.7 V 8 1.5 11 mA mA PWMD = 0, Mute PWMD = 1, Mute 11 2 15 mA mA PWMD = 0, Mute PWMD = 1, Mute 50 dB 1 kHz sine at 100 mVrms 20 dB ≤ 100 kHz sine at 100 mVrms 50 dB 1 kHz sine at 100 mVrms 40 dB ≤ 100 kHz sine at 100 mVrms I2C Bus Ron Output Impedance SCL, SDA Analog Supply IAVDD Current Consumption Analog Audio, SEL_53V = 0 AVDD0/1 SEL_53V = 1 PSRRAA PSRRLO Power Supply Rejection Ratio for Analog Audio Output Power Supply Rejection Ratio for Line Output AVDD0/1, OUTL/R AVDD0/1, FINL/R Reference Frequency Generation VDCXTI DC Voltage at Oscillator Pins XTI/O 0.5 * VSUPA V CLI Input Capacitance at Oscillator Pin XTI/O 3 pF Vxtalout Voltage Swing at Oscillator Pins, pp XTI/O Oscillator Start-Up Time 60 100 % VSUPA 50 ms AVDD/VDD ≥ 2.5 V * =standard temperature range, DAC 3550A tested in extended temperature range on request 20 Micronas DAC 3550A Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Output Voltage AC OUTL/R, FOUTL/R, FINL/R 0.65 0.7 0.75 Vrms SEL_53V = 0, RL > 5 kΩ, Analog Gain = 0 dB Input = 0 dBFS digital 1.0 1.05 1.1 Vrms SEL_53V = 1 −0.5 0 0.5 dB f = 1 kHz, sine wave, RL > 5 kΩ 0.5 Vrms to AUXnL/R 5 mW SEL_53V = 0, RL = 32 Ω, Analog Gain = +3 dB, distortion < 1%, external 47 Ω series resistor required 12 mW SEL_53V = 1 120 mW RL = 32 Ω (bridged), Analog Gain = +3 dB, distortion < 10%, SEL_53V = 0, IRPA = 1 280 mW SEL_53V = 1 Analog Audio VAO GAUX Gain from Auxiliary Inputs to Line Outputs AUXnL/R, FINL/R PHP Output Power (Headphone) OUTL/R PSP Output Power (Speaker) OUTL/R −75 GAO Analog Output Gain Setting Range OUTL/R dGAO1 Analog Output Gain Step Size OUTL/R 3.0 dB dGAO2 Analog Output Gain Step Size OUTL/R 1.5 dB EGA1 Analog Output Gain Error OUTL/R −2 2 dB −46.5 dB ≥ Analog Gain ≥−54 dB EGA2 Analog Output Gain Error OUTL/R −1 1 dB −40.5 dB ≥ Analog Gain ≥−45 dB EGA3 Analog Output Gain Error OUTL/R −0.5 0.5 dB +18 dB ≥ Analog Gain ≥−39 dB EdGA Analog Output Gain Step Size Error OUTL/R −0.5 0.5 dB +18 dB ≥ Analog Gain ≥−48 dB SNRAUX Signal-to-Noise Ratio from Analog Input to Line Output AUXn, FINL/R 98 dB Signal-to-Noise Ratio from Analog Input to Headphone Output AUXn, OUTn 93 dB SEL_53V = 0: input −40 dB below 0.7 Vrms Analog Gain = 0 dB, BW =20 Hz...20 kHz unweighted Micronas 18 dB Analog Gain: −75 dB...−54 dB Analog Gain: −54 dB...+18 dB 21 DAC 3550A Symbol Parameter Pin Name Min. Typ. SNR1 Signal-to-Noise Ratio OUTL/R 89 FINL/R 90 Max. Unit Test Conditions 91 dB RL ≥ 32 Ω (external 47 Ω series resistor required) BW =20 Hz...0.5 fs unweighted, Analog Gain = 0 dB, Input = −20 dBFS 92 dB RL ≥ 5 kΩ, Rdec ≥ 612 Ω BW etc. as above 16 bit I2S, SEL_53V = 0 94 dB 32 bit I2S, SEL_53V = 0 96 dB 16 bit I2S, SEL_53V = 1 98 dB 32 bit I2S, SEL_53V = 1 103 dBA 32 bit I2S, SEL_53V = 1 62 dB RL ≥ 32 Ω (external 47 Ω series resistor required) BW = 20 Hz..0.5 fs unweighted Analog Gain= −40.5 dB, Input = −3 dBFS SNR2 Signal-to-Noise Ratio OUTL/R LevMute Mute Level OUTL/R −110 dBV BW = 20 Hz...22 kHz unweighted, no digital input signal, Analog Gain = Mute RD/A D/A Pass Band Ripple OUTL/R, FOUTL/R −0.1 dB 0...0.446 fs (no external filters used) AD/A D/A Stop Band Attenuation 40 dB 0.55...7.533 fs (no external filters used) BWAUX Bandwidth for Auxiliary Inputs AUXnL/R, FINL/R 760 kHz (no external filters used) THDALO Total Harmonic Distortion from Auxiliary Inputs to Line Outputs AUXnL/R, FINL/R 0.01 % BW = 20 Hz...22 kHz, unweighted, RL > 5 kΩ Input 1 kHz at 0.5 Vrms Rdec ≥ 612 Ω THDDLO Total Harmonic Distortion (D/A converter to Line Output) FINL/R 0.01 % BW = 20 Hz...0.5 fs, unweighted, RL > 5 kΩ Input 1 kHz at −3 dBFS Rdec ≥ 612 Ω THDHP Total Harmonic Distortion (Headphone) OUTL/R 0.05 % BW = 20 Hz...0.5 fs, unweighted, RL ≥ 32 Ω (47 Ω series resistor required), Analog Gain = 0 dB, Input 1 kHz at −3 dBFS 22 58 Micronas DAC 3550A Symbol Parameter Pin Name THDSP Total Harmonic Distortion (Speaker) OUTL/R XTALKLO Cross-Talk Left/Right Channel (Line Output) AUXnL/R, FOUTL/R, FINL/R −70 XTALKHP Crosstalk Left/Right Channel (Headphone) OUTL/R XTALK2 Crosstalk between Input Signal Pairs AUXnL/R VAGNDC Analog Reference Voltage AGNDC Micronas Min. Typ. Max. Unit Test Conditions 0.5 % BW = 20 Hz...0.5 fs, unweighted, RL ≥ 32 Ω (speaker bridged), Analog Gain = 0 dB, Input 1 kHz at −3 dBFS −80 dB f = 1 kHz, sine wave, RL > 7.5 kΩ Analog Gain = 0 dB, Input = −3 dBFS or 0.5 Vrms to AUXnL/R −70 −80 dB f = 1 kHz, sine wave, OUTL/R: RL ≥ 32 Ω (47 Ω series resistor required) Analog Gain = 0 dB, Input = −3 dBFS or 0.5 Vrms to AUXnL/R −70 −80 dB f = 1 kHz, sine wave, FOUTL/R: RL > 7.5 kΩ OUTL/R: RL ≥ 32 Ω (47 Ω series resistor required) Analog Gain = 0 dB, Input = −3 dBFS and 0.5 Vrms to AUXnL/R 1.5 V SEL_53V = 0 RL >> 10 MΩ, referred to VREF 2.25 V SEL_53V = 1 RL >> 10 MΩ, referred to VREF 23 DAC 3550A Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions RIAUX Input Resistance at Input Pins AUXnL/R 12.1 11.6 15 17.9 19.0 kΩ kΩ TJ = 27 °C TA = 0 to 70 °C1) Input selected, PWMD = 0 i = ± 10 µA, referred to VREF 24.2 23.3 30 35.8 37.9 kΩ kΩ TJ = 27 °C TA = 0 to 70 °C1) Input not selected i = ± 10 µA, referred to VREF ROOUT Output Resistance at Output Pins OUTL/R 700 Ω TJ = 27 °C PWMD = 1 i = ± 200 µA, referred to VREF ROFILT Output Resistance of Filter Pins FINL 15 kΩ FINR 11.25 kΩ PWMD = 1, Mute i = ± 10 µA, referred to VREF VOffI Offset Voltage at Input Pins AUXnL/R −20 20 mV referred to AGNDC VOffO Offset Voltage at Output Pins OUTL/R −10 10 mV Mute referred to AGNDC VOffFO Offset Voltage at Filter Output Pins FOUTL/R −20 20 mV PWMD = 0, referred to AGNDC VOffFI Offset Voltage at Filter Input Pins FINL/R −20 20 mV PWMD = 0, referred to AGNDC dVDCPD Difference of DC Voltage at Output Pins after Back-end Low Power Sequence OUTL/R −10 10 mV Analog Gain = Mute, PWMD switched from 0 to 1 24 Micronas DAC 3550A 4. Applications 11 kΩ 2nd-order 4.1. Line Output Details 11 kΩ 11 kΩ Rdec 220 pF 1.0 nF FINL(R) Cline Rin AVSS FOUTL(R) FOPL(R) FINL(R) AVSS - Fig. 4–1: Use of FINL/R as Line Outputs Table 4–1: Load at FINL/R when used as Line Output for external amplifier Fig. 4–3: 2nd-order low-pass filter Table 4–3: Attenuation of 2nd-order low-pass filter Filter Order Rdec Rin 1st, 2nd, 3rd 680 Ω > 10 kΩ Rdec:Resistor used for decoupling Cline from FINL(R) to achieve stability Frequency Gain 24 kHz −1.5 dB 30 kHz −3.0 dB Cline: Capacitive load according to e.g. cable, amplifier Rin: Input resistance of amplifier 3rd-order 7.5 kΩ 4.2. Recommended Low-Pass Filters for Analog Outputs* 1st-order 7.5 kΩ 1.8 nF 7.5 kΩ 120 pF 1.8 nF AVSS 330 pF 15 kΩ 15 kΩ FOUTL(R) 15 kΩ FOPL(R) FINL(R) - FOUTL(R) FOPL(R) FINL(R) Fig. 4–4: 3rd-order low-pass filter - Table 4–4: Attenuation of 3rd-order low-pass filter Fig. 4–2: 1st-order low-pass filter Table 4–2: Attenuation of 1st-order low-pass filter Frequency Gain 24 kHz −2.2 dB 30 kHz −3.0 dB Frequency Gain 18 kHz 0.17 dB 24 kHz −0.23 dB 30 kHz −3.00 dB * without deemphasis circuit Micronas 25 DAC 3550A 4.3. Recommendations for Filters and Deemphasis 4.4. Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass R3 R1 R1 R2 R4 C3 R5 R2 R3 R4 C1 C2 ON C1 R5 C4 OFF C2 C3 AVSS FOUTL(R) FOPL(R) FINL(R) DEEML(R) FOUTL(R) FINL(R) FOPL(R) - - Fig. 4–5: General circuit schematic Fig. 4–6: General circuit schematic Table 4–5: Resistor and Capacitor values Table 4–6: Resistor and Capacitor values 1st order 2nd order 3rd order DC-Gain = 10 dB fc1 = 100 Hz fc2 = 330 Hz R1 (kΩ) 0 7.5 C1 (pF) open 560 R1 (kΩ) 13 R2 (kΩ) 18 11 7.5 C1 (nF) 47 C2 (pF) open 1000 270 R2 (kΩ) 0 R3 (kΩ) 18 11 15 R3 (kΩ) 15 C3 (pF) 180 180 82 R4 (kΩ) 15 R4 (kΩ) 0 11 7.5 R5 (kΩ) 13 R5 (kΩ) 18 22 22 C2 (nF) 47 C4 (nF) 1.8 1.0 1.0 C3 (pF) 180 26 Micronas DAC 3550A 4.5. Power-up/down Sequence 4.5.2. Power-down Sequence In order to get a click-free power-up/down characteristic, it is recommended to use the following sequences: 1. Stop I2S data. 2. Send I2C: LOW POWER. 3. Switch VDD, AVDD0/1 to 0. 4.5.1. Power-up Sequence 1. Start VDD from 0 to +3.3 V and start AVDD0/1 from 0 to +3.3 V/+5 V. AVDD should not ramp up faster than VDD. 2. Release PORQ from 0 to AVDD0/1. 3. Send I2C: volume, input select, speaker, ... optional. 4. Start I2S data. The most important point is: PORQ has to ramp up after AVDD0/1, simply by using a 10-kΩ pull-up resistor to AVDD0/1 and a 2.2-nF capacitor to ground. No further control on PORQ is needed. VDD ≥90% VDD AVDD ≥90% AVDD PORQ 0.7 × AVDD <0.2 × VDD <30 ms Fig. 4–7: Power-up sequence Micronas 27 DAC 3550A 4.6. Typical Applications n 28 Micronas Fig. 4–8: Application circuit schematic 1: Standard application with analog deemphasis. Oscillator not needed. A n A Micronas 29 DAC 3550A Fig. 4–9: Application circuit schematic 2: MPEG application with analog Megabass and 14.725 MHz crystal A DAC 3550A demand signal Host (PC, Controller) I2S MAS MPEG clock 3507D MPEG bit stream line out DAC 3550A 14.725 MHz ROM, CD-ROM, CLKOUT RAM, Flash Mem. .. Fig. 4–10: MPEG Layer-3 Player FM-TUNER DEMOD L I2S DSP & SERVO Optical Pickup R DAC DAC 3550A 3550A line out 384 × fs CLKOUT Fig. 4–11: CD-Player with FM-Radio TUNER ADRBUS 18.432 MHz MSP 34xx DATA BCLK LRCLK I2S DRP 3510 A DAC DAC 3550A 3550A line-out 32 kHz 18.432 MHz Fig. 4–12: ADR Receiver 30 Micronas DAC 3550A Micronas 31 DAC 3550A 5. Data Sheet History 1. Final data sheet: “DAC 3550A Stereo Audio DAC, Edition July 23, 1999, 6251-467-1DS. First release of the final data sheet. Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com Printed in Germany Order No. 6251-467-1DS 32 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Micronas DAC 3550A Preliminary Data Sheet Supplement Subject: New Package for DAC 3550A Data Sheet Concerned: DAC 3550A 6251-467-1PD, Edition April 23, 1999 Supplement: No. 2/ 6251-467-1PDS Edition: May 18, 1999 New Package for DAC 3550A: 49-Ball Plastic Ball Grid Array (PBGA49) 1. Outline Dimensions D0026/1E Fig. 1: 49-Ball Plastic Ball Grid Array (PBGA49) Dimensions in mm MICRONAS INTERMETALL page 1 of 3 DAC 3550A PRELIMINARY DATA SHEET SUPPLEMENT 2. Pin Connections and Short Descriptions NC = not connected, leave vacant X = obligatory; connect as described in application circuit diagram LV = if not used, leave vacant VSS = if not used, connect to VSS VDD = connect to VDD Unassigned pins must be left vacant. Pin No. / Pin ID Pin Name Type Connection Short Description (If not used) PMQFP 44-pin PBGA 49-ball 1 B5 AGNDC BID X Analog reference voltage 2 A6 AVSS1 SUPPLY X VSS 1 for audio back-end 3 B4 AVSS0 SUPPLY X VSS 0 for audio output amplifiers LV Not connected LV Audio output: headphone left or speaker + LV Not connected LV Audio output: headphone right or Speaker − LV Not connected 4 5 NC C4 6 7 OUTL OUT NC A3 8 OUTR OUT NC 9 A2 AVDD0 SUPPLY X VDD 0 for audio output amplifiers 10 A1 AVDD1 SUPPLY X VDD 1 for audio back-end LV Not connected 11 NC 12 C3 XTI IN X Quartz oscillator pin 1 13 C2 XTO BID X Quartz oscillator pin 2 14 D2 CLKOUT OUT LV Clock output 15 C1 SCL BID LV I2C clock 16 D3 SDA BID LV I2C data 17 D1 VSS SUPPLY X Digital VSS 18 E1 VDD SUPPLY X Digital VDD 19 F2 MCS1 IN X I2C chip sSelect 1 20 F1 MCS2 IN X I2C chip select 2 21 G1 DEECTRL IN VSS Deemphasis on/off control NC LV Not connected VSS I2S bit clock 22 23 E3 CLI 24 F3 DAI IN VSS I2S data 25 F4 WSI IN VSS I2S frame identification 26 G4 PORQ IN VDD Power-on-reset, active-low page 2 of 3 MICRONAS INTERMETALL DAC 3550A PRELIMINARY DATA SHEET SUPPLEMENT Pin No. / Pin ID PMQFP 44-pin PBGA 49-ball 27 F5 28 Pin Name Type Connection Short Description (If not used) TESTEN IN NC X Test enable LV Not connected 29 G5 AUX2L IN LV AUX2 left input for external analog signals (e.g. tape) 30 F6 AUX2R IN LV AUX2 right input for external analog signals (e.g. tape) 31 G6 AUX1L IN LV AUX1 left input for external analog signals (e.g. FM) 32 G7 AUX1R IN LV AUX1 right input for external analog signals (e.g. FM) LV Not connected 33 NC 34 E5 DEEML OUT LV Deemphasis network, left 35 E6 DEEMR OUT LV Deemphasis network, right LV Not connected 36 NC 37 F7 FOUTL OUT X Output to left external filter 38 D6 FOPL BID X Filter op amp inverting input, left 39 E7 FINL IN/OUT X Input for FOUTL or filter op amp output (line out) LV Not connected 40 NC 41 D7 FOUTR OUT X Output to right external filter 42 C6 FOPR BID X Right filter op amp inverting input 43 C7 FINR IN/OUT X Input for FOUTR or filter op amp output (line out) 44 A7 VREF IN X Analog reference ground MICRONAS INTERMETALL page 3 of 3