DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 1.8 V to 5.5 V, 80 µA, 8 BIT, LOW POWER, SINGLE CHANNEL, DIGITAL-TO-ANALOG CONVERTER FEATURES 1 • • • • • • • • 234 • • • Qualified for Automotive Applications Relative Accuracy: 0.25 LSB INL Micro-Power Operation: 80 µA at 1.8 V Power-Down: 0.5 µA at 5 V, 0.1 µA at 1.8 V Wide Power Supply: 1.8 V to 5.5 V Power-On Reset to Zero Scale Straight Binary Data Format Low Power Serial Interface With Schmitt-Triggered Inputs: Up to 50 MHz On-Chip Output Buffer Amplifier, Rail-to-Rail Operation SYNC Interrupt Facility Tiny 6-Pin SC70 Package RELATED DEVICES Pin and Function Compatible 16-BIT 14-BIT 12-BIT 10-BIT 8-BIT DAC8411 DAC8311 DAC7311 DAC6311 DAC5311 AVDD GND Power-On Reset REF(+) DAC Register 8-/10-/12-Bit DAC Input Control Logic Output Buffer Power-Down Control Logic VOUT Resistor Network APPLICATIONS • • • • Portable, Battery-Powered instruments Process Control Digital Gain and Offset Adjustment Programmable Voltage and Current Sources SYNC SCLK DIN DESCRIPTION The DAC5311 is an 8-bit, low-power, single-channel, voltage output, digital-to-analog converters (DAC). It is monotonic by design and provides excellent linearity and minimizes undesired code-to-code transient voltages while offering an easy upgrade path within a pin-compatible family. The device uses a versatile, 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI™, QSPI™, MICROWIRE™, and digital signal processor (DSP) interfaces. DAC5311 uses an external power supply as a reference voltage to set the output range. The devices incorporate a power-on reset (POR) circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the device occurs. It contains a power-down feature, accessed over the serial interface, that reduces current consumption of the device to 0.1 µA at 1.8 V in power-down mode. The low power consumption of this part in normal operation makes it ideally suited for portable battery-operated equipment. The power consumption is 0.55 mW at 5 V, reducing to 2.5 µW in power-down mode. DAC5311 is pin-compatible with the DAC8311 and DAC8411, offering an easy upgrade path from 8-bit resolution to 14- and 16-bit resolution. The device is available in a small 6-pin SC70 package. This package offers a flexible solution over the automotive temperature range of –40°C to 85°C. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) –40°C to 85°C ±0.25 ±0.25 (1) (2) PACKAGE (2) SC70-6 – DCK Reel of 3000 ORDERABLE PART NUMBER DAC5311IDCKRQ1 PACKAGE MARKING OCZ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) AVDD to GND –0.3 V to 6 V Digital input voltage to GND –0.3 V to AVDD +0.3 V AVOUT to GND –0.3 V to AVDD +0.3 V Operating temperature range –40°C to 85°C Storage temperature range –65°C to 150°C Junction temperature (TJ max) 150°C Power dissipation (TJ max – TA)/θJA W θJA thermal impedance (1) 2 250°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 ELECTRICAL CHARACTERISTICS At AVDD = 1.8 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (1) Resolution Relative accuracy 8 Measured by the line passing through codes 3 and 252 Differential nonlinearity Offset error Measured by the line passing through two codes (2) Offset error drift ±0.01 ±0.25 LSB ±0.01 ±0.25 LSB ±0.05 ±4 mV µV/°C 3 Zero code error All zeros loaded to the DAC register Full-scale error All ones loaded to DAC register 0.2 Gain error Gain temperature coefficient Bits mV 0.04 0.2 % of FSR 0.05 ±0.15 % of FSR AVDD = 5 V ±0.5 AVDD = 1.8 V ±1.5 ppm of FSR/°C OUTPUT CHARACTERISTICS (3) Output voltage range Output voltage settling time 0 RL = 2 kΩ, CL = 200 pF, AVDD = 5 V, 1/4 scale to 3/4 scale RL = 2 MΩ, CL = 470 pF Slew rate Capacitive load stability Code change glitch impulse RL = ∞ RL = 2 kΩ 1-LSB change around major carry Digital feed through Power-on glitch impulse RL = 2 kΩ, CL = 200 pF, AVDD = 5 V Power-up time V 10 µs 12 µs 0.7 V/µs 470 pF 1000 pF 0.5 nV-s 0.5 nV-s 17 mV 0.5 Ω AVDD = 5 V 50 mA AVDD = 3 V 20 mA Coming out of power-down mode 50 µs DC output impedance Short-circuit current 6 AVDD AC PERFORMANCE SNR THD SFDR TA= 25°C, BW = 20 kHz, 12-bit level, AVDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation SINAD DAC output noise density (4) DAC output noise (5) (1) (2) (3) (4) (5) 81 dB –65 dB 65 dB 65 dB TA= 25°C, at zero-scale input, fOUT = 1 kHz, AVDD = 5 V 17 nV/√Hz TA= 25°C, at mid-code input, fOUT = 1 kHz, AVDD = 5 V 110 nV/√Hz TA= 25°C, at mid-code input, 0.1 Hz to 10 Hz, AVDD = 5 V 3 µVPP Linearity calculated using a reduced code range of 3 to 252, output unloaded. Straight line passing through codes 3 and 252, output unloaded. Specified by design and characterization, not production tested. For more details, see Figure 16. For more details, see Figure 17. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 3 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 1.8 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUTS (6) ±1 µA AVDD = 5 V 0.8 V AVDD = 1.8 V 0.5 V Input current VINL, input low voltage VINH, input high voltage AVDD = 5 V 1.8 AVDD = 1.8 V 1.1 Pin capacitance V V 1.5 3 pF 5.5 V AVDD = 3.6 V to 5.5 V 110 160 AVDD = 2.7 V to 3.6 V 95 150 AVDD = 1.8 V to 2.7 V 80 140 AVDD = 3.6 V to 5.5 V 0.5 3.5 AVDD = 2.7 V to 3.6 V 0.4 3.0 AVDD = 1.8 V to 2.7 V 0.1 2.0 AVDD = 3.6 V to 5.5 V 0.55 0.88 AVDD = 2.7 V to 3.6 V 0.25 0.54 AVDD = 1.8 V to 2.7 V 0.14 0.38 AVDD = 3.6 V to 5.5 V 2.50 19.2 AVDD = 2.7 V to 3.6 V 1.08 10.8 AVDD = 1.8 V to 2.7 V 0.72 8.1 POWER REQUIREMENTS AVDD 1.8 Normal mode VINH = AVDD and VINL = GND, at midscale code (7) IDD Power-down mode Normal mode VINH = AVDD and VINL = GND, at midscale code VINH = AVDD and VINL = GND, at midscale code Power dissipation Power-down mode VINH = AVDD and VINL = GND, at midscale code µA µA mW µW TEMPERATURE RANGE Specified performance range (6) (7) 4 –40 85 °C Specified by design and characterization, not production tested. For more details, see Figure 9, Figure 44, and Figure 69. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 PIN CONFIGURATION DCK PACKAGE SC70-6 (TOP VIEW) SYNC 1 6 VOUT SCLK 2 5 GND DIN 3 4 AVDD/VREF Table 1. PIN DESCRIPTION PIN NAME DESCRIPTION 1 SYNC Level-triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC5311. See the SYNC Interrupt section for more details. 2 SCLK Serial clock input. Data can be transferred at rates up to 50 MHz. 3 DIN 4 AVDD/VREF 5 GND Ground reference point for all circuitry on the part. 6 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Serial data input. Data is clocked into the 16-bit input shift register on the falling edge of the serial clock input. Power supply input, 1.8 V to 5.5 V. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 5 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com SERIAL WRITE OPERATION t9 t1 SCLK 1 16 t8 t2 t3 t4 t7 SYNC t10 t6 t5 DB15 DIN DB15 DB0 TIMING REQUIREMENTS (1) All specifications at –40°C to 85°C, AVDD = 1.8 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS t1 (2) SCLK cycle time t2 SCLK high time t3 SCLK low time t4 SYNC to SCLK rising edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC high time t9 16th SCLK falling edge to SYNC falling edge t10 SYNC rising edge to 16th SCLK falling edge (for successful SYNC interrupt) (1) (2) 6 MIN AVDD = 1.8 V to 3.6 V 50 AVDD = 3.6 V to 5.5 V 20 AVDD = 1.8 V to 3.6 V 25 AVDD = 3.6 V to 5.5 V 10 AVDD = 1.8 V to 3.6 V 25 AVDD = 3.6 V to 5.5 V 10 AVDD = 1.8 V to 3.6 V 0 AVDD = 3.6 V to 5.5 V 0 AVDD = 1.8 V to 3.6 V 5 AVDD = 3.6 V to 5.5 V 5 AVDD = 1.8 V to 3.6 V 4.5 AVDD = 3.6 V to 5.5 V 4.5 AVDD = 1.8 V to 3.6 V 0 AVDD = 3.6 V to 5.5 V 0 AVDD = 1.8 V to 3.6 V 50 AVDD = 3.6 V to 5.5 V 20 AVDD = 1.8 V to 3.6 V 100 AVDD = 3.6 V to 5.5 V 100 AVDD = 1.8 V to 3.6 V 15 AVDD = 3.6 V to 5.5 V 15 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 50 MHz at AVDD = 3.6 V to 5.5 V and 20 MHz at AVDD = 1.8 V to 3.6 V. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 5 V At TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted) DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 0.4 AVDD = 5V 0.01 AVDD = 5V 0 Zero-Code Error (mV) LE (LSB) 0.02 -0.01 -0.02 0.02 DLE (LSB) ZERO-CODE ERROR vs TEMPERATURE 0.01 0 0 64 96 128 160 192 224 0 -40 -25 -10 256 5 20 35 50 65 Temperature (°C) Figure 1. Figure 2. DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (25°C) OFFSET ERROR vs TEMPERATURE 80 95 110 125 80 95 110 125 80 95 110 125 0.6 AVDD = 5V 0.01 AVDD = 5V 0.4 0 Offset Error (mV) LE (LSB) 32 -0.01 -0.02 0.02 DLE (LSB) 0.1 Digital Input Code 0.02 0.01 0.2 0 -0.2 0 -0.4 -0.01 -0.6 -40 -25 -10 -0.02 0 32 64 96 128 160 192 224 256 5 20 35 50 65 Digital Input Code Temperature (°C) Figure 3. Figure 4. DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (85°C) FULL-SCALE ERROR vs TEMPERATURE 0.02 0.06 AVDD = 5V 0.01 AVDD = 5V 0.04 0 Full-Scale Error (mV) LE (LSB) 0.2 -0.01 -0.02 -0.01 -0.02 0.02 DLE (LSB) 0.3 0.01 0 0.02 0 -0.02 -0.04 -0.01 -0.02 0 32 64 96 128 160 192 224 256 -0.06 -40 -25 -10 Digital Input Code 5 20 35 50 65 Temperature (°C) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 7 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 5 V (continued) At TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted) SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 0.6 AVDD = 5V DAC Loaded with 000h 5.0 Analog Output Voltage (V) Analog Output Voltage (V) 5.5 4.5 4.0 3.5 3.0 AVDD = 5V DAC Loaded with FFFh 2.5 0 2 0.4 0.2 0 4 6 8 10 0 4 Figure 8. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 10 2000 SYNC Input (all other digital inputs = GND) Power-Supply Current (mA) 100 80 60 1500 Sweep from 0V to 5.5V 1000 Sweep from 5.5V to 0V 500 0 0 512 1024 1536 2048 2560 3072 3584 4096 0 0.5 1.0 1.5 2.0 Digital Input Code 2.5 3.0 3.5 4.0 4.5 5.0 95 110 125 VLOGIC (V) Figure 9. Figure 10. POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 140 1.6 AVDD = 5V Quiescent Current (mA) AVDD = 5V Power-Supply Current (mA) 8 Figure 7. AVDD = 5.5V 130 120 110 100 -40 -25 -10 8 6 ISINK (mA) 120 Power-Supply Current (mA) 2 ISOURCE (mA) 5 20 35 50 65 80 95 110 125 1.2 0.8 0.4 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) Temperature (°C) Figure 11. Figure 12. Submit Documentation Feedback 80 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 5 V (continued) At TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 102 -20 AVDD = 5V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz -40 AVDD = 5V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz 94 THD SNR (dB) THD (dB) SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY -60 86 2nd Harmonic 78 -80 3rd Harmonic 70 -100 0 1 2 3 4 5 0 2 3 4 fOUT (kHz) Figure 13. Figure 14. POWER SPECTRAL DENSITY DAC OUTPUT NOISE DENSITY vs FREQUENCY 0 5 300 AVDD = 5V, fOUT = 1kHz, fS = 225kSPS, Measurement Bandwidth = 20kHz 20 AVDD = 5V 250 Noise (nV/ÖHz) -40 Gain (dB) 1 fOUT (kHz) -60 -80 200 150 Midscale 100 -100 Zero Scale Full Scale 50 -120 0 -140 0 5 10 15 10 20 100 1k 10k 100k Frequency (Hz) Frequency (kHz) Figure 15. Figure 16. DAC OUTPUT NOISE 0.1-Hz TO 10-Hz BANDWIDTH CLOCK FEED THROUGH 5 V, 2 MHz, MIDSCALE VNOISE (1mV/div) VOUT (500mV/div) AVDD = 5V, DAC = Midscale, No Load 3mVPP AVDD = 5V Clock Feedthrough Impulse ~0.5nV-s Time (2s/div) Time (500ns/div) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 9 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 5 V (continued) At TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted) GLITCH ENERGY 5 V, 8-BIT, 1-LSB STEP, RISING EDGE GLITCH ENERGY 5 V, 8-BIT, 1-LSB STEP, FALLING EDGE AVDD = 5V From Code: 81h To Code: 80h VOUT (5mV/div) VOUT (5mV/div) Glitch Impulse ~1nV-s AVDD = 5V From Code: 80h To Code: 81h Clock Feedthrough ~0.5nV-s Glitch Impulse ~1nV-s Clock Feedthrough ~0.5nV-s Time (5ms/div) Time (5ms/div) Figure 19. Figure 20. FULL-SCALE SETTLING TIME 5-V RISING EDGE FULL-SCALE SETTLING TIME 5-V FALLING EDGE AVDD = 5V From Code: 000h To Code: FFFh AVDD = 5V From Code: FFFh To Code: 000h Rising Edge 1V/div Zoomed Rising Edge 100mV/div Falling Edge 1V/div Zoomed Falling Edge 100mV/div Trigger Pulse 5V/div Trigger Pulse 5V/div Time (2ms/div) Time (2ms/div) Figure 21. Figure 22. HALF-SCALE SETTLING TIME 5-V RISING EDGE HALF-SCALE SETTLING TIME 5-V FALLING EDGE AVDD = 5V From Code: C00h To Code: 400h Falling Edge 1V/div Rising Edge 1V/div Zoomed Falling Edge 100mV/div Zoomed Rising Edge 100mV/div AVDD = 5V From Code: 400h To Code: C00h Trigger Pulse 5V/div Trigger Pulse 5V/div Time (2ms/div) Time (2ms/div) Figure 23. 10 Figure 24. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 5 V (continued) At TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted) POWER-OFF GLITCH AVDD (2V/div) AVDD = 5V DAC = Zero Scale Load = 200pF || 10kW 17mV AVDD = 5V DAC = Zero Scale Load = 200pF || 10kW VOUT (20mV/div) VOUT (20mV/div) AVDD (2V/div) POWER-ON RESET TO 0 V POWER-ON GLITCH Time (5ms/div) Time (10ms/div) Figure 25. Figure 26. POWER-SUPPLY CURRENT vs POWER-SUPPLY VOLTAGE POWER-DOWN CURRENT vs POWER-SUPPLY VOLTAGE 120 0.4 AVDD = 1.8V to 5.5V 110 Quiescent Current (mA) Power-Supply Current (mA) AVDD = 1.8V to 5.5V 100 90 80 70 1.800 2.725 3.650 4.575 0.3 0.2 0.1 0 1.800 5.500 2.725 3.650 AVDD (V) AVDD (V) Figure 27. Figure 28. 4.575 5.500 POWER-SUPPLY CURRENT HISTOGRAM 50 45 AVDD = 5.5V 40 Occurrences 35 30 25 20 15 10 5 136 140 128 132 120 124 116 112 104 108 96 100 88 92 80 84 0 IDD (mA) Figure 29. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 11 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = +3.6 V At TA = 25°C, AVDD = +3.6 V, and DAC loaded with midscale code (unless otherwise noted) POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 140 1.2 AVDD = 3.6V 130 Quiescent Current (mA) 120 110 100 0.4 90 80 -40 -25 -10 5 20 35 50 65 80 95 0 -40 -25 -10 110 125 5 20 35 80 Figure 30. Figure 31. POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT HISTOGRAM 50 95 110 125 AVDD = 3.6V 45 40 900 35 Occurrences Sweep from 0V to 3.6V 600 30 25 20 15 300 10 Sweep from 3.6V to 0V 5 VLOGIC (V) 126 130 118 122 110 114 4.0 102 3.5 106 3.0 94 2.5 98 2.0 86 1.5 90 1.0 82 0.5 70 0 78 0 0 IDD (mA) Figure 32. Figure 33. SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 3.7 0.6 AVDD = 3.6V DAC Loaded with 0000h 3.5 Analog Output Voltage (V) Analog Output Voltage (V) 65 Temperature (°C) SYNC Input (all other digital inputs = GND) 3.3 3.1 2.9 2.7 AVDD = 3.6V DAC Loaded with FFFFh 2.5 0 12 50 Temperature (°C) 1200 Power-Supply Current (mA) 0.8 74 Power-Supply Current (mA) AVDD = 3.6V 2 4 0.4 0.2 0 6 8 10 0 2 4 6 ISOURCE (mA) ISINK (mA) Figure 34. Figure 35. Submit Documentation Feedback 8 10 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 2.7 V At TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted) DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 0.4 AVDD = 2.7V 0.01 AVDD = 2.7V 0 Zero-Code Error (mV) LE (LSB) 0.02 -0.01 -0.02 0.02 DLE (LSB) ZERO-CODE ERROR vs TEMPERATURE 0.01 0 0 64 96 128 160 192 224 0 -40 -25 -10 256 5 20 35 50 65 Temperature (°C) Figure 36. Figure 37. DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (25°C) OFFSET ERROR vs TEMPERATURE 80 95 110 125 80 95 110 125 80 95 110 125 0.6 AVDD = 2.7V 0.01 AVDD = 2.7V 0.4 0 Offset Error (mV) LE (LSB) 32 -0.01 -0.02 0.02 DLE (LSB) 0.1 Digital Input Code 0.02 0.01 0.2 0 -0.2 0 -0.4 -0.01 -0.6 -40 -25 -10 -0.02 0 32 64 96 128 160 192 224 256 5 20 35 50 65 Digital Input Code Temperature (°C) Figure 38. Figure 39. DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (85°C) FULL-SCALE ERROR vs TEMPERATURE 0.02 0.06 AVDD = 2.7V 0.01 AVDD = 2.7V 0.04 0 Full-Scale Error (mV) LE (LSB) 0.2 -0.01 -0.02 -0.01 -0.02 0.02 DLE (LSB) 0.3 0.01 0 0.02 0 -0.02 -0.04 -0.01 -0.02 0 32 64 96 128 160 192 224 256 -0.06 -40 -25 -10 Digital Input Code 5 20 35 50 65 Temperature (°C) Figure 40. Figure 41. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 13 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 2.7 V (continued) At TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted) SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 2.8 0.6 Analog Output Voltage (V) Analog Output Voltage (V) AVDD = 2.7V DAC Loaded with 000h 2.6 2.4 2.2 AVDD = 2.7V DAC Loaded with FFFh 2.0 0 2 0.4 0.2 0 4 6 8 10 0 8 Figure 43. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 10 800 SYNC Input (all other digital inputs = GND) Power-Supply Current (mA) Power-Supply Current (mA) 6 Figure 42. AVDD = 2.7V 90 80 70 60 50 600 Sweep from 0V to 2.7V 400 Sweep from 2.7V to 0V 200 0 0 512 1024 1536 2048 2560 3072 3584 4096 0 0.5 1.0 1.5 2.0 2.5 Digital Input Code VLOGIC (V) Figure 44. Figure 45. POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 120 3.0 1.0 AVDD = 2.7V AVDD = 2.7V 110 Quiescent Current (mA) Power-Supply Current (mA) 4 ISINK (mA) 100 100 90 80 70 -40 -25 -10 14 2 ISOURCE (mA) 5 20 35 50 65 80 95 110 125 0.8 0.6 0.4 0.2 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) Temperature (°C) Figure 46. Figure 47. Submit Documentation Feedback 80 95 110 125 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 2.7 V (continued) At TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 94 -20 AVDD = 2.7V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz AVDD = 2.7V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz 90 THD -40 SNR (dB) THD (dB) 86 -60 82 78 2nd Harmonic -80 74 3rd Harmonic 70 -100 0 1 2 3 4 5 0 2 3 4 fOUT (kHz) Figure 48. Figure 49. POWER SPECTRAL DENSITY POWER-SUPPLY CURRENT HISTOGRAM 0 50 AVDD DD = 2.7V, fOUT OUT = 1kHz, fS S = 225kSPS, Measurement Bandwidth = 20kHz 20 45 5 AVDD = 2.7V 40 35 Occurrences -40 Gain (dB) 1 fOUT (kHz) -60 -80 30 25 20 15 -100 10 -120 5 Frequency (kHz) 104 100 96 92 88 80 84 20 76 15 72 10 64 5 60 0 68 0 -140 IDD (mA) Figure 51. CLOCK FEED THROUGH 2.7 V, 20 MHz, MIDSCALE GLITCH ENERGY 2.7 V, 8-BIT, 1-LSB STEP, RISING EDGE VOUT (2mV/div) VOUT (500mV/div) Figure 50. Glitch Impulse ~1nV-s Clock Feedthrough ~0.4nV-s AVDD = 2.7V From Code: 80h To Code: 81h AVDD = 2.7V Clock Feedthrough Impulse ~0.4nV-s Time (5ms/div) Time (5ms/div) Figure 52. Figure 53. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 15 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 2.7 V (continued) At TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted) GLITCH ENERGY 2.7 V, 8-BIT, 1-LSB STEP, FALLING EDGE FULL-SCALE SETTLING TIME 2.7-V RISING EDGE AVDD = 2.7V From Code: 000h To Code: FFFh VOUT (2mV/div) AVDD = 2.7V From Code: 81h To Code: 80h Rising Edge 1V/div Zoomed Rising Edge 100mV/div Clock Feedthrough ~0.4nV-s Glitch Impulse ~1nV-s Trigger Pulse 2.7V/div Time (5ms/div) Time (2ms/div) Figure 54. Figure 55. FULL-SCALE SETTLING TIME 2.7-V FALLING EDGE HALF-SCALE SETTLING TIME 2.7-V RISING EDGE AVDD = 2.7V From Code: 400h To Code: C00h AVDD = 2.7V From Code: FFFh To Code: 000h Falling Edge 1V/div Rising Edge 1V/div Zoomed Falling Edge 100mV/div Zoomed Rising Edge 100mV/div Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div Time (2ms/div) Time (2ms/div) Figure 57. HALF-SCALE SETTLING TIME 2.7-V FALLING EDGE POWER-ON RESET TO 0 V POWER-ON GLITCH Falling Edge 1V/div Trigger Pulse 2.7V/div Zoomed Falling Edge 100mV/div VOUT (20mV/div) AVDD = 2.7V From Code: C00h To Code: 400h AVDD (1V/div) Figure 56. Time (5ms/div) Time (2ms/div) Figure 58. 16 17mV AVDD = 2.7V DAC = Zero Scale Load = 200pF || 10kW Figure 59. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 2.7 V (continued) At TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted) AVDD = 2.7V DAC = Zero Scale Load = 200pF || 10kW VOUT (20mV/div) AVDD (1V/div) POWER-OFF GLITCH Time (10ms/div) Figure 60. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 17 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 1.8 V At TA = 25°C, AVDD = 1.8 V, and DAC loaded with midscale code (unless otherwise noted) DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) AVDD = 1.8V 0.01 AVDD = 1.8V 1.0 0 -0.01 -0.02 0.02 DLE (LSB) ZERO-CODE ERROR vs TEMPERATURE 1.2 Zero-Code Error (mV) LE (LSB) 0.02 0.01 0 64 96 128 160 192 224 0 -40 -25 -10 256 20 35 50 65 Figure 61. Figure 62. DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (25°C) OFFSET ERROR vs TEMPERATURE 80 95 110 125 80 95 110 125 80 95 110 125 0.6 AVDD = 1.8V 0.01 AVDD = 1.8V 0.4 0 -0.01 -0.02 0.02 0.01 0.2 0 -0.2 0 -0.4 -0.01 -0.6 -40 -25 -10 -0.02 0 32 64 96 128 160 192 224 256 5 20 35 50 65 Digital Input Code Temperature (°C) Figure 63. Figure 64. DAC5311 8-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (85°C) FULL-SCALE ERROR vs TEMPERATURE 0.2 0.06 AVDD = 1.8V 0.1 AVDD = 1.8V 0.04 Full-Scale Error (mV) 0 -0.1 -0.2 0.02 0.01 0 0.02 0 -0.02 -0.04 -0.01 -0.02 0 32 64 96 128 160 192 224 256 -0.06 -40 -25 -10 Digital Input Code 5 20 35 50 65 Temperature (°C) Figure 65. 18 5 Temperature (°C) Offset Error (mV) LE (LSB) 32 Digital Input Code 0.02 DLE (LSB) 0.4 0.2 0 LE (LSB) 0.6 -0.01 -0.02 DLE (LSB) 0.8 Figure 66. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 1.8 V (continued) At TA = 25°C, AVDD = 1.8 V, and DAC loaded with midscale code (unless otherwise noted) SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 2.0 0.6 AVDD = 1.8V DAC Loaded with 000h Analog Output Voltage (V) Analog Output Voltage (V) 1.8 1.6 1.4 1.2 1.0 0.8 AVDD = 1.8V DAC Loaded with FFFh 0.6 0 0.4 0.2 0 2 4 6 8 0 2 4 ISOURCE (mA) Figure 67. Figure 68. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 100 SYNC Input (all other digital inputs = GND) Power-Supply Current (mA) Power-Supply Current (mA) 8 200 AVDD = 1.8V 90 80 70 60 50 150 Sweep from 0V to 1.8V 100 50 Sweep from 1.8V to 0V 0 0 512 1024 1536 2048 2560 3072 3584 4096 0 0.5 1.0 1.5 Digital Input Code VLOGIC (V) Figure 69. Figure 70. POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 110 2.0 0.8 AVDD = 1.8V AVDD = 1.8V 100 Quiescent Current (mA) Power-Supply Current (mA) 6 ISINK (mA) 90 80 70 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.6 0.4 0.2 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) Temperature (°C) Figure 71. Figure 72. 80 95 110 125 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 19 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 1.8 V (continued) At TA = 25°C, AVDD = 1.8 V, and DAC loaded with midscale code (unless otherwise noted) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 90 -20 AVDD = 1.8V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz THD AVDD = 1.8V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz 86 SNR (dB) -40 THD (dB) SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY -60 -80 82 78 2nd Harmonic 74 -100 3rd Harmonic 70 -110 0 1 2 3 4 5 0 2 3 4 fOUT (kHz) Figure 73. Figure 74. POWER SPECTRAL DENSITY POWER-SUPPLY CURRENT HISTOGRAM 0 50 AVDD = 1.8V, fOUT = 1kHz, fS = 225kSPS, Measurement Bandwidth = 20kHz 20 45 5 AVDD = 1.8V 40 35 Occurrences -40 Gain (dB) 1 fOUT (kHz) -60 -80 30 25 20 15 -100 10 -120 5 Frequency (kHz) 116 120 108 112 100 104 92 96 84 88 IDD (mA) Figure 76. CLOCK FEED THROUGH 1.8 V, 20 MHz, MIDSCALE GLITCH ENERGY 1.8 V, 8-BIT, 1-LSB STEP, RISING EDGE Glitch Impulse ~1nV-s VOUT (2mV/div) VOUT (500mV/div) Figure 75. AVDD = 1.8V Clock Feedthrough Impulse ~0.34nV-s Clock Feedthrough ~0.3nV-s Time (5ms/div) AVDD = 1.8V From Code: 80h To Code: 81h Time (5ms/div) Figure 77. 20 76 20 80 15 68 10 72 5 60 0 64 0 -140 Figure 78. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 TYPICAL CHARACTERISTICS: AVDD = 1.8 V (continued) At TA = 25°C, AVDD = 1.8 V, and DAC loaded with midscale code (unless otherwise noted) GLITCH ENERGY 1.8 V, 8-BIT, 1-LSB STEP, FALLING EDGE FULL-SCALE SETTLING TIME 1.8-V RISING EDGE AVDD = 1.8V From Code: 000h To Code: FFFh VOUT (2mV/div) AVDD = 1.8V From Code: 81h To Code: 80h Clock Feedthrough ~0.3nV-s Zoomed Rising Edge 100mV/div Rising Edge 1V/div Trigger Pulse 1.8V/div Glitch Impulse ~1nV-s Time (2ms/div) Time (5ms/div) Figure 79. Figure 80. FULL-SCALE SETTLING TIME 1.8-V FALLING EDGE HALF-SCALE SETTLING TIME 1.8-V RISING EDGE AVDD = 1.8V From Code: 400h To Code: C00h AVDD = 1.8V From Code: FFFh To Code: 000h Falling Edge 1V/div Rising Edge 1V/div Zoomed Falling Edge 100mV/div Zoomed Rising Edge 100mV/div Trigger Pulse 1.8V/div Trigger Pulse 1.8V/div Time (2ms/div) Time (2ms/div) Figure 82. HALF-SCALE SETTLING TIME 1.8-V FALLING EDGE POWER-ON RESET TO 0 V POWER-ON GLITCH Falling Edge 1V/div Zoomed Falling Edge 100mV/div Trigger Pulse 1.8V/div VOUT (20mV/div) AVDD = 1.8V From Code: C00h To Code: 400h AVDD (1V/div) Figure 81. AVDD = 1.8V DAC = Zero Scale Load = 200pF || 10kW 4mV Time (5ms/div) Time (2ms/div) Figure 83. Figure 84. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 21 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: AVDD = 1.8 V (continued) At TA = 25°C, AVDD = 1.8 V, and DAC loaded with midscale code (unless otherwise noted) AVDD = 1.8V DAC = Zero Scale Load = 200pF || 10kW VOUT (20mV/div) AVDD (1V/div) POWER-OFF GLITCH Time (10ms/div) Figure 85. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 THEORY OF OPERATION DAC SECTION The DAC5311 is fabricated using TI's proprietary HPA07 process technology. The architecture consists of a string DAC followed by an output buffer amplifier. Because there is no reference input pin, the power supply (AVDD) acts as the reference. Figure 86 shows a block diagram of the DAC architecture. AVDD REF (+) DAC Register VOUT Resistor String Output Amplifier GND Figure 86. DAC5311 Architecture The input coding to the DAC5311 is straight binary, so the ideal output voltage is given by: D V OUT + AVDD 2n Where: n = resolution in bits (8) D = decimal equivalent of the binary code that is loaded to the DAC register. It ranges from 0 to 255 for 8-bit DAC5311. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 23 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com RESISTOR STRING The resistor string section is shown in Figure 87. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is tested monotonic because it is a string of resistors. VREF RDIVIDER VREF 2 R R To Output Amplifier R R Figure 87. Resistor String OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0 V to AVDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics section for the given voltage input. The slew rate is 0.7 V/µs with a half-scale settling time of typically 6µs with the output unloaded. SERIAL INTERFACE The DAC5311 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. Input Shift Register The input shift register is 16 bits wide, as shown in Table 2. The first two bits (PD0 and PD1) are reserved control bits that set the desired mode of operation (normal mode or any one of three power-down modes) as indicated in Table 3. The remaining data bits are eight data bits, followed by don't care bits, as shown in Table 2. 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the DAC5311 compatible with high-speed DSPs. On the 16th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed. At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought high again before the next write sequence. SYNC Interrupt In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, bringing SYNC high before the 16th falling edge acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 88. Table 2. 8-Bit Data Input Register DB15 DB14 PD1 PD0 D7 D6 D5 D4 D3 D2 D1 DB6 DB5 D0 X DB0 X X X X X CLK SYNC DIN DB15 DB0 DB15 Invalid Write Sequence: SYNC HIGH before 16th Falling Edge DB0 Valid Write Sequence: Output Updates on 16th Falling Edge Figure 88. DAC5311 SYNC Interrupt Facility POWER-ON RESET TO ZERO-SCALE The DAC5311 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0 V. The DAC register remains that way until a valid write sequence is made to the DAC. This design is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. The occurring power-on glitch impulse is only a few millivolts (typically, 17 mV; see Figure 25). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 25 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com POWER-DOWN MODES The DAC5311 contains four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 3 shows how the state of the bits corresponds to the mode of operation of the device. Table 3. Modes of Operation PD1 PD0 OPERATING MODE Normal Mode 0 0 Normal Operation Power-Down Modes 0 1 Output 1 kΩ to GND 1 0 Output 100 kΩ to GND 1 1 High-Z When both bits are set to '0', the device works normally with a standard power consumption of typically 80 µA at 1.8 V. However, for the three power-down modes, the typical supply current falls to 0.5 µA at 5 V, 0.4 µA at 3V, and 0.1 µA at 1.8 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. The advantage of this architecture is that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND either through a 1-kΩ resistor or a 100-kΩ resistor, or is left open-circuited (High-Z). Figure 89 illustrates the output stage. Amplifier Resistor String DAC VOUT Power-down Circuitry Resistor Network Figure 89. Output Stage During Power-Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 50 µs for AVDD = 5 V and AVDD = 3 V. DAC NOISE PERFORMANCE Typical noise performance is shown in Typical Characteristics. Output noise spectral density at the VOUT pin versus frequency is depicted for full-scale, midscale, and zero-scale input codes. The typical noise density for midscale code is 110 nV/√Hz at 1 kHz and at 1 MHz. 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 APPLICATION INFORMATION USING THE REF5050 AS A POWER SUPPLY FOR THE DAC5311 As a result of the extremely low supply current required by the DAC5311, an alternative option is to use a REF5050 5 V precision voltage reference to supply the required voltage to the part, as shown in Figure 90. This option is especially useful if the power supply is too noisy or if the system supply voltages are at some value other than 5 V. The REF5050 outputs a steady supply voltage for the DAC5311. If the REF5050 is used, the current needed to supply DAC5311 is typically 110 µA at 5 V, with no load on the output of the DAC. When the DAC output is loaded, the REF5050 also needs to supply the current to the load. The total current required (with a 5-kΩ load on the DAC output) is: 110 µA + (5 V/5 kΩ) = 1.11 mA The load regulation of the REF5050 is typically 0.002%/mA, which results in an error of 90 µV for the 1.1 mA current drawn from it. +5.5V +5V REF5050 1 mF Three-Wire Serial Interface 110mA SYNC VOUT = 0V to 5V SCLK DAC5311 DIN Figure 90. REF5050 as Power Supply to DAC5311 For other power-supply voltages, alternative references such as the REF3030 (3 V), REF3033 (3.3 V), or REF3220 (2.048 V) are recommended. For a full list of available voltage references from TI, see the TI web site at www.ti.com. BIPOLAR OPERATION The DAC5311 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 91. The circuit shown gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an OPA211, OPA340, or OPA703 as the output amplifier. For a full list of available operational amplifiers from TI, see the TI web site at www.ti.com The output voltage for any input code can be calculated as follows: VO + ƪ ǒ2DnǓ AVDD ǒ R1 ) R 2 R1 Ǔ * AV DD ǒ Ǔƫ R2 R1 (1) Where: n = resolution in bits (8) D = decimal equivalent of the binary code that is loaded to the DAC register. It ranges from 0 to 255 for 8-bit DAC5311. With AVDD = 5 V, R1 = R2 = 10 kΩ: ǒ Ǔ V O + 10 n D *5V 2 (2) This is an output voltage range of ±5 V with 00h corresponding to a –5 V output and FFh corresponding to a 5-V output. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 27 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com R2 10kW +5V +5.5V R1 10kW OPA211 VOUT AVDD 10mF ±5V DAC5311 - 5.5V 0.1mF Three-Wire Serial Interface Figure 91. Bipolar Operation with the DAC5311 MICROPROCESSOR INTERFACING DAC5311 to 8051 Interface Figure 92 shows a serial interface between the DAC5311 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC5311, while RXD drives the serial data line of the part. The SYNC signal is derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data are to be transmitted to the DAC5311, P3.3 is taken low. The 8051 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 remains low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC5311 requires its data with the MSB as the first bit received. Therefore, the 8051 transmit routine must take this requirement into account, and mirror the data as needed. 80C51/80L51(1) DAC5311(1) P3.3 SYNC TXD SCLK RXD DIN NOTE: (1) Additional pins omitted for clarity. Figure 92. DAC5311 to 80C51/80L51 Interfaces DAC5311 to Microwire Interface Figure 93 shows an interface between the DAC5311 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and are clocked into the DAC5311 on the rising edge of the SK signal. DAC5311(1) Microwire CS SYNC SK SCLK SO DIN NOTE: (1) Additional pins omitted for clarity. Figure 93. DAC5311 to Microwire Interface 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 DAC5311 to 68HC11 Interface Figure 94 shows a serial interface between the DAC5311 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC5311, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051. DAC5311(1) 68HC11(1) PC7 SYNC SCK SCLK MOSI DIN NOTE: (1) Additional pins omitted for clarity. Figure 94. DAC5311 to 68HC11 Interface The 68HC11 should be configured so that its CPOL bit is a '0' and its CPHA bit is a '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is taken low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data are transmitted MSB first. In order to load data to the DAC5311, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 29 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC5311 offers single-supply operation; it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. Because of the single ground pin of the DAC5311, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND is connected directly to an analog ground plane. This plane should be separate from the ground connection for the digital components until they are connected at the power entry point of the system. The power applied to AVDD should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as the internal logic switches state. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. This condition is particularly true for the DAC5311, as the power supply is also the reference voltage for the DAC. As with the GND connection, AVDD should be connected to a 5 V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1 µF to 10 µF and 0.1 µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise. 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC. They are most important in applications where the signal changes slowly and accuracy is required. Resolution Generally, the DAC resolution can be expressed in different forms. Specifications such as IEC 60748-4 recognize the numerical, analog, and relative resolution. The numerical resolution is defined as the number of digits in the chosen numbering system necessary to express the total number of steps of the transfer characteristic, where a step represents both a digital input code and the corresponding discrete analogue output value. The most commonly-used definition of resolution provided in data sheets is the numerical resolution expressed in bits. Least Significant Bit (LSB) The least significant bit (LSB) is defined as the smallest value in a binary coded system. The value of the LSB can be calculated by dividing the full-scale output voltage by 2n, where n is the resolution of the converter. Most Significant Bit (MSB) The most significant bit (MSB) is defined as the largest value in a binary coded system. The value of the MSB can be calculated by dividing the full-scale output voltage by 2. Its value is one-half of full-scale. Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity (INL) is defined as the maximum deviation between the real transfer function and a straight line passing through the endpoints of the ideal DAC transfer function. INL is measured in LSBs. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is defined as the maximum deviation of the real LSB step from the ideal 1 LSB step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. If the DNL is within ±1 LSB, the DAC is said to be monotonic. Full-Scale Error Full-scale error is defined as the deviation of the real full-scale output voltage from the ideal output voltage while the DAC register is loaded with the full-scale code (0xFFFF). Ideally, the output should be VDD – 1 LSB. The full-scale error is expressed in percent of full-scale range (%FSR). Offset Error Offset error is defined as the difference between actual output voltage and the ideal output voltage in the linear region of the transfer function. This difference is calculated by using a straight line defined by two codes (for example, for 16-bit resolution, codes 485 and 64714). Since the offset error is defined by a straight line, it can have a negative or positive value. Offset error is measured in mV. Zero-Code Error Zero-code error is defined as the DAC output voltage, when all '0's are loaded into the DAC register. Zero-scale error is a measure of the difference between actual output voltage and ideal output voltage (0 V). It is expressed in mV. It is primarily caused by offsets in the output amplifier. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 31 DAC5311-Q1 SBAS470 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com Gain Error Gain error is defined as the deviation in the slope of the real DAC transfer characteristic from the ideal transfer function. Gain error is expressed as a percentage of full-scale range (%FSR). Full-Scale Error Drift Full-scale error drift is defined as the change in full-scale error with a change in temperature. Full-scale error drift is expressed in units of %FSR/°C. Offset Error Drift Offset error drift is defined as the change in offset error with a change in temperature. Offset error drift is expressed in µV/°C. Zero-Code Error Drift Zero-code error drift is defined as the change in zero-code error with a change in temperature. Zero-code error drift is expressed in µV/°C. Gain Temperature Coefficient The gain temperature coefficient is defined as the change in gain error with changes in temperature. The gain temperature coefficient is expressed in ppm of FSR/°C. Power-Supply Rejection Ratio (PSRR) Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB). Monotonicity Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output changes in the same direction or remains at least constant for each step increase (or decrease) in the input code. DYNAMIC PERFORMANCE Dynamic performance parameters are specifications such as settling time or slew rate, which are important in applications where the signal rapidly changes and/or high frequency signals are present. Slew Rate The output slew rate (SR) of an amplifier or other electronic circuit is defined as the maximum rate of change of the output voltage for all possible input signals. SR = max DVOUT(t) Dt (3) Where ΔVOUT(t) is the output produced by the amplifier as a function of time t. Output Voltage Settling Time Settling time is the total time (including slew time) for the DAC output to settle within an error band around its final value after a change in input. Settling times are specified to within ±0.003% (or whatever value is specified) of full-scale range (FSR). Code Change/Digital-to-Analog Glitch Energy Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolts-second (nV-s), and is measured when the digital input code is changed by 1 LSB at the major carry transition. 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 Digital Feed Through Digital feed through is defined as impulse seen at the output of the DAC from the digital inputs of the DAC. It is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus; that is, from all '0's to all '1's and vice versa. Channel-to-Channel DC Crosstalk Channel-to-channel dc crosstalk is defined as the dc change in the output level of one DAC channel in response to a change in the output of another DAC channel. It is measured with a full-scale output change on one DAC channel while monitoring another DAC channel remains at midscale. It is expressed in LSB. Channel-to-Channel AC Crosstalk AC crosstalk in a multi-channel DAC is defined as the amount of ac interference experienced on the output of a channel at a frequency (f) (and its harmonics), when the output of an adjacent channel changes its value at the rate of frequency (f). It is measured with one channel output oscillating with a sine wave of 1-kHz frequency, while monitoring the amplitude of 1-kHz harmonics on an adjacent DAC channel output (kept at zero scale). It is expressed in dB. Signal-to-Noise Ratio (SNR) Signal-to-noise ratio (SNR) is defined as the ratio of the root mean-squared (RMS) value of the output signal divided by the RMS values of the sum of all other spectral components below one-half the output frequency, not including harmonics or dc. SNR is measured in dB. Total Harmonic Distortion (THD) Total harmonic distortion + noise is defined as the ratio of the RMS values of the harmonics and noise to the value of the fundamental frequency. It is expressed in a percentage of the fundamental frequency amplitude at sampling rate fS. Spurious-Free Dynamic Range (SFDR) Spurious-free dynamic range (SFDR) is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of the difference in amplitude between the fundamental and the largest harmonically or non-harmonically related spur from dc to the full Nyquist bandwidth (half the DAC sampling rate, or fS/2). A spur is any frequency bin on a spectrum analyzer, or from a Fourier transform, of the analog output of the DAC. SFDR is specified in decibels relative to the carrier (dBc). Signal-to-Noise Plus Distortion (SINAD) SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing any internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. DAC Output Noise Density Output noise density is defined as internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. DAC Output Noise DAC output noise is defined as any voltage deviation of DAC output from the desired value (within a particular frequency band). It is measured with a DAC channel kept at midscale while filtering the output voltage within a band of 0.1 Hz to 10 Hz and measuring its amplitude peaks. It is expressed in terms of peak-to-peak voltage (Vpp). Full-Scale Range (FSR) Full-scale range (FSR) is the difference between the maximum and minimum analog output values that the DAC is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these values are usually given as the values matching with code 0 and 2n – 1. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC5311-Q1 33 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC5311IDCKRQ1 Package Package Pins Type Drawing SC70 DCK 6 SPQ Reel Reel Diameter Width (mm) W1 (mm) 3000 177.8 9.7 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 2.3 2.52 1.2 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5311IDCKRQ1 SC70 DCK 6 3000 184.0 184.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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