DD-03182 SERIES ARINC 429 LINE DRIVER FEATURES DESCRIPTION The DD-03182 device is a line driver chip that transmits data on the serial data bus in accordance with the “ARINC Specification 429 Mark 33 Digital Information Transfer System” (ARINC 429). This device can be used with DDC’s DD-03296 discrete-to-digital device, in conjunction with the DD03282 transceiver chip or the DD00429 microprocessor interface. The line driver receives TTL information on the DataA/DataB input pins and transmits it out on the AOUT/BOUT output pins. The output voltage level is programmable via the VREF input pin. The output pins are also protected against short circuits from aircraft power. The slew rate of the DD-03182 can be programmed for either High (100 kbit) or Low (12.5 kbit) speed via two external timing capacitors connected to the CA/CB input pins. APPLICATIONS The DD-03182 can be used for many different applications ranging from flight critical to nonessential. Surface mount, DIP and PLCC package configurations are available. Military temperature range is also available if required. • Plastic 14-Pin SOIC Package Available with or without Fuse • Pin-For-Pin Alternative for Most Harris/Holt/Raytheon Applications • Programmable Output Voltage Level • Short-Circuit Protection on Outputs • Programmable Slew and Data Rates +V CA DATA (A) LEVEL SHIFTER AND SLOPE CONTROL (A) OUTPUT DRIVER (A) AOUT ROUT 2 CLOCK GND VREF OVERVOLTAGE PROTECTION (OPTIONAL) SYNC LEVEL SHIFTER AND SLOPE CONTROL (B) DATA (B) OUTPUT DRIVER (B) ROUT 2 V1 CURRENT REGULATOR BIAS -V CB FIGURE 1. DD-03182 BLOCK DIAGRAM © 1993, 1999 Data Device Corporation Overvoltage Protection optional for DD-03182VP only. BOUT GENERAL TABLE 1. DD-03182 SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATINGS VOLTAGE BETWEEN PINS +V and -V V1 and GND VREF and GND Output Short-circuit Protection Output Overvoltage Protection Power Dissipation POWER SUPPLY REQUIREMENTS +V -V V1 VREF (for ARINC 429) VREF (for other applications) THERMAL Operating Ambient Temperature Ceramic Plastic Storage Temperature Lead Temperature (localized 10 sec duration) Thermal Resistance: Junction to Case θjc DD-03182DC Junction to Ambient θja (see Note 3) DD-03182DC DD-03182PP DD-03182GP DD-03182VP Max. Junction Temperature SIZE DD-03182VP DD-03182DC DD-03182GP DD-03182PP WEIGHT DD-03182VP DD-03182DC DD-03182GP DD-03182PP UNITS MIN TYP V V V MAX The ARINC 429 standard is widely used in the civil aerospace market (commercial aircraft). ARINC 429 operates at either 12 to 14.5 or 100 kbits on a simplex bus. A simplex bus is one on which there is only one transmitter but multiple receivers (up to a maximum of 20 in the case of 429). If receipt of a message by a given sink R(n) is required by the source T, a separate bus with R(n) as the source and T as the sink is required. To those designers who focus on military systems, a simplex bus may seem cumbersome, but it can be readily certified for civil aircraft. 40 7 6 See Note 1 See Note 2 Communications on 429 buses use 32-bit words with odd parity. The waveform is a bipolar return to zero with each bit lasting either 70 or 83µs ±2.5 percent, or 10µs, ±2.5 percent, depending on whether the bus is low- or high-speed. A low-speed bus is used for general purpose, low critical applications. A highspeed bus is used for transmitting large quantities of data or flight critical information. See TABLE 2 VDC VDC VDC VDC VDC 11.4 -11.4 4.75 4.75 0 °C °C °C °C -55 -40 -65 15 -15 5 5 15 °C/W °C/W °C/W °C/W °C 75 95 115 130 oz. (g.) oz. (g.) oz. (g.) oz. (g.) ARINC 429 imposes relatively modest and readily achievable performance demands on the hardware. FIGURE 2 is a general schematic of a 429 bus. The transmitter output impedance should be in the range of 75 to 85 Ω, equally divided between the two leads. The output voltage, Vo, is 10 V and is generated by imposing equal but opposite polarity voltages on the two leads. The null voltage is 0.5 V. For the receiver, the input resistance shall be greater than 12,000 Ω and the input differential capacitance and the capacitance to ground shall, in both cases, be less than 50 pF. The 12,000 Ω minimum input resistance ensures that up to 20 receivers can be on the bus without overloading it and minimizes receiver interaction under fault conditions. To preclude continued receiver operation in a lead-to-ground fault condition, 429 has established the range of acceptable receiver voltage levels to be +6.5 to +13.0 V and -6.5 to -13.0 V and null levels from +2.5 to -2.5 V. Any signals falling outside of these levels will be ignored. Also note that a lead-to-ground fault will produce a differential voltage swing up 5.5 V. FIGURE 4 shows the waveforms required by 429 and permissible levels for transmitter and receiver voltages. +125 +85 +150 +300 °C/W in. (mm.) in. (mm.) in. (mm.) in. (mm.) 16.5 -16.5 5.25 5.25 175 0.344 x 0.158 x 0.069 (8.737 x 4.013 x 1.753) 0.785 x 0.291 x 0.160 (19.939 x 7.391 x 4.064) 0.413 x 0.300 x 0.082 (10.490 x 7.620 x2.080) 0.454 x 0.454 x 0.155 (11.53 x 11.53 x 3.94) 0.01 0.08 0.02 0.04 Signal Leads (0.28) (2.26) (0.57) (1.13) A A B B Transmitter Receiver Shield Notes: 1. Both outputs can be shorted to ground or to each other, at +25°C ambient temperature. 2. Both outputs are fused between 0.5 Amp DC and 1.0 Amp DC to prevent an overvoltage fault from coupling onto the system power bus. 3. Thermal resistance when mounted on a 4" x 4" FR4 PC board in a horizontal position, still air. To Other Receivers (max. total of 20) FIGURE 2. GENERALIZED 429 BUS 2 TABLE 2. DD-03182 POWER DISSIPATION FOR CONTINUOUS ARINC 429 TRANSMISSION VREF and +V @ -V @ LOAD POWER LOAD V1 @ 15 V -15 V (mW) (Note 2) (mA) (mA) (Note 1) 5V R C (Note 3) (Note 3) (mA) (Ω) (pF) DATA RATE (KBPS) 0 TO 100 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 100 100 100 100 100 100 100 100 100 Notes: No load 2000 2000 2000 800 800 800 400 400 400 2000 2000 2000 800 800 800 400 400 400 0 1000 10,000 30,000 1000 10,000 30,000 1000 10,000 30,000 1000 3,000 10,000 1000 3,000 10,000 1000 3,000 10,000 2.5 4.6 6.5 11.3 7.8 8.9 13.5 12.5 13 16.2 5.8 9.3 22.2 8.4 11.4 23.1 12.8 14.3 24.4 -5.0 -7.1 -8.9 -13.8 -10.3 -11.4 -16 -15.1 -15.5 -18.7 -8.3 -11.7 -24.7 -11 -14 -25.7 -15.3 -16.8 -26.9 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 4.4 CHIP POWER (mW) (Note 1) 0 19 19 19 42 42 42 71 71 71 19 19 19 42 42 42 71 71 71 120 158 206 336 219 249 371 317 329 414 189 281 627 237 317 629 324 364 633 1. Supply current data is at 100% duty cycle. Load and chip power is calculated as 89% duty cycle (32 bits,/36 bits). 2. Data is not presented for 30,000 pF at 100 kbps. This is considered an unrealistic load for high-speed operation. 3. For 12 volt power supplies, multiply tabulated values of chip power by 0.8. TABLE 3. DD-03182 DC ELECTRICAL CHARACTERISTICS CONDITIONS: Ambient Temperature is in accordance with the temperature range of device type ordered; +V = +15 VDC ±10%; -V = -15 VDC ±10%; V1 = VREF = +5 VDC ±5%*. PARAMETER (SYMBOL) Quiescent +V Supply Current (IQ+V) UNITS mA MIN TYP 2.5 Quiescent -V Supply Current (IQ-V) mA 5 Quiescent V1 Supply Current (IQV1) mA 4.4 Quiescent VREF supply current (IQVREF) µA 10 Logic 1 input V (VIH) Logic 1 input I (IIH) V µA MAX No load 429 mode. DATA = CLOCK = SYNC = L 2.0 10 Logic 0 input V (VIL) V 0.6 Logic 0 input I (IIL) µA -20 Output voltage high: +1 (VOH) V Output voltage null: 0 (VNULL) VREF -250 mV TEST CONDITIONS No load 429 mode. DATA = CLOCK = SYNC = L No load 429 mode. DATA = CLOCK = SYNC = L No load 429 mode. DATA = CLOCK = SYNC = L No load No load No load No load (Pin 15 IIL = -2 mA max.) VREF VREF +250 mV No load 429 Mode +250 No load 429 Mode -VREF -VREF +250 mV No load 429 Mode mV -250 Output voltage low: -1 (VOL) V -VREF -250 mV Timing capacitor charge current: CA [+1] CB [-1] (ICT+) CA [-1] CB [+1] (ICT-) µA µA +V Short-circuit supply current (ISC [+V]) mA +150 Output short to GND. -V Short-circuit supply current (ISC [-V]) mA -150 Output short to GND. Output resistance each output (ROUT/2) is at +25°C only. ohms Input capacitance (CIN) No load 429 Mode. SYNC = CLOCK = H CA and CB held at 0 +200 -200 30 pF 37.5 45 15 *Note: The device will operate with +V and -V supplies at ±12 VDC ±5% in accordance with the temperature range of the device type ordered. 3 ing capacitors on CA and CB. Typical Values are 75 pF for 100 kHz data and 500 pF for 12.5 kHz data. The DD-03182 line driver is designed to take data from a box and place it on the data bus. The serial data is presented on DATA(A) and DATA(B) inputs in a dual rail format. The driver is enabled by the SYNC and CLOCK inputs. The output voltage level is programmed by the VREF input and is normally tied to +5 VDC along with V1 to produce output levels of +5V, 0V, and -5 V on each output for 10 V differential outputs (see FIGURE 3). The cable used in 429 buses is a twisted, shielded pair of 20- to 26-gauge conductors. The shield is grounded at both ends of the cable run and at all production breaks. Although there is no specification placed on the cable impedance, it generally falls in the range of 60 to 80 Ω. The outputs are fused for fail-safe protection against shorts to aircraft power. The output slew rate is controlled by external tim- TABLE 4. DD-03182 TRUTH TABLE SYNC (Note 1) CLOCK (Note 1) DATA (A) (Note 1) DATA (B) (Note 1) AOUT (Note 2) BOUT (Note 2) COMMENTS L X X X 0 0 Null X L X X 0 0 Null H H L L 0 0 Null H H H H 0 0 Null H H H L +1 -1 Logic 1 H H L H -1 +1 Logic 0 Notes: 1. X = Don’t care. 2. The AOUT/BOUT notation is as follows: +1 = VREF volts 0=0 A IN (A) DATA B IN (B) DATA +V REF A OUT -V REF +V REF B OUT -V REF 0V 0V Note: The output slew rates are controlled by timing capacitors CA and CB. They are charged to ±200µA (nominal). Slew rate (SR) is calculated by SR = 200/C (V/µs), where C is in pF. FIGURE 3. ARINC 429 WAVEFORM 4 SLEW RATE VS. TIMING CAPACITOR VALUES (0.4 V/µsec)(10) = 4.0 V The output slew rates are controlled by timing capacitors CA and CB, and are charged by ±200 µA (nominal). Slew rate (SR) is calculated by: SR = 4/(Rise Time) SR = 200/C (V/µsec), where C is in pF (equation 1). 0.267 µsec = 4V/15 µsec Capacitor = 200/0.267 = 750 pF HIGH-SPEED SLEW RATE DD-03182 PIN FUNCTIONS 0.8 µsec = 4V/5 µsec Capacitor = 200/0.8 = 250 pF Refer to FIGURES 7, 8 and 9 and TABLE 5 for specific package pin configurations. CA and CB = 75 pF for 100 kbps From equation 1: 200/75 = 2.67 V/µsec 10% - 90% = 0.5 V to 4.5 V ∆ = 4.0 V VREF (Input) – the voltage on VREF sets the output voltage levels on AOUT and BOUT. The output logic level swings between +VREF volts, 0 volts and -VREF volts. For 100 kbps bit rate, the slew rate specification is 1.5 µsec ±0.5 µsec. Slew rate range (1.0 to 2.0 µsec). N/C – No Connection 200/SR = Capacitor, in pF 200/2.67 = 75 pF SYNC (Input) – Logic 0 outputs will be forced to NULL or MARK state. Logic 1 enables data transmission. (2.67 V/µsec)(1.5) = 4.0 V CLOCK (Input) – Logic 0 outputs will be forced to NULL or MARK state. Logic 1 enables data transmission. SR = 4/(Rise Time) DATA(A)/DATA(B) (Inputs) – These signals contain the serial data to be transmitted on the ARINC 429 data bus. 4 µsec = 4V/1 µsec Capacitor = 200/4 = 50 pF 2 µsec = 4V/2 µsec Capacitor = 200/2 = 100 pF LOW-SPEED SLEW RATE CA/CB (Analog) – External timing capacitors are tied from these points to ground to establish the output signal slew rate. Typically, CA=CB=75 pF for 100 kHz data and CA=CB=500 pF for 12.5 kHz data. CA and CB = 500 pF for 12.5 kbps From equation 1: 200/500 = 0.4 V/µsec AOUT/BOUT (Output) – These are the line driver outputs which are connected to the aircraft serial data bus. -V (Input) – This is the negative supply input (-15 VDC nominal). For 12.5 kbps bit rate, the slew rate specification is 10 µsec ±5.0 µsec. Slew rate range (5 to 15 µsec). GND – Ground +V (Input) – This is the positive supply input (+15 VDC nominal). 200/SR = Capacitor in pF 200/0.4 = 500 pF V1 (Input) – This is the logic supply input (+5 VDC nominal). TABLE 5. DD-03182 PINOUTS PIN NUMBER DC OR GP PACKAGE DC OR GP PACKAGE 1 VREF VREF VREF PP PACKAGE 15 N/C GND 2 N/C N/C N/C 16 V1 +V 3 SYNC GND SYNC 17 BOUT 4 DATA (A) 5 CA SYNC DATA (A) 18 N/C N/C CA 6 AOUT 19 N/C DATA (A) AOUT 7 -V 20 N/C N/C -V 21 N/C 8 GND N/C GND 22 CB 9 +V CA +V 23 DATA (B) N/C BOUT 24 N/C 25 CLOCK PP PACKAGE VP PACKAGE PIN NUMBER 10 N/C 11 BOUT N/C CB 12 CB N/C DATA (B) 26 N/C 13 DATA (B) AOUT CLOCK 27 N/C 14 CLOCK -V V1 28 V1 5 ADG412BR TX0_SEL V+ 13 1 IN1 SPD1A 2 S1 3 D1 GND TX0_SEL 16 IN2 SPD1B 15 S2 14 D2 V- 4 9 IN3 TX1_SEL SPD2A 10 TX1_SEL 8 SPD2A 7 5 VCC S3 11 D3 VR 12 IN4 S4 DD-03182GP VCC VCC 6 D4 VCC VCC TX0_A TX0_B SPD1A 16 V1 1 VREF VCC C12 470 pF C8 68 pF 3 SYNC 14 CLK 4 DATA_A 13 DATA_B 5 CA 12 CB 7 9 SPD1B B_OUT 6 TX0_A_OUT 11 TX0_B_OUT VV+ 8 C13 470 pF A_OUT GND C9 68 pF FIGURE 4. RECOMMENDED CIRCUITRY SWITCHING CAPACITORS FOR HIGH-SPEED/LOW-SPEED OPERATION +5V 1 VCC ARINC 429 RECEIVE CH 1 ARINC 429 RECEIVE CH 2 2 DI1(A) 3 DI1(B) 4 DI2(A) 5 DI2(B) +5V +15V ARINC 429 TRANSMIT 6 11 C2 75pF 6 7 TXR 30 SEL -15V 7 9 16 A 4 B 13 14 3 C C 1 5 12 8 DR1 DR2 DD-03282DC 31 32 TX0 A TX0 B C2 75pF DO(A) DO(B) 40 DD-03182GP 37 NOTE: C1 = C2 = 500pF FOR LO SPEED OPERATION 38 1 MHZ CLK 9 10 28 29 34 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MR DBCEN 1MCK TXCK 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 GND 21 FIGURE 5. TYPICAL TRANSCEIVER/LINE DRIVER INTERCONNECT CONFIGURATION 6 DIGITAL CONTROL INTERFACE EN TX 33 +5V 39 OE1 OE2 LD1 LD2 LDCW 8 DIGITAL DATA INTERFACE TOP VIEW AOUT DD-03182 BOUT MICRO-SEM SMAJ6.5CA G N D N / C 4 3 2 1 V 1 N / C N / C 28 27 26 CLOCK DATA (A) 6 24 N/C N/C 7 23 DATA (B) 22 CB DD-03182PP PLCC N/C 8 CA 9 21 N/C N/C 10 20 N/C N/C 11 19 N/C N / C 13 14 A -v O U T 15 16 G N D +v 17 18 B N / C O U T FIGURE 7. DD-03182PP PIN CONFIGURATION TOP VIEW TOP VIEW 1 14 V1 N/C 2 13 CLOCK SYNC 3 12 DATA(B) DATA(A) 4 11 CB CA 5 10 B OUT A R E F 25 12 FIGURE 6. RECOMMENDED TRANSIENT PROTECTION CIRCUIT V 5 N/C MICRO-SEM SMAJ6.5CA S Y N C OUT 6 9 +V -V 7 8 GND 1 16 V1 N/C 2 15 N/C SYNC 3 14 CLOCK DATA(A) 4 13 DATA(B) CA 5 12 CB A OUT 6 11 B OUT -V 7 10 N/C GND 8 9 +V FIGURE 9. DD-03182DC AND GP PIN CONFIGURATION FIGURE 8. DD-03182VP PIN CONFIGURATION 7 PIN 1 DIMENSIONS ARE IN INCHES (mm) 0.181 - 0.205 (4.597 - 5.207) 0.150 - 0.158 (3.810 - 4.013) 0.228 - 0.244 (5.791 - 6.198) 0.018 - 0.022 (0.457 - 0.559) 0.336 - 0.344 (8.534 - 8.737) 0.053 - 0.069 (1.346 - 1.753) 3˚ - 6˚ 0.007 - 0.009 (0.178 - 0.229) 0.05 (1.270) BSC 0.014 - 0.018 (0.356 - 0.457) 0.004 - 0.008 (0.102 - 0.203) FIGURE 10. DD-03182VP 14-PIN SURFACE MOUNT (SOIC) MECHANICAL OUTLINE DIMENSIONS ARE IN INCHES (mm) LEAD #1 0.785 MAX (19.94) 0.025 RAD (0.64) 0.291 MAX (7.39) 0.050 MAX (1.27) 0.160 MAX (4.06) 0.290 - 0.320 (7.37 - 8.13) 0.060 ±0.005 (1.52 ±0.13) 0.125 MIN (3.18) 0 - 10 deg. 0.008 - 0.012 (0.20 - 0.30) 0.020 - 0.070 (0.51 - 1.78) 0.100 ±0.010 (2.54 ±0.25) 0.018 ±0.002 (0.46 ±0.05) 0.385 ±0.025 (9.78 ±0.64) FIGURE 11. DD-03182DC CERAMIC DIP (JE) MECHANICAL OUTLINE 8 PIN 1 DIMENSIONS ARE IN INCHES (mm) LEAD COPLANARITY 0.004 MAX 0.026 MIN 0.032 MAX (0.66 MIN 0.81 MAX) 0.291 MIN 0.300 MAX (7.39 MIN 7.62 MAX) 0.397 MIN 0.413 MAX (10.08 MIN 10.49 MAX) 0.092 MIN 0.094 MAX (2.34 MIN 2.39 MAX) 0.007 MIN 0.013 MAX (0.18 MIN 0.33 MAX) 0.047MIN 0.053 MAX (1.19 MIN 1.35 MAX) 0.015 MIN 0.050 MAX (0.38 MIN 1.27 MAX) 0.393 MIN 0.420 MAX (9.98 MIN 10.67 MAX) 0.014 MIN 0.019 MAX (0.36 MIN 0.48 MAX) 0.003 MIN 0.012 MAX (0.076 MIN 0.30 MAX) FIGURE 12. DD-03182GP 16-PIN SURFACE MOUNT (SOIC) MECHANICAL OUTLINE ORIENTATION MARK DENOTES PIN 1 ±0.005 0.490 [12.45)] 0.175 [4.45] ±0.002 0.454 [11.53] 0.100 [2.54] 0.018 [0.46] MIN 1 ±0.002 0.490 [12.45] 6 EQ. SP @ 0.050 = 0.300 (TOL NONCUM) (TYP) 1 ±0.002 0.454 [11.53] 0.029 [0.74] (TYP) 0.050 [1.27] (TYP) ±0.020 0.410 [10.41] 0.020 [0.51] MIN Notes: 1. LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010. 2. DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS]. FIGURE 13. DD-03182PP PLCC MECHANICAL OUTLINE 9 ORDERING INFORMATION OTHER APPLICABLE DOCUMENTS DD-03182XX-XXXX – ARINC 429 Line Driver RTCA/DO-160D: Environmental Conditions and Test Procedure for Airborne Equipment T = Tape and Reel (GP and VP only) ARINC Specification 429 Mark 33 Digital Information Transfer System Options: 0 = With resistors and fuses 1 = With resistors, no fuses* Screening: 0 = Standard DDC Procedures 2 = Burn-in (DC and GP only) Temperature Range: 1 = -55 to +125°C (ceramic only) 2 = -40 to +85°C 9 = -55 to +85°C (GP package only) Package Style/Type: DC = 16-pin ceramic DIP GP = 16-pin plastic SOIC PP = 28-pin plastic PLCC VP = 14-Pin plastic SOIC *VP version only. 10 NOTES 11 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7402 Headquarters - Tel: (631) 567-5600 ext. 7402, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com ILC DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 J-09/99-1M PRINTED IN THE U.S.A. 12