ETC DM1M36SJ6-15

Enhanced
Memory Systems Inc.
DM1M36SJ6/DM1M32SJ6 Multibank EDO
1Mbx36/1Mbx32 Enhanced DRAM
SIMM
Product Specification
Features
Architecture
The DM1M36SJ achieves
1Mb x 36 density by mounting
nine 1Mb x 4 EDRAMs,
packaged in 28-pin plastic
SOJ packages, on a multilayer substrate. Eight DM2242
devices and one DM2252
device provide data and parity
storage. The DM1M32SJ6
contains eight DM2242
devices for data only.
The EDRAM memory
module architecture is very
similar to a standard 4MB
DRAM module with the
addition of an integrated
cache and on-chip control
Description
which allows it to operate much like an EDO DRAM.
The Enhanced Memory Systems Multibank EDO 4MB EDRAM
The EDRAM’s SRAM cache is integrated into the DRAM array as
SIMM module provides a single memory module solution for the
tightly coupled row registers. The EDRAM has a total of four
main memory or local memory of fast PCs, workstations, servers, and independent DRAM memory banks each with its own SRAM row
other high performance systems. Due to its fast 12ns cache row
register. Memory reads always occur from the cache row register of
register, the EDRAM memory module supports zero-wait-state burst
one of these banks as specified by row address bits A2 and A9 (bank
read operations at up to 83MHz bus rates in a non-interleave
select). When the internal comparator detects that the row address
configuration and 132MHz bus rates with a two-way interleave configuration. matches the last row read from any of the four DRAM banks (page
On-chip write posting and fast page mode operation supports
hit), the SRAM is accessed and data is available on the output pins in
12ns write and burst write operations. On a cache miss, the fast
12ns from the column address input. Subsequent reads within the
DRAM array reloads the 2KByte cache over a 2KByte-wide bus in 18ns page (burst reads or random reads) can continue at 12ns cycle time.
for an effective bandwidth of 113.6 Gbytes/sec. This means very low
When the row address does not match the last row read from any of
latency and fewer wait states on a cache miss than a non-integrated
the last four DRAM banks (page miss), the new DRAM row is
cache/DRAM solution. The JEDEC compatible 72-bit SIMM
accessed and loaded into the appropriate SRAM row register and data
configuration allows a single memory controller to be designed to
is available on the output pins all within 30ns from row enable.
support either JEDEC slow DRAMs or high speed EDRAMs to provide Subsequent reads within the page (burst reads or random reads) can
a simple upgrade path to higher system performance.
continue at 12ns cycle time.
Since reads occur from the SRAM
cache, the DRAM precharge can occur
Functional Diagram
during burst reads. This eliminates the
A 0-8
Column
precharge time delay suffered by other
/CAL 0-3,P
Add
Column Decoder
DRAMs and SDRAMs when accessing a
Latch
4-512 X 36 Cache Pages
new page. The EDRAM has an
(Row Registers)
11-Bit
independent on-chip refresh counter and
Comp
dedicated refresh control pin to allow the
Sense Amps
/G
& Column Write Select
DRAM array to be refreshed concurrently
I/O
Last
Control
A 0-10
with cache read operations (hidden
Row
DQ 0-35
and
Read
Data
refresh).
Add
Latches
Latch
Memory writes are posted to the
/S
data latch and directed to the DRAM
Memory
Row
Array
/WE
Add
array. During a write hit, the on-chip
2048 x 512 x 36
Latch
address comparator activates a parallel
write path to the SRAM cache to maintain
coherency. Random or page mode writes
V
can be posted 5ns after column address
A 0-9
C
8KByte SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
■ Fast DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes
■ Hidden Precharge and Refresh Cycles
■ Extended 64ms Refresh Period for Low Standby Power
■ Standard CMOS/TTL Compatible I/O Levels and +5 or 3.3V Volt Supply
■ Compatibility with JEDEC 1M x 36 DRAM SIMM Configuration
Allows Performance Upgrade in System
■ Multibank Extended Data Output (EDO) for Faster System Operation
■ Low Power, Self Refresh Option
■ Industrial Temperature Range Option
Row Decoder
■
CC
/F
W/R
/RE 0,2
Row Add
and
Refresh
Control
1-9
Refresh
Counter
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
VSS
© 1996 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM, Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2118-000
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A2,9 (LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the column address is available at the output pins at
Functional Description
the greater of times tRAC1, tAC, tGQV, and tASC +tCLV.. Since no DRAM
activity is initiated, /RE can be brought high after time tRE1, and a
The EDRAM is designed to provide optimum memory
shorter precharge time, tRP1, is required. It is possible to access
performance with high speed microprocessors. As a result, it is
additional
SRAM cache locations by providing new column
possible to perform simultaneous operations to the DRAM and
addresses
to
the multiplex address inputs. New data is available at
SRAM cache sections of the EDRAM. This feature allows the EDRAM
the
output
at
time tASC +tCLV after each column address change.
to hide precharge and refresh operation during SRAM cache reads
and maximize SRAM cache hit rate by maintaining valid cache
DRAM Read Miss
contents during write operations even if data is written to another
A DRAM read request is initiated by clocking /RE with W/R low
memory page. These new functions, in conjunction with the faster and /F high. The EDRAM will compare the new row address to the
basic DRAM and cache speeds of the EDRAM, minimize processor LRR address latch for the bank specified by row address bits A
2,9
wait states.
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
EDRAM Basic Operating Modes
address does not match the LRR, the requested data is not in SRAM
The EDRAM operating modes are specified in the table below. cache and a new row must be fetched from the DRAM. The EDRAM
will load the new row data into the SRAM cache and update the
Hit and Miss Terminology
LRR latch. The data at the specified column address is available at
In this datasheet, “hit” and “miss” always refer to a hit or miss the output pins at the greater of times t t t and t
RAC, AC, GQV,
ASC +tCLV. It
to any of the four pages of data contained in the SRAM cache row
is possible to bring /RE high after time tRE since the new row data is
registers. There are four cache row registers, one for each of the
safely latched into SRAM cache. This allows the EDRAM to
four banks of DRAM. These registers are specified by the bank
precharge the DRAM array while data is accessed from SRAM
select row address bits A2 and A9. The contents of these cache row cache. It is possible to access additional SRAM cache locations by
registers is always equal to the last row that was read from each of providing new column addresses to the multiplex address inputs.
the four internal DRAM banks (as modified by any write hit data). New data is available at the output at time t
ASC +tCLV after each
column address change.
and data are available. The EDRAM allow 12ns page mode cycle
time for both write hits and write misses. Memory writes do not
affect the contents of the cache row register except during a cache
hit. By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
A0-10
Column Address Latch
Row Address Latch
Bank 0
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA0-10
CA0-8
1MB Array
1MB Array
1MB Array
1MB Array
D0-35
Data-In
Latch
CA0-8
512 x 36
Cache
512 x 36
Cache
Bank 0
512 x 36
Cache
Bank 1
(0,0)
Bank 2
(0,1)
(1,0)
1 of 4 Selector
RA2, RA9
CAL
Data-Out
Latch
G
S
Q 0-35
2-76
512 x 36
Cache
Bank 3
(1,1)
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
W/E, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A2,9 (LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low (both /CAL and /WE must be high
when initiating the write cycle with the falling edge of /RE). The
write address and data can be latched very quickly after the fall of
/RE (tRAH + tASC for the column address and tDS for the data).
During a write burst sequence, the second write data can be posted
at time tRSW after /RE. Subsequent writes within a page can occur
with write cycle time tPC. With /G enabled and /WE disabled, it is
possible to perform cache read operations while the /RE is
activated in write hit mode. This allows read-modify-write, writeverify, or random read-write sequences within the page with 12ns
cycle times (the first read cannot complete until after time tRAC2).
At the end of a write sequence (after /CAL and /WE are brought
high and tRE is satisfied), /RE can be brought high to precharge the
memory. It is possible to perform cache reads concurrently with
precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, the /CAL
input can be used as a byte write select in multi-chip systems. If /CAL
is not clocked on a write sequence, the memory will perform a /RE only
refresh to the selected row and data will remain unmodified.
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
W/E, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
address bits A2,9 (LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified.The write address
and data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (tRAH + tASC for
the column address and tDS for the data). During a write burst
sequence, the second write data can be posted at time tRSW after
/RE. Subsequent writes within a page can occur with write cycle
time tPC. During a write miss sequence, cache reads are inhibited
and the output buffers are disabled (independently of /G) until
time tWRR after /RE goes high. At the end of a write sequence (after
/CAL and /WE are brought high and tRE is satisfied), /RE can be
brought high to precharge the memory. It is possible to perform
cache reads concurrently with the precharge. During write
sequences, a write operation is not performed unless both /CAL
and /WE are low. As a result, /CAL can be used as a byte write select
in multi-chip systems. If /CAL is not clocked on a write sequence,
the memory will perform a /RE only refresh to the selected row and
data will remain unmodified.
/RE Inactive Operation
It is possible to read data from the SRAM cache without
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/miss comparison. In this case, the
controller can avoid the time required to perform row/column
multiplexing on hit cycles. This capability also allows the EDRAM to
perform cache read operations during precharge and refresh
cycles to minimize wait states. It is only necessary to select /S and
/G and provide the appropriate column address to read data. The
row address of the SRAM cache accessed without clocking /RE will
be specified by the LRR address latch loaded during the last /RE
active read cycle. To perform a cache read, /CAL is clocked to latch the
column address. The cache data is valid at time tCLV after the column
address is setup to /CAL.
Write-Per-Bit Operation
The DM1M36SJ6 EDRAM SIMM provides a write-per-bit
capability to selectively modify individual parity bits (DQ8,17,26,35)
for byte write operations. The parity device (DM2252) is selected
via /CALP. Data bits do not require or support write-per-bit
capability. Byte write selection to non-parity bits is accomplished
via /CAL0-3. The bits to be written are determined by a bit mask data
word which is placed on the parity I/O data pins prior to clocking
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
removed and write data can be placed on the databus. The mask is
EDRAM Basic Operating Modes
Function
/S
/RE
W/R
/F
/CAL
/WE
A0-10
Read Hit
L
↓
L
H
H
X
Row = LRR
No DRAM Reference, Data in Cache
Read Miss
L
↓
L
H
H
X
Row ≠ LRR
DRAM Row to Cache
Write Hit
L
↓
H
H
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
↓
H
H
H
H
Row ≠ LRR
Write to DRAM, Cache Not Updated, Reads Disabled
Internal Refresh
X
↓
X
L
X
X
X
Cache Reads Enabled
Low Power Standby
H
H
X
X
H
H
X
Standby Current
Unallowed Mode
H
L
X
H
X
X
X
Unallowed Mode (Except -L Option)
Low Power Self
Refresh Option
H
↓
X
H
L
H
X
Standby Current, Internal Refresh Clock
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
2-77
Comment
only specified on the /RE transition. During page mode burst write
operations, the same mask is used for all write operations.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles during which /S can be disabled.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
Reduced Pin Count Operation
It is possible to simplify the interface to the 4MByte SIMM to
reduce the number of control lines. /RE0 and /RE2 could be tied
together externally to provide a single row enable. W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
Pin Descriptions
/RE0,2 — Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address as well as the states of W/R and /F. It is not
necessary to clock /RE to read data from the EDRAM SRAM row
registers. On read operations, /RE can be brought high as soon as
data is loaded into cache to allow early precharge.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter
is the recommended method of EDRAM refresh, it is
possible to perform an /RE only refresh using an
externally supplied row address. /RE refresh is performed
by executing a write cycle (W/R and /F are high) where /CAL is
not clocked. This is necessary so that the current cache contents
and LRR are not modified by the refresh operation. All
combinations of addresses A0-9 must be sequenced every 64ms
refresh period. A10 does not need to be cycled. Read refresh cycles
are not allowed because a DRAM refresh cycle does not occur
when a read refresh address matches the LRR address latch.
/CAL0-3,P — Column Address Latch
This input is used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address is closed and the output of the latch contains
the address present while /CAL was high. It also controls the
operation of the output data latch. Data is latched while /CAL is
high, and the latch is transparent when /CAL is low.
+3.3 Volt Power Supply Operation
If the +3.3 volt power supply option is specified, the EDRAM
will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAM will not accept input levels which exceed the
power supply voltage. If mixed I/O levels are expected in your
system, please specify the +5 volt version of the EDRAM.
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce standby
current.
/G — Output Enable
This input controls the gating of read data to the output data
pin during read operations.
Low Power, Self-Refresh Option
When the low power, self refresh mode option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
mode, the power is turned off to all I/O pins except /RE to minimize
chip power, and an on-board refresh clock is enabled to perform
self-refresh cycles using the on-board refresh counter. The EDRAM
remains in this low power mode until /RE is brought high again to
terminate the mode. The EDRAM /RE input must remain high for tRP2
following exit from self-refresh mode to allow any on-going internal
refresh to terminate prior to the next memory operation.
Initialization Cycles
A minimum of eight /RE active initialization cycles (read, write
or refresh)are required before normal operation is guaranteed.
Following these start-up cycles, two read cycles to different row
addresses must be performed for each of the four internal banks
of DRAM to initialize the internal cache logic. Row address bits A2
and A9 define the four internal DRAM banks. /RE must be high for
300ns prior to initialization.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
Unallowed Mode
Read, write, or /RE only refresh operations must not be initiated
to unselected memory banks by clocking /RE when /S is high.
DQ0-35 — Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM2252 write-per-bit memory, these pins
are also used to specify the bit mask used during write operations.
A0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 9-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
VCC Power Supply
These inputs are connected to the +5 or 3.3 volt power supply.
VSS Ground
These inputs are connected to the power supply ground
connection.
2-78
44
34
/RE0
/RE2
VCC
VCC
VCC
VCC
VCC
1
29
39
71
72
VSS
VSS
VSS
VSS
VSS
70
PD
DQ 35
/CAL2
/CAL3
/CALP
C2
C3
C4
C5
C6
C7
C8
C9
*DM2252 is not present on the DM1M32SJ.
2-79
24
25
/RE
6
/CAL
16
/CAL1
C1
DQ3
DQ2
DQ1
DQ0
/RE
6
/CAL
16
/RE
6
/CAL
16
/RE
6
/CAL
16
/RE
26
34
24
DQ3
25
DQ2
26
DQ1
DQ0
24
DQ3
DQ2
25
26
DQ1
DQ0
24
DQ3
6
6
/CAL
16
/RE
/CAL
16
/RE
6
/CAL
16
DQ3
25
DQ2
26
DQ1
DQ0
27
27
27
27
33
32
DQ 31
30
29
28
27
25
26
24
23
DQ 22
21
24
25
DQ2
27
26
DQ1
DQ0
24
DQ3
25
DQ2
27
26
DQ1
DQ0
25
24
DQ3
DQ2
26
DQ1
DQ0
27
/RE
6
/CAL0
+5V (+3.3V)
10
11
30
59
66
20
19
DQ 18
16
17
15
14
DQ 13
12
11
9
10
7
8
6
24
DQ3
26
25
DQ2
DQ1
DQ0
24
DQ3
DQ2
EDRAM
16
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
EDRAM
DM2242J
1Mb x 4
/RE
W/R
/WE
/F
/S
/G
EDRAM
EDRAM
8
VSS 21
VSS 28
VSS
EDRAM
6
17
20
18
19
23
EDRAM
EDRAM
DM2242J
1Mb x 4
EDRAM
DM2242J
1Mb x 4
DM2242J
1Mb x 4
DM2242J
1Mb x 4
/CAL
W/R
/WE
/F
/S0
/G
Byte 2
EDRAM
DM2242J
1Mb x 4
DM2242J
1Mb x 4
7
VCC
14
VCC
22
VCC
DM2252J
1Mb x 4
DM2242J
1Mb x 4
Byte 3
U1
Byte 1
Byte 4
U2
U9
U3
16
48
47
68
69
67
25
27
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
U4
+5V (+3.3V)
Parity
U5
*
U8
U7
U6
/CAL
1
2
12
3
4
5
9
10
11
13
15
26
27
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DQ1
DQ0
12
13
14
15
16
17
18
28
31
32
19
40
43
41
42
46
5
3
DQ 4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
2
4
6
8
20
22
24
26
36
49
51
53
55
57
61
63
65
37
3
5
7
9
21
23
25
27
35
50
52
54
56
58
60
62
64
38
2
DQ 0
Edge
Connecter
J1
1
Interconnect Diagram
Pinout
Interconnect
Pin No. Function (Component Pin)
Organization
Interconnect
Pin No. Function (Component Pin)
Organization
1
GND
C (8, 21, 28)
Ground
37
DQ17*
U5 (25)
Parity I/O for Byte 2
2
DQ0
U1 (27)
Byte 1 I/O 1
38
DQ35*
U5 (24)
Parity I/O for Byte 4
3
DQ18
U2 (24)
Byte 3 I/O 1
39
GND
C (8, 21, 28)
Ground
4
DQ1
U1 (26)
Byte 1 I/O 2
40
/CAL 0
U1,3 (16)
Byte 1 Column Address Latch
5
DQ19
U2 (25)
Byte 3 I/O 2
41
/CAL 2
U2,4 (16)
Byte 3 Column Address Latch
6
DQ2
U1 (25)
Byte 1 I/O 3
42
/CAL 3
U7,8 (16)
Byte 4 Column Address Latch
7
DQ20
U2 (26)
Byte 3 I/O 3
43
/CAL 1
U6,9 (16)
Byte 2 Column Address Latch
8
DQ3
U1 (24)
Byte 1 I/O 4
44
/RE0
U1,3,6,9 (6)
Row Enable (Bytes 1,2)
9
DQ21
U2 (27)
Byte 3 I/O 4
45
NC
10
+5/3.3 V
C (7, 14, 22)
VCC
46
/CAL P*
U5 (16)
Parity Column Address Latch
11
+5/3.3 V
C (7, 14, 22)
VCC
47
/WE
C (20)
Write Enable
12
A0
C (1)
Address
48
W/R
C (17)
W/R Mode Control
13
A1
C (2)
Address
49
DQ9
U6 (27)
Byte 2 I/O 1
14
A2
C (12)
Address
50
DQ27
U7 (27)
Byte 4 I/O 1
15
A3
C (3)
Address
51
DQ10
U6 (26)
Byte 2 I/O 2
16
A4
C (4)
Address
52
DQ28
U7 (26)
Byte 4 I/O 2
17
A5
C (5)
Address
53
DQ11
U6 (25)
Byte 2 I/O 3
18
A6
C (9)
Address
54
DQ29
U7 (25)
Byte 4 I/O 3
19
A 10
C (15)
Address
55
DQ12
U6 (24)
Byte 2 I/O 4
20
DQ4
U3 (27)
Byte 1 I/O 5
56
DQ30
U7 (24)
Byte 4 I/O 4
21
DQ22
U4 (24)
Byte 3 I/O 5
57
DQ13
U9 (24)
Byte 2 I/O 5
22
DQ5
U3 (26)
Byte 1 I/O 6
58
DQ31
U8 (27)
Byte 4 I/O 5
23
DQ23
U4 (25)
Byte 3 I/O 6
59
+5/3.3 V
C (7, 14, 22)
VCC
24
DQ6
U3 (25)
Byte 1 I/O 7
60
DQ32
U8 (26)
Byte 4 I/O 6
25
DQ24
U4 (26)
Byte 3 I/O 7
61
DQ14
U9 (25)
Byte 2 I/O 6
26
DQ7
U3 (24)
Byte 1 I/O 8
62
DQ33
U8 (25)
Byte 4 I/O 7
27
DQ25
U4 (27)
Byte 3 I/O 8
63
DQ15
U9 (26)
Byte 2 I/O 7
28
A7
C (10)
Address
64
DQ34
U8 (24)
Byte 4 I/O 8
29
GND
C (8, 21, 28)
Ground
65
DQ16
U9 (27)
Byte 2 I/O 8
30
+5/3.3 V
C (7, 14, 22)
VCC
66
+5/3.3 V
C (7, 14, 22)
VCC
31
A8
C (11)
Address
67
/G
C (23)
Output Enable
32
A9
C (13)
Address
68
/F
C (18)
Refresh Mode Control
33
NC
Reserved for 2Mb x 36
69
/S
C (19)
Chip Select
34
/RE2
U2,4,5,7,8 (6)
Row Enable (Bytes 3,4, Parity)
70
PD
Signal GND
Presence Detect
35
DQ26*
U5 (27)
Parity I/O for Byte 3
71
GND
C (8, 21, 28)
Ground
36
DQ8 *
U5 (26)
Parity I/O for Byte 1
72
GND
C (8, 21, 28)
Ground
Reserved for 2Mb x 36
*No Connect for DM1M32SJ
C = Common to All Memory Chips, U1 = Chip 1, etc.
2-80
Absolute Maximum Ratings
Capacitance
(Beyond Which Permanent Damage Could Result)
3.3V Option
Rating
Ratings
Input Voltage (VIN)
- .5 ~ 4.6v
- 1 ~ 7v
Output Voltage (VOUT)
- .5 ~ 4.6v
- 1 ~ 7v
Power Supply Voltage (VCC)
- .5 ~ 4.6v
- 1 ~ 7v
Ambient Operating Temperature (TA)
-40 ~ +85°C
-40 ~ +85°C
Storage Temperature (TS)
-55 ~ 150°C
-55 ~ 150°C
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
Class 1
Short Circuit O/P Current (IOUT)
20mA*
50mA*
Description
* One output at a time per device; short duration
Description
Max*
Input Capacitance
66/73pf
A0-9
Input Capacitance
90/96pf
A10, W/R, /WE, /F, /S
Input Capacitance
45pf
/RE0
Input Capacitance
46/56pf
/RE2
Input Capacitance
26/28pf
/G
Input Capacitance
27pf
/CAL0-3
Input Capacitance
16pf
/CALP
I/O Capacitance
8pf
DQ0-35
* DM1M32SJ/DM1M36SJ, respectively
AC Test Load and Waveforms
Load Circuit
VIN Timing Reference Point at VIL and VIH
Input Waveforms
+ 5.0 (+3.3 Volt Option)
Output
R2 = 295Ω (5.0 volt)
R1 = 828Ω
R1 = 1178Ω
Pins
VIH
(5.0 volt)
(3.3 Volt Option)
CL = 50pf
GND
VIL
VIL
≤5ns
R2 = 868Ω (3.3 Volt Option)
2-81
VIH
≤5ns
Electrical Characteristics
TA = 0 - 70°C (Commercial), -40 to 85°C (Industrial)
Symbol
3.3V Option
Parameters
Min
Max
Min
Max
VCC
Supply Voltage
3.0V
3.6V
4.75V
5.25V
VIH
Input High Voltage
2.0V
VCC+0.3V
2.4V
Vcc+0.5V
VIL
Input Low Voltage
Vss-0.3V
0.8V
Vss-0.5V
0.8V
VOH
Output High Level
2.4V
VOL
Output Low Level
Ii(L)
Input Leakage Current
-45µA
45µA
IO(L)
Output Leakage Current
-45µA
45µA
Test Conditions
All Voltages Referenced to VSS
IOUT = - 5mA (-2ma For 3.3 Volt Option)
2.4V
0.4V
IOUT = 4.2mA (2ma For 3.3 Volt Option)
-90µA
90µA
OV ≤ VIN ≤ Vcc + 0.5 Volts
-90µA
90µA
O ≤ VI/O ≤ Vcc
0.4V
Operating Current — DM1M32SJ
Symbol
Operating Current
33MHz Typ (1) -12 Max
-15 Max
Test Condition
Notes
ICC1
Random Read
880mA
1800mA
1440mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
520mA
1160mA
920mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
440mA
880mA
720mA
/G and Addresses Cycling: t SC = t SC Minimum
2, 4
ICC4
Random Write
1080mA
1520mA
1200mA
/RE, /CAL, /WE and Addresses Cycling: t C = t C Minimum
2, 3
ICC5
Fast Page Mode Write
400mA
1080mA
840mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
8mA
8mA
8mA
ICC7
Self-Refresh (-L Option)
1.6mA
1.6mA
1.6mA
ICCT
Average Typical
Operating Current
240mA
—
—
See "Estimating EDRAM Operating Power" Application Note
1
33MHz Typ (1)
-12 Max
-15 Max
Test Condition
Notes
All Control Inputs Stable ≥ V CC - 0.2V
/S, /F, W/R, /WE and A0-10 at ≥ VCC -0.2V,
/RE and /CAL at <V SS + 0.2V, I/O Open
Operating Current — DM1M36SJ
Symbol
Operating Current
ICC1
Random Read
990mA
2025mA
1620mA
/RE, /CAL, and Addresses Cycling: tC = tC Minimum
2, 3, 5
ICC2
Fast Page Mode Read
585mA
1305mA
1035mA
/CAL and Addresses Cycling: tPC = tPC Minimum
2, 4, 5
ICC3
Static Column Read
495mA
990mA
810mA
Addresses Cycling: tSC = tSC Minimum
2, 4, 5
ICC4
Random Write
1215mA
1710mA
1350mA
/RE, /CAL, /WE, and Addresses Cycling: tC = tC Minimum
2, 3
ICC5
Fast Page Mode Write
450mA
1215mA
945mA
/CAL, /WE, and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
9mA
9mA
9mA
All Control Inputs Stable ≥ VCC - 0.2V, Output Driven
ICC7
Self-Refresh
Option (-L)
1.8mA
1.8mA
1.8mA
270mA
—
—
ICCT
Average Typical
Operating Current
/S, /F, W/R, /WE, and A0-10 at ≥ VCC - 0.2V
/RE and /CAL at ≤ VSS + 0.2V, I/O Open
See “Estimating EDRAM Operating Power” Application Note
1
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed. (2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) ICC is measured with a maximum of one address change while
/RE = VIL. (4) ICC is measured with a maximum of one address change while /CAL = VIH. (5) /G is high.
2-82
Switching Characteristics
VCC = 5V ± 5% (+5 Volt Option), Vcc = 3.3V ± 0.3V (+3.3 Volt Option), CL = 50pf, TA = 0 to 70°C (Commercial), -40 to 85°C (Industrial)
-12
Symbol
Description
Min
-15
Max
Min
Max
Units
tAC(1)
Column Address Access Time
tACH
Column Address Valid to /CAL Inactive (Write Cycle)
12
15
ns
tACI
Column Address
12
15
ns
tAQX
Column Address Change to Output Data Invalid
5
5
ns
tASC
Column Address Setup Time
5
5
ns
tASR
Row Address Setup Time
5
5
ns
tC
Row Enable Cycle Time
55
65
ns
tC1
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
20
25
ns
tCAE
Column Address Latch Active Time
5
6
ns
tCAH
Column Address Hold Time
0
0
ns
tCH
Column Address Latch High Time (Latch Transparent)
5
5
ns
tCHR
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
ns
tCHW
Column Address Latch High to Write Enable Low (Multiple Writes)
0
0
ns
tCLV
Column Address Latch Low to Data Valid
tCQH
Column Address Latch Low to Data Invalid
tCQV
Column Address Latch High to Data Valid
tCRP
Column Address Latch Setup Time to Row Enable
5
5
ns
tCWL
/WE Low to /CAL Inactive
5
5
ns
tDH
Data Input Hold Time
0
0
ns
tDMH
Mask Hold Time From Row Enable (Write-Per-Bit)
1
1.5
ns
tDMS
Mask Setup Time to Row Enable (Write-Per-Bit)
5
5
ns
tDS
Data Input Setup Time
5
5
ns
tGQV(1)
Output Enable Access Time
tGQX(2,3)
Output Enable to Output Drive Time
0
5
tGQZ
Output Turn-Off Delay From Output Disabled (/G↑)
0
5
tMH
/F and W/R Mode Select Hold Time
0
0
ns
tMSU
/F and W/R Mode Select Setup Time
5
5
ns
tNRH
/CAL, /G, W/R, and /WE Hold Time For /RE-Only Refresh
0
0
ns
tNRS
/CAL, /G, W/R, and /WE Setup Time For /RE-Only Refresh
5
5
ns
tPC
Column Address Latch Cycle Time
12
15
ns
(4,5)
(1)
tRAC
12
15
7
3
7
3
15
ns
ns
ns
15
ns
5
ns
0
5
ns
0
5
ns
5
Row Enable Access Time, On a Cache Miss
30
35
ns
tRAC1
Row Enable Access Time, On a Cache Hit (Limit Becomes tAC)
15
17
ns
tRAC2(1,6)
Row Enable Access Time for a Cache Write Hit
30
35
ns
tRAH
Row Address Hold Time
1
tRE
Row Enable Active Time
30
(1)
2-83
1.5
100000
35
ns
100000
ns
Switching Characteristics (continued)
VCC = 5V ± 5% (+5 Volt Option), Vcc = 3.3V ± 0.3V (+3.3 Volt Option), CL = 50pf, TA = 0 to 70°C (Commercial), -40 to 85°C (Industrial)
-12
Symbol
Description
Min
tRE1
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
tREF
Refresh Period
tRGX
Max
Min
tRQX1
Row Enable High to Output Turn-On After Write Miss
0
tRP(7)
Row Precharge Time
tRP1
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
tRP2
Row Precharge Time, Self-Refresh Mode
tRRH
Read Hold Time From Row Enable (Write Only)
tRSH
10
12
0
Units
ns
64
64
9
Max
10
8
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
(2,6)
-15
ms
ns
15
ns
20
25
ns
8
10
ns
100
100
ns
0
0
ns
Last Write Address Latch to End of Write
12
15
ns
t RSW
Row Enable to Column Address Latch Low For Second Write
35
40
ns
tRWL
Last Write Enable to End of Write
12
15
ns
tSC
Column Address Cycle Time
12
15
ns
tSHR
Select Hold From Row Enable
0
0
ns
tSQV(1)
Chip Select Access Time
tSQX(2,3)
Output Turn-On From Select Low
0
12
tSQZ(4,5)
Output Turn-Off From Chip Select
0
8
tSSR
Select Setup Time to Row Enable
5
tT
Transition Time (Rise and Fall)
1
tWC
Write Enable Cycle Time
tWCH
15
ns
0
15
ns
0
10
ns
12
5
10
1
ns
10
ns
12
15
ns
Column Address Latch Low to Write Enable Inactive Time
5
5
ns
tWHR(7)
Write Enable Hold After /RE
0
0
ns
tWI
Write Enable Inactive Time
5
5
ns
tWP
Write Enable Active Time
5
5
ns
tWQV(1)
Data Valid From Write Enable High
tWQX(2,5)
Data Output Turn-On From Write Enable High
0
12
tWQZ(3,4)
Data Turn-Off From Write Enable Low
0
12
tWRP
Write Enable Setup Time to Row Enable
5
tWRR
Write to Read Recovery (Following Write Miss)
15
ns
0
15
ns
0
15
ns
12
5
16
(1) VOUT Timing Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL
(3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL
(5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to tRAC2
(7) For Back-to-Back /F Refreshes, tRP = 40ns. For Non-consecutive /F Refreshes, tRP = 25ns and 32ns Respectively
(8) For Write-Per-Bit Devices, tWHR is Limited By Data Input Setup Time, tDS
2-84
ns
18
ns
/RE Inactive Cache Read Hit
/RE
0,2
/F
W/R
t ACI
A0-10
t CAH
Column 1
Column 2
t ASC
t CAH
t CAE
/CAL0-3, P
Row
t ASC
t CH
t PC
t CQV
/WE
t CLV
DQ0-35
Open
t AC
t CLV
t CQH
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SQX
t SQV
t SQZ
/S
Don’t Care or Indeterminate
Notes: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2. Latched data becomes invalid when /S is inactive.
2-85
/RE Active Cache Read Hit
t C1
t RE1
/RE0,2
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t ACI
t RAH
A0-10
Row
t CAH
Column 1
Column 2
t CRP
Row
t ASC
t ASC
t CAH
t CH
t CAE
/CAL0-3,P
t PC
t CQV
/WE
t CLV
t RAC1
DQ0-35
Open
t AC
t CLV
t CQH
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
Don’t Care or Indeterminate
Note: 1. Latched data becomes invalid when /S is inactive.
2-86
/RE Active Cache Read Miss
tC
t RE
/RE0,2
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t ACI
t RAH
A0-10
Row
t CAH
Column 1
Column 2
t ASC
Row
t ASC
t CRP
t CAH
t CH
t CAE
/CAL0-3,P
t
PC
t CQV
/WE
t CLV
t RAC
Open
DQ0-35
t CLV
t AC
t CQH
Data 1
Data 2
t AC
t GQZ
/G
t SSR
t GQX
t SHR
t GQV
t SQZ
/S
Don’t Care or Indeterminate
Note: 1. Latched data becomes invalid when /S is inactive.
2-87
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE0,2
t MSU
t RP
t MH
t CHR
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-8
A0-10
Row
t RSW
A0-8
Column 1
A0-10
t ASC
t CRP
t CAH
/CAL0-3,P
t CAE
t CWL
DQ0-35
Open
t CAE
t CH
t PC
t CHW
t CAH
t CWL
t CAE
t WCH
t RRH
t WP
/WE
t DS
Column n
t RSH
t WP
t WHR
A0-8
Column 2
t ACH
t ACH
t WCH
t WRP
t ASC
t CAH
t WC
t DH
t WI
t RWL
t DH
t DS
Data 1
Data 2
t CLV
t WRR
t AC
Cache (Column n)
t RQX1
t GQX
/G
t GQV
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. Parity bits DQ8,17,26,35 must have mask provided at falling edge of /RE.
2. /G becomes a don’t care after tRGX during a write miss.
2-88
Page Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
t RE
/RE0, 2
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t AC
t ASR
t RAH
A0-10
Row
t CAH
Column 1
t ASC
t CAH
t ASC
t CAE
t CLV
t CRP
/CAL0-3,P
Column 2
t ACH
Column 3
t RSH
t CAE
t WHR
t CLV
t RWL
t AC
t WQV
Read Data
Write Data
t DH
t DS
t GQX
Read Data
t WQX
t GQZ
t GQV
t GQZ
/G
t RRH
t WP
t RAC2
t CQH
t CQV
t CWL
/WE
DQ0-35
t CHR
t CAE
t WCH
t WRP
t CQX
t CAH
t ASC
t GQV
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2. Parity bits DQ
must have mask provided at falling edge of /RE.
8,17,26,35
2-89
Write-Per-Bit Cycle (/G = High)
tC
t RE
/RE0, 2
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t AC
t ASR
t RAH
A0-10
Row
t CAH
Column 1
t ASC
t CAH
t ASC
t CAE
t CLV
t CRP
/CAL0-3,P
Column 2
t ACH
Column 3
t RSH
t CAE
t WHR
t CLV
t RWL
t AC
t WQV
Read Data
Write Data
t DH
t DS
t GQX
Read Data
t WQX
t GQZ
t GQV
t GQZ
/G
t RRH
t WP
t RAC2
t CQH
t CQV
t CWL
/WE
DQ0-35
t CHR
t CAE
t WCH
t WRP
t CQX
t CAH
t ASC
t GQV
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2. Parity bits DQ
must have mask provided at falling edge of /RE.
8,17,26,35
2-90
/F Refresh Cycle
t RE
/RE0, 2
t MSU
t RP
t MH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
t RE
/RE0,2
tC
t RP
t ASR
t RAH
A 0-10
Row
t NRS
t NRH
/CAL0-3,P, /WE, /G
t MSU
t MH
W/R, /F
t SSR
t SHR
/S
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
2-91
Low Power Self-Refresh Mode Option
/RE
0,2
t RP2
A 0-10
t MSU
t MH
/CAL
0-3, P
t MSU
/F, W/R,
/WE, /S
t MH
Don’t Care or Indeterminate
NOTES: 1. EDRAM self refreshes as long as /RE remains low. (Low Power Self Refresh part only).
2. When using the Low Power Self Refresh mode the following operations must be performed:
If row addresses are being refreshed in an evenly distributed manner over the refresh interval using /F refresh cycles, then at least one
/F refresh cycle must be performed immediately after exit from the Low Power Self Refresh Mode. If row addresses are being refreshed
in any other manner (/F burst or /RE distributed or burst), then all rows must be refreshed immediately before entry to and immediately
after exit from the Low Power Self Refresh.
2-92
Mechanical Data
72 Pin SIMM Module
4.245 (107.82)
4.255 (108.08)
Inches (mm)
3.984 (101.19)
0.133 (3.38)
0.123 (3.12)
0.127 (3.22)
0.400
(10.16)
0.945 (24.00)
0.955 (24.26)
C1
C2
C3
C4
C5
C6
C7
C8
C9
U1
U2
U3
U4
U5
U6
U7
U8
U9
1
0.225
(5.72)
72
0.040 (1.02)
0.042 (1.07)
0.060 (1.52)
RAD.
0.064 (1.63)
0.050 (1.27)
0.245 (6.22)
0.255 (6.48)
0.010
(.254)
0.075 (1.90)
0.085 (2.16)
0.062 (1.57) RAD.
0.208 (5.28)
0.250 (6.35)
1.750 (44.45)
0.250 (6.35)
0.100
(2.54)
0.047 (1.19)
0.054 (1.37)
3.750 (95.25)
2.125 (53.98)
U1-U4, U6-U9 — Enhanced DM2242J-XX, 1M x 4 EDRAMs, 300 Mil SOJ
U5 — Enhanced DM2252J-XX, 1M x 4 EDRAM with Write-Per-Bit (Not present on DM 1M32SJ)
C1-C9 — 0.22µF Chip Capacitors
Socket — Amp 822030-3 or Equivalent
Part Numbering System
DM1M36SJ6 - 12I
Temperature Range
No Designator = 0 to 70oC (Commercial)
I = -40 to 85oC (Industrial)
L = 0 to 70oC, Low Power Self-Refresh
Access Time from Cache in Nanoseconds
12ns
15ns
Configuration
6 = 5 Volt, Multibank EDO
7 = 3.3 Volt, Multibank EDO
Packaging System
J = 300 Mil, Plastic SOJ
Memory Module Configuration
S = SIMM
I/O Width (Including Parity)
32 = 32 Bits
36 = 36 Bits
Memory Depth (Megabits)
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
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