DS1315
Phantom Time Chip
www.dalsemi.com
PIN ASSIGNMENT
FEATURES
§ Real time clock keeps track of hundredths of
seconds, seconds, minutes, hours, days, date
of the month, months, and years
§ Adjusts for months with fewer than 31 days
§ Automatic leap year correction valid up to
2100
§ No address space required to communicate
with RTC
§ Provides nonvolatile controller functions for
battery backup of SRAM
§ Supports redundant battery attachment for
high–reliability applications
§ Full ±10% VCC operating range
§ +3.3 volt or +5 volt operation
§ Industrial (–45°C to +85°C) operating
temperature ranges available
§ Drop in replacement for DS1215
ORDERING INFORMATION
{
DS1315XX-XX
33-3.3 volt operation
5-5 volt operation
X1
1
16
VCC1
X2
2
15
VCC0
WE
3
14
BAT2
BAT1
4
13
RST
GND
5
12
OE
D
6
11
CEI
Q
7
10
CEO
GND
8
9
ROM/RAM
16-Pin DIP (300-mil)
X1
1
16
VCC1
X2
2
15
VCC0
WE
3
14
BAT2
BAT1
4
13
RST
GND
5
12
OE
D
6
11
CEI
Q
7
10
CEO
GND
8
9
blank-commercial temp range
N-industrial temp range
blank-16-pin DIP
S-16-pin SOIC
E-20-pin TSSOP
ROM/RAM
16-Pin SOIC (300-mil)
X1
1
20
VCC1
X2
2
19
VCC0
WE
3
18
BAT2
NC
BAT1
4
17
16
NC
GND
15
OE
NC
6
7
14
NC
D
8
13
CEI
Q
9
12
CEO
GND
10
11
ROM/RAM
5
RST
20-Pin TSSOP
1 of 21
082699
DS1315
PIN DESCRIPTION
X1, X2
WE
BAT1
GND
D
Q
ROM/ RAM
CEO
CEI
OE
RST
BAT2
VCC0
VCC1
- 32.768 kHz Crystal Connection
- Write Enable
- Battery 1 Input
- Ground
- Data Input
- Data Output
- ROM/RAM Mode Select
- Chip Enable Output
- Chip Enable Input
- Output Enable
- Reset
- Battery 2 Input
- Switched Supply Output
- Power Supply Input
DESCRIPTION
The DS1315 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory
controller. In the absence of power, an external battery maintains the timekeeping operation and provides
power for a CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes,
hours, day, date, month, and year information. The last day of the month is automatically adjusted for
months with less than 31 days, including leap year correction. The watch operates in one of two formats:
a 12-hour mode with an AM/PM indicator or a 24-hour mode. The nonvolatile controller supplies all the
necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The DS1315 can be
interfaced with either RAM or ROM without leaving gaps in memory.
OPERATION
The block diagram of Figure 1 illustrates the main elements of the Time Chip. The following paragraphs
describe the signals and functions.
2 of 21
DS1315
TIMING BLOCK DIAGRAM Figure 1
Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles containing the proper data on data in
(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin ( CEO ).
After recognition is established, the next 64 read or write cycles either extract or update data in the Time
Chip and CEO remains high during this time, disabling the connected memory.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable input ( CEI ), output enable ( OE ), and write enable ( WE ). Initially, a read cycle using the
CEI and OE control of the Time Chip starts the pattern recognition sequence by moving pointer to the
first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CEI
and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match
is found, the pointer increments to the next location of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If
a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as
described above until all the bits in the comparison register have been matched. (This bit pattern is shown
in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on
D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations
3 of 21
DS1315
outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition
sequence or data transfer sequence to the Time Chip.
A standard 32.768 kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information
on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
TIME CHIP COMPARISON REGISTER DEFINITION Figure 2
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 1019.
4 of 21
DS1315
NONVOLATILE CONTROLLER OPERATION
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the
ROM/ RAM select pin. When ROM/ RAM is connected to ground, the controller is set in the RAM mode
and performs the circuit functions required to make CMOS RAM and the timekeeping function
nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a
maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS
SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the
battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the
system, the unused battery input should be connected to ground.
The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The
DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces
the chip enable output ( CEO ) to VCCI or VBAT-0.2 volts for external RAM write protection. During
nominal supply conditions, CEO will track CEI with a propagation delay. Internally, the DS1315 aborts
any data transfer in progress without changing any of the Time Chip registers and prevents future access
until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3.
When the ROM/ RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a
read-only device that retains data in the absence of power, battery backup and write protection is not
required. As a result, the chip enable logic will force CEO low when power fails. However, the Time
Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A
typical ROM/Time Chip interface is illustrated in Figure 4.
DS1315 TO RAM/TIME CHIP INTERFACE Figure 3
5 of 21
DS1315
ROM/TIME CHIP INTERFACE Figure 4
TIME CHIP REGISTER INFORMATION
Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1
bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time
Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a
register could produce erroneous results. These read/write registers are defined in Figure 5.
Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing
the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0
and ending with bit 7 of register 7.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the second 10-hour bit (20-23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the
reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set
to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing
data in the timekeeping registers. Reset operates independently of all other in-puts. Bit 5 controls the
oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to
increment.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
6 of 21
DS1315
TIME CHIP REGISTER DEFINITION Figure 5
7 of 21
DS1315
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground
Operating Temperature, commercial range
Operating Temperature, industrial range
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C
-45°C to +85°C
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage 5
Volt Operation
Power Supply Voltage 3.3
Volt Operation
Input Logic 1
Input Logic 0
Battery Voltage VBAT1 or
VBAT2
(0°C to 70°C)
SYMBOL
VCC
MIN
4.5
TYP
5.0
MAX
5.5
UNITS
V
NOTES
1
VCC
3.0
3.3
3.6
V
1
VIH
VIL
VBAT1,
VBAT2
2.2
-0.3
2.5
VCC+0.3
+0.6
3.7
V
V
V
1
1
DC OPERATING ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER
Average VCC Power
Supply Current
VCC Power Supply Current,
(VCC0 = VCCI-0.3)
TTL Standby Current
( CEI = VIH)
CMOS Standby Current
( CEI = VCCI-0.2)
Input Leakage Current
(any input)
Output Leakage Current
(any input)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = 4.0 mA)
Power-Fail Trip Point
Battery Switch Voltage
SYMBOL
ICC1
MIN
TYP
MAX
5
UNITS
mA
NOTES
6
ICC01
150
mA
7
ICC2
3
mA
6
ICC3
1
mA
6
10
IIL
-1
+1
µA
IOL
-1
+1
µA
VOH
2.4
VOL
VPF
VSW
4.25
VBAT1,
VBAT2
8 of 21
V
2
0.4
V
2
4.5
V
13
DS1315
DC POWER DOWN ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC < 4.5V)
PARAMETER
CEO Output Voltage
VBAT1 or VBAT2 Battery
Current
Battery Backup Current
@ VCCO = VBAT-0.2V
SYMBOL
VCEO
MIN
VCCI-0.2
or
VBAT1,2
-0.2
TYP
MAX
UNITS
V
NOTES
8
IBAT
0.5
µA
6
ICCO2
10
µA
9
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/ RAM = GND
(0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Read Recovery
Write Cycle
Write Pulse Width
Write Recovery
Data Setup
Data Hold Time
CEI Pulse Width
OE Pulse Width
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tOW
tRST
MIN
65
TYP
MAX
55
55
5
5
25
25
10
65
55
10
30
0
55
55
65
9 of 21
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
DS1315
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/ RAM = VCCO
(0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Address Setup Time
Address Hold Time
Read Recovery
Write Cycle
CEI Pulse Width
OE Pulse Width
Write Recovery
Data Setup
Data Hold Time
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tAS
tAH
tRR
tWC
tCW
tOW
tWR
tDS
tDH
tRST
MIN
65
TYP
MAX
55
55
5
5
25
25
5
5
10
65
55
55
10
30
0
65
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
DC OPERATING ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER
Average VCC Power
Supply Current
Average VCC Power
Supply Current,
(VCCO = VCCI-0.3)
TTL Standby Current
( CEI = VIH)
CMOS Standby Current
( CEI = VCCI-0.2)
Input Leakage Current
(any input)
Output Leakage Current
(any input)
Output Logic 1 Voltage
(IOUT = 0.4 mA)
Output Logic 0 Voltage
(IOUT = 1.6 mA)
Power-Fail Trip Point
Battery Switch Voltage
SYMBOL
ICC1
MIN
TYP
MAX
3
UNITS
mA
NOTES
6
ICC01
100
mA
7
ICC2
2
mA
6
ICC3
1
mA
6
IIL
-1
+1
µA
ILO
-1
+1
µA
VOH
2.4
VOL
VPF
VSW
2.8
VBAT1,
VBAT2,
or VPF
10 of 21
V
2
0.4
V
2
2.97
V
14
DS1315
DC POWER DOWN ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC < 2.97V)
PARAMETER
CEO Output Voltage
VBAT1 OR VBAT2
Battery Current
Battery Backup Current
@ VCCO = VBAT-0.2
SYMBOL
VCEO
MIN
VCCI
or
VBAT1,2
-0.2
TYP
MAX
UNITS
V
NOTES
8
IBAT
0.3
µA
6
ICCO2
10
µA
9
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/ RAM = GND
(0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Read Recovery
Write Cycle
Write Pulse Width
Write Recovery
Data Setup
Data Hold Time
CEI Pulse Width
OE Pulse Width
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tOW
tRST
MIN
120
TYP
MAX
100
100
5
5
40
40
20
120
100
20
45
0
100
100
120
11 of 21
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
DS1315
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/ RAM = VCCO
(0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Address Setup Time
Address Hold Time
Read Recovery
Write Cycle
CEI Pulse Width
OE Pulse Width
Write Recovery
Data Setup
Data Hold Time
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tAS
tAH
tRR
tWC
tCW
tOW
tWR
tDS
tDH
tRST
MIN
120
TYP
MAX
100
100
5
5
40
40
10
10
20
120
100
100
20
45
0
120
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
NOTES
4
5
5
(tA = 25°C)
SYMBOL
CIN
COUT
MIN
TYP
12 of 21
MAX
10
10
UNITS
pF
pF
NOTES
DS1315
TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/ RAM = GND Figure 6
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/ RAM = GND Figure 7
13 of 21
DS1315
TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/ RAM = VCCO Figure 8
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/ RAM = VCCO Figure 9
14 of 21
DS1315
TIMING DIAGRAM: RESET PULSE Figure 10
tRST
RST
5V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS,
ROM/ RAM = VCCO OR GND
PARAMETER
Recovery Time at
Power-Up
VCC Slew Rate
Power-Down
VPF(max) to VPF(min)
VCC Slew Rate
Power-Down
VPF(min) to VSW
VCC Slew Rate
Power-Up
VPF(min) to VPF(max)
CEI High to Power-Fail
CEI Propagation Delay
SYMBOL
MIN
tREC
1.5
tF
TYP
(0°C to 70°C)
MAX
UNITS
NOTES
2.5
mS
11
300
µs
11
tFB
10
µs
11
tR
0
µs
11
µs
ns
11
2, 3, 11
tPF
tPD
0
5
5V DEVICE POWER-UP CONDITION Figure 11
15 of 21
DS1315
5V DEVICE POWER-DOWN CONDITION Figure 12
3.3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS,
ROM/ RAM = VCCO OR GND
(0°C to 70°C)
PARAMETER
Recovery Time at
Power-Up
VCC Slew Rate
Power-Down
VPF(max) to VPF(min)
VCC Slew Rate
Power-Up
VPF(min) to VPF(max)
CEI High to Power-Fail
CEI Propagation Delay
SYMBOL
MIN
tREC
1.5
tF
TYP
MAX
UNITS
NOTES
2.5
ms
12
300
µs
12
tR
0
µs
12
tPF
tPD
0
µs
ns
12
2, 3, 11
10
16 of 21
DS1315
3.3V DEVICE POWER-UP CONDITION Figure 13
3.3V DEVICE POWER-DOWN CONDITION Figure 14
17 of 21
DS1315
NOTES:
1. All voltages are referenced to ground.
2. Measured with load shown in Figure 15.
3. Input pulse rise and fall times equal 10 ns.
4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM
mode.
5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in
ROM mode.
6. Measured without RAM connected.
7. ICCO1 is the maximum average load current the DS1315 can supply to external memory.
8. Applies to CEO with the ROM/ RAM pin grounded. When the ROM/ RAM pin is connected to VCCO,
CEO will go to a low level as VCCI falls below VBAT.
9. ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10. Applies to all input pins except RST . RST is pulled internally to VCCI.
11. See Figures 11 and 12.
12. See Figures 13 and 14.
13. VSW is determined by the larger of VBAT1 and VBAT2.
14. VSW is determined by the smaller of VBAT1, VBAT2, and VPF.
OUTPUT LOAD Figure 15
18 of 21
DS1315
DS1315 TIME CHIP 16-PIN DIP
PKG
DIM.
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
19 of 21
16-PIN
MIN
MAX
0.740 0.780
0.240
0.260
0.120
0.140
0.300
0.325
0.015
0.040
0.110
0.140
0.090
0.110
0.300
0.370
0.008
0.012
0.015
0.021
DS1315
DS1315 TIME CHIP 16-PIN SOIC
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
L IN.
MM
PHI
16-PIN
MIN
MAX
0.402 0.412
10.21 10.46
0.290 0.300
7.37
7.65
0.089 0.095
2.26
2.41
0.004 0.012
0.102
0.30
0.094 0.105
2.38
2.68
0.050 BSC
1.27 BSC
0.398 0.416
10.11 10.57
0.009 0.013
0.229
0.33
0.013 0.019
0.33
0.48
0.016 0.040
0.40
1.02
0°
8°
20 of 21
DS1315
DS1315 TIME CHIP 16-PIN TSSOP
DIM
A MM
A1 MM
A2 MM
C MM
L MM
e1 MM
B MM
D MM
E MM
G MM
H MM
phi
MIN MAX
1.10
0.05
0.75
1.05
0.09
0.18
0.50
0.70
0.65 BSC
0.18
0.30
6.40
6.90
4.40 NOM
0.25 REF
6.25
6.55
0°
8°
21 of 21