DS25CP104
3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit
Pre-Emphasis and Receive Equalization
General Description
Features
The DS25CP104 is a 3.125 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal
integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface.
The DS25CP104 features four levels (Off, Low, Medium,
High) of transmit pre-emphasis (PE) and four levels (Off, Low,
Medium, High) of receive equalization (EQ) settable via the
SMBus interface. Off and Medium PE levels and Off and Low
EQ levels are settable with the external pins. In addition, the
SMBus circuitry enables the loss of signal (LOS) monitors that
can inform a system of the presence of an open inputs condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device insertion and
return losses, reduce component count and further minimize
board space.
■ DC - 3.125 Gbps low jitter, low skew, low power operation
■ Pin and SMBus configurable, fully differential, nonblocking architecture
■ Pin (two levels) and SMBus (four levels) selectable preemphasis and equalization eliminate ISI jitter
■ Wide Input Common Mode Range enables easy interface
to CML and LVPECL drivers
■ LOS circuitry detects open inputs fault condition
■ On-chip 100Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 6 mm x 6 mm LLP-40 space saving package
Applications
■
■
■
■
SD/HD/3GHD SDI Routers
OC-48 / STM-16
Fibre Channel (2GFC)
InfiniBand and FireWire
Typical Application
30003703
© 2007 National Semiconductor Corporation
300037
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DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with PE and EQ
August 2007
DS25CP104
Ordering Code
NSID
Function
DS25CP104TSQ
Crosspoint Switch
Available Equalization
Levels
Available Pre-Emphasis
Levels
Off / Low / Medium / High
Off / Low / Medium / High
Block Diagram
30003701
Pin Diagram
30003702
DS25CP104 Pin Diagram
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2
DS25CP104
Pin Descriptions
Pin Name
Pin
Number
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EQ0, EQ1,
EQ2, EQ3
40, 39,
11, 12
I, LVCMOS
Receive equalization level select pins. These pins are functional
regardless of the EN_smb pin state.
PE0, PE1,
PE2, PE3
31, 20,
19, 18
I, LVCMOS
Transmit pre-emphasis level select pins. These pins are functional
regardless of the EN_smb pin state.
EN_smb
17
I, LVCMOS
System Management Bus (SMBus) enable pin. The pin has an
internal pull down. When the pin is set to a [1], the device is in the
SMBus mode. All SMBus registers are reset when this pin is
toggled. There is a 20k pulldown device on this pin.
S00/SCL
37
I, LVCMOS
S01/SDA
36
I/O, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are
SMBus clock input and data input pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = H, these pins are the
User-Set SMBus Slave Address inputs.
S30, S31
13, 14
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic H or L.
PWDN
38
I, LVCMOS
For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
VDD
3, 8,
Power
15,25, 30
Power supply pins.
GND
16, DAP
Ground pin and a pad (DAP - die attach pad).
Power
3
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DS25CP104
Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
θJA
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+26.9°C/W
θJC
ESD Susceptibility
HBM (Note 1)
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Input Voltage
−0.3V to +4V
LVDS Differential Input Voltage
0V to 1.0V
LVDS Output Voltage
−0.3V to +4V
LVDS Differential Output Voltage
0V to 1.0V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
4.65W
Derate SQA Package
37.2 mW/°C above +25°C
+3.8°C/W
≥8 kV
≥250V
≥1250V
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Supply Voltage (VCC)
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
SMBus (SDA, SCL)
Min
3.0
0
Typ
3.3
Max
3.6
1
Units
V
V
−40
+25
+85
°C
3.6
V
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
2.0
GND
VIN = 3.6V
VCC = 3.6V
EN_smb pin
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
VOL
Low Level Output Voltage
IOL= 4 mA
40
0.8
V
0
±10
μA
175
250
μA
0
±10
μA
−0.9
−1.5
V
0.4
V
1
V
+100
mV
SDA pin
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Input Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = +3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
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0
VCM = +0.05V or VCC-0.05V
0
−100
4
0
0.05
±1
mV
VCC 0.05
V
±10
μA
Parameter
Conditions
Min
Typ
Max
Units
250
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
IOS
Output Short Circuit Current (Note 8)
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
RL = 100Ω
-35
1.05
RL = 100Ω
1.2
-35
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
SUPPLY CURRENT
ICC1
Supply Current
PWDN = 0
40
50
mA
ICC2
Supply Current
PWDN = 1
PE = Off, EQ = Off
Broadcast (1:4) Mode
145
175
mA
ICC3
Supply Current
PWDN = 1
PE = Off, EQ = Off
Quad Buffer (4:4) Mode
157
190
mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
5
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DS25CP104
Symbol
DS25CP104
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
480
650
ps
460
650
ps
LVDS OUTPUT AC SPECIFICATIONS (Note 11)
tPLHD
Differential Propagation Delay Low to
High
tPHLD
Differential Propagation Delay High to
Low
tSKD1
Pulse Skew |tPLHD − tPHLD| , (Note 12)
20
100
ps
tSKD2
Channel to Channel Skew , (Note 13)
40
125
ps
tSKD3
Part to Part Skew , (Note 14)
50
200
ps
tLHT
Rise Time
80
150
ps
tHLT
Fall Time
80
150
ps
tON
Power Up Time
Time from PWDN =LH to OUTn active
6
20
μs
tOFF
Power Down Time
Time from PWDN =HL to OUTn inactive
8
25
ns
tSEL
Select Time
Time from Sn =LH or HL to new signal
at OUTn
8
12
ns
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE WITH EQ = Off, PE = Off (Note 11)(Figure 5)
tRJ1
tRJ2
tDJ1
tDJ2
tTJ1
tTJ2
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Random Jitter (RMS Value)
No Test Channels
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
No Test Channels
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
10
22
ps
3.125 Gbps
10
27
ps
Total Jitter (Peak to Peak)
No Test Channels
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.07
0.11
UIP-P
3.125 Gbps
0.13
0.16
UIP-P
6
Parameter
Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH EQ = Off, PE = Low(Note 11) (Figure 6 Figure 9)
tRJ1A
tRJ2A
tDJ1A
tDJ2A
Random Jitter (RMS Value)
Test Channels A
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels A
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
10
22
ps
3.125 Gbps
10
27
ps
JITTER PERFORMANCE WITH EQ = Off, PE = Medium (Note 11) (Figure 6 Figure 9)
tRJ1B
tRJ2B
tDJ1B
tDJ2B
tTJ1B
tTJ2B
Random Jitter (RMS Value)
Test Channels B
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels B
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
12
30
ps
3.125 Gbps
12
30
ps
Total Jitter (Peak to Peak)
Test Channels B
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.10
UIP-P
3.125 Gbps
0.10
0.15
UIP-P
JITTER PERFORMANCE WITH EQ = Off, PE = High (Note 11) (Figures 6, 9)
tRJ1C
tRJ2C
tDJ1C
tDJ2C
Random Jitter (RMS Value)
Test Channels C
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels C
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
30
60
ps
3.125 Gbps
30
65
ps
7
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DS25CP104
Symbol
DS25CP104
Symbol
Parameter
Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH PE = Off, EQ = Low (Note 11) (Figure 7 Figure 9)
tRJ1D
tRJ2D
tDJ1D
tDJ2D
tTJ1D
tTJ2D
Random Jitter (RMS Value)
Test Channels D
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels D
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
20
40
ps
3.125 Gbps
20
40
ps
Total Jitter (Peak to Peak)
Test Channels D
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.15
UIP-P
3.125 Gbps
0.09
0.20
UIP-P
JITTER PERFORMANCE WITH PE = Off, EQ = Medium (Note 11) (Figures 7, 9)
tRJ1E
tRJ2E
tDJ1E
tDJ2E
Random Jitter (RMS Value)
Test Channels E
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Residual Deterministic Jitter (Peak to
Peak)
Test Channels E
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
35
60
ps
3.125 Gbps
28
55
ps
JITTER PERFORMANCE WITH PE = Off, EQ = High (Note 11) (Figures 7, 9)
tRJ1F
tRJ2F
tDJ1F
tDJ2F
Random Jitter (RMS Value)
Test Channels F
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
1.3
1.8
ps
1.5625 GHz
1.4
2.4
ps
Residual Deterministic Jitter (Peak to
Peak)
Test Channels F
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
30
75
ps
3.125 Gbps
35
90
ps
JITTER PERFORMANCE WITH PE = Medium, EQ = Low (Note 11) (Figures 7, 9)
tRJ1G
tRJ2G
tDJ1G
tDJ2G
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Random Jitter (RMS Value)
Input Test Channels D
Output Test Channels B
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Input Test Channels D
Output Test Channels B
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
25
ps
3.125 Gbps
20
ps
8
Parameter
Conditions
Min
Typ
Max
Units
100
kHz
SMBus AC SPECIFICATIONS
fSMB
SMBus Operating Frequency
10
tBUF
Bus free time between Stop and Start
Conditions
4.7
μs
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0
μs
tSU:SDA
Repeated Start Condition setup time.
4.7
μs
tSU:SDO
Stop Condition setup time
4.0
μs
tHD:DAT
Data hold time
300
ns
tSU:DAT
Data setup time
250
ns
tTIMEOUT
Detect clock low timeout
25
tLOW
Clock low period
4.7
tHIGH
Clock high period
4.0
tPOR
Time in which a device must be
operational after power-on reset
35
ms
μs
50
μs
500
ms
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the same signal path of any two devices running at the same VCC and within 5°C of each
other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
9
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DS25CP104
Symbol
DS25CP104
DC Test Circuits
30003720
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30003721
FIGURE 2. Differential Driver AC Test Circuit
30003722
FIGURE 3. Propagation Delay Timing Diagram
30003723
FIGURE 4. LVDS Output Transition Times
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10
DS25CP104
Pre-Emphasis and Equalization Test Circuits
30003729
FIGURE 5. Jitter Performance Test Circuit
30003727
FIGURE 6. Pre-Emphasis Performance Test Circuit
30003726
FIGURE 7. Equalization Performance Test Circuit
11
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DS25CP104
30003730
FIGURE 8. Pre-Emphasis and Equalization Performance Test Circuit
30003728
FIGURE 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7
and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries: Trace Width (W) = 5 mils, Gap
(S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
500 MHz
750 MHz
1000 MHz
1250 MHz
1500 MHz
1560 MHz
A
10
-1.2
-1.7
-2.0
-2.4
-2.7
-2.8
B
20
-2.6
-3.5
-4.1
-4.8
-5.5
-5.6
C
30
-4.3
-5.7
-7.0
-8.2
-9.4
-9.7
D
15
-1.6
-2.2
-2.7
-3.2
-3.7
-3.8
E
30
-3.4
-4.5
-5.6
-6.6
-7.7
-7.9
F
60
-7.8
-10.3
-12.4
-14.5
-16.6
-17.0
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Insertion Loss (dB)
12
The DS25CP104 is a 3.125 Gbps 4x4 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. The DS25CP104 operates in two modes: Pin
Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with
external pins. This is possible with two input select pins per
output (e.g. S00 and S01 pins for OUT0). There is also one
transmit pre-emphasis (PE) level select pin per output for
switching the PE levels between Medium and Off settings and
one receive equalization (EQ) level select pin per input for
switching the EQ levels between Low and Off settings.
In the Pin Mode, feedback from the LOS (Loss Of Signal)
monitor circuitry is not available (there is not an LOS output
pin).
When in the SMBus Mode, the full switch configuration, four
levels of transmit pre-emphasis (Off, Low, Medium and High),
four levels of receive equalization (Off, Low, Medium and
High) and SoftPWDN can be programmed via the SMBus interface. In addition, by using the SMBus interface, a user can
obtain the feedback from the built-in LOS circuitry which detects an open inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus
clock (SCL) input and data (SDA) input pins respectively; the
DS25CP104 OPERATION IN THE PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device
power suppy pins, the DS25CP104 enters the Power Up
mode when the PWDN pin is set to logic H. When in the Power
Down mode (PWDN pin is set to logic L), all circuitry is shut
down except the minimum required circuitry for the LOS and
SMBus Slave operation.
Switch Configuration
In the Pin Mode, the DS25CP104 operates as a fully pin-configurable crosspoint switch. The following truth tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
TABLE 1. Input Select Pins Configuration for the Output OUT0
S01
S00
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
TABLE 2. Input Select Pins Configuration for the Output OUT1
S11
S10
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
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DS25CP104
S10, S11, S21 and S21 pins become the User-Set SMBus
Slave Address input pins (ADDR0, 1, 2 and 3) while the S30
and S31 pins become non-functional (tieing these two pins to
either H or L is recommended if the device will function only
in the SMBus mode).
In the SMBus Mode, the PE and EQ select pins as well as the
PWDN pin remain functional. How these pins function in each
mode is explained in the following sections.
Functional Description
DS25CP104
TABLE 3. Input Select Pins Configuration for the Output OUT2
S21
S20
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31
S30
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
Setting Pre-Emphasis Levels
The DS25CP104 has one PE level select pin per output for
setting the transmit pre-emphasis to either Medium or Off level. The following is the transmit pre-emphasis truth table.
TABLE 5. Transmit Pre-Emphasis Truth Table
OUTPUT OUTn, n = {0, 1, 2, 3}
Pre-Emphasis Control Pin (PEn) State
Pre-Emphasis Level
0
Off
1
Medium
Transmit Pre-emphasis Level Selection for an Output OUTn
Setting Equalization Levels
The DS25CP104 has one EQ level select pin per input for
setting the receive equalization to either Low or Off level. The
following is the receive equalization truth table.
TABLE 6. Receive Equalization Truth Table
INPUT INn, n = {0, 1, 2, 3}
Equalization Control Pin (EQn) State
Equalization Level
0
Off
1
Low
Receive Equalization Level Selection for an Input INn
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14
Device Address
Based on the SMBus 2.0 specification, the DS25CP104 has
a 7-bit slave address. The three most significant bits of the
TABLE 7. DS25CP104 Slave Address
1
0
1
ADDR3
MSB
ADDR2
ADDR1
ADDR0
LSB
This slave address configuration allows up to sixteen
DS25CP104 devices on a single SMBus bus.
Writing to a Register
To write a data value to a register in the DS25CP104, the host
writes three bytes to the DS25CP104. The first byte is the
device address—the device address is a 7 bit value, and if
writing to the DS25CP104 the last bit (LSB) is set to ‘0’ to
signify that the operation is a write. The second byte written
is the register address, and the third byte written is the data
to be written into the addressed register. If additional data
writes are performed, the register address is automatically incremented. At the end of the write cycle the host places the
bus in the STOP state.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
Reading From a Register
To read the data value from a register, first the host writes the
device address with the LSB set to a ‘0’ denoting a write, then
the register address is written to the device. The host then
reasserts the START condition, and writes the device address
once again, but this time with the LSB set to a ‘1’ denoting a
read, and following this the DS25CP104 will drive the SDA
line with the data from the addressed register. The host indicates that it has finished reading the data by asserting a ‘1’
for the ACK bit. After reading the last byte, the host will assert
a ‘0’ for NACK to indicate to the DS25CP104 that it does not
require any more data.
SMBus Transactions
A transaction begins with the host placing the DS25CP104
SMBus into the START condition, then a byte (8 bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been received.
15
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DS25CP104
slave address are hard wired inside the DS25CP104 and are
“101”. The four least significant bits of the address are assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
DS25CP104 OPERATION IN THE SMBUS MODE
The DS25CP104 operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
DS25CP104
Register Descriptions
There are five data registers in the DS25CP104 accessible via the SMBus interface.
TABLE 8. DS25CP104 SMBus Data Registers
Address
(hex)
Name
Access
Description
0
Switch Configuration
R/W
Switch Configuration Register
1
PE Level Select
R/W
Transmit Pre-emphasis Level Select Register
2
EQ Level Select
R/W
Receive Equalization Level Select Register
3
Control
R/W
Powerdown, LOS Enable and Pin Control Register
4
LOS
RO
Loss Of Signal (LOS) Reporting Register
30003710
FIGURE 10. DS25CP104 Registers Block Diagram
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16
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register
mapping and associated truth table.
Bit
Default
Bit Name
Access
Description
D[1:0]
00
Input Select 0
R/W
Selects which input is routed to the OUT0.
D[3:2]
00
Input Select 1
R/W
Selects which input is routed to the OUT1.
D[5:4]
00
Input Select 2
R/W
Selects which input is routed to the OUT2.
D[7:6]
00
Input Select 3
R/W
Selects which input is routed to the OUT3.
TABLE 9. Switch Configuration Register Truth Table
D1
D0
Input Routed to the OUT0
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based
on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).
PE LEVEL SELECT REGISTER
The PE Level Select register selects the pre-emphasis level for each of the outputs. The following two tables show the register
mapping and associated truth table.
Default
Bit Name
D[1:0]
Bit
00
PE Level Select 0
Access
R/W
Description
Sets pre-emphasis level on the OUT0.
D[3:2]
00
PE Level Select 1
R/W
Sets pre-emphasis level on the OUT1.
D[5:4]
00
PE Level Select 2
R/W
Sets pre-emphasis level on the OUT2.
D[7:6]
00
PE Level Select 3
R/W
Sets pre-emphasis level on the OUT3.
TABLE 10. PE Level Select Register Truth Table
D1
D0
0
0
Pre-Emphasis Level for the OUT0
Off
0
1
Low
1
0
Medium
1
1
High
NOTE: The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
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DS25CP104
SWITCH CONFIGURATION REGISTER
DS25CP104
EQ LEVEL SELECT REGISTER
The EQ Level Select register selects the equalization level for each of the inputs. The following two tables show the register mapping
and associated truth table.
Bit
Default
Bit Name
Access
Description
D[1:0]
00
EQ Level Select 0
R/W
Sets equalization level on the IN0.
D[3:2]
00
EQ Level Select 1
R/W
Sets equalization level on the IN1.
D[5:4]
00
EQ Level Select 2
R/W
Sets equalization level on the IN2.
D[7:6]
00
EQ Level Select 3
R/W
Sets equalization level on the IN3.
TABLE 11. EQ Level Select Register Truth Table
D1
D0
Equalization Level for the IN0
0
0
Off
0
1
Low
1
0
Medium
1
1
High
NOTE: The truth tables for the IN1, IN2, and IN3 outputs are identical to this table.
CONTROL REGISTER
The Control register enables SoftPWDN control, individual output power down (PWDNn) control, LOS Circuitry Enable control, PE
Level Select Enable control and EQ Level Select Enable control via the SMBus. The following table shows the register mapping.
Bit
Default
Bit Name
1111
PWDNn
R/W
Writing a [0] to the bit D[n] will power down the output OUTn
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
D[4]
0
Ignore_External_EQ
R/W
Writing a [1] to the bit D[4] will ignore the state of the external
EQ pins and will allow setting the EQ levels via the SMBus
interface.
D[5]
0
Ignore_External_PE
R/W
Writing a [1] to the bit D[5] will ignore the state of the external
PE pins and will allow setting the PE levels via the SMBus
interface.
D[6]
0
EN_LOS
R/W
Writing a [1] to the bit D[6] will enable the LOS circuitry and
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
D[7]
0
SoftPWDN
R/W
Writing a [0] to the bit D[7] will place the device into the power
down mode. This pin is ORed together with the PWDN pin.
D[3:0]
Access
Description
TABLE 12. DS25CP104 Power Modes Truth Table
PWDN
SoftPWDN
PWDNn
0
0
x
Power Down Mode. In this mode, all circuitry is shut down except the
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
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DS25CP104 Power Mode
18
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit
Default
Bit Name
D[0]
0
LOS0
RO
Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
D[1]
0
LOS1
RO
Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
D[2]
0
LOS2
RO
Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
D[3]
0
LOS3
RO
Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
0000
Reserved
RO
Reserved for future use. Returns undefined value when read.
D[7:4]
Access
Description
19
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DS25CP104
LOS REGISTER
DS25CP104
INPUT INTERFACING
The DS25CP104 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS25CP104 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS25CP104 inputs are internally terminated with
a 100Ω resistor.
30003731
Typical LVDS Driver DC-Coupled Interface to DS25CP104 Input
30003732
Typical CML Driver DC-Coupled Interface to DS25CP104 Input
30003733
Typical LVPECL Driver DC-Coupled Interface to DS25CP104 Input
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The DS25CP104 outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that
the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate
LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface
implementation.
30003734
Typical DS25CP104 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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DS25CP104
OUTPUT INTERFACING
DS25CP104
Typical Performance
30003750
30003752
Total Jitter as a Function of Data Rate
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and EQ Level
30003751
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and EQ Level
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30003753
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and EQ Level
22
DS25CP104
30003754
30003756
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and PE Level
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and PE Level
30003757
30003755
Supply Current as a Function of Data Rate and PE Level
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and PE Level
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DS25CP104
30003762
30003763
A 2.5 Gbps NRZ PRBS-23 without PE
After 30" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
A 3.125 Gbps NRZ PRBS-23 without PE
After 30" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
30003760
30003761
A 3.125 Gbps NRZ PRBS-23 with High PE
After 2" Differential FR-4 Microstrip
H: 50 ps / DIV, V: 100 mV / DIV
A 2.5 Gbps NRZ PRBS-23 with High PE
After 2" Differential FR-4 Microstrip
H: 75 ps / DIV, V: 100 mV / DIV
30003764
30003765
A 2.5 Gbps NRZ PRBS-23 with High PE
After 30" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
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A 3.125 Gbps NRZ PRBS-23 with High PE
After 30" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
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DS25CP104
30003767
30003766
A 3.125 Gbps NRZ PRBS-23 without EQ
After 60" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
A 2.5 Gbps NRZ PRBS-23 without EQ
After 60" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
30003769
30003768
A 3.125 Gbps NRZ PRBS-23 with High EQ
After 60" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
A 2.5 Gbps NRZ PRBS-23 with High EQ
After 60" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
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DS25CP104
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25CP104TSQ
NS Package Number SQA40A
(See AN-1187 for PCB Design and Assembly Recommendations)
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DS25CP104
Notes
27
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DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with PE and EQ
Notes
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