DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 DS90UA102-Q1 Multi-Channel Digital Audio Link Check for Samples: DS90UA102-Q1 FEATURES DESCRIPTION • • The DS90UA102-Q1 Deserializer, in conjunction with the DS90UA101-Q1 Serializer, provides a solution for distribution of digital audio in multi-channel audio systems. It receives a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency. 1 • • • • • • • • • • • • • • • • Digital Audio Deserializer Flexible Digital Audio Outputs, supporting I2S (Stereo) and TDM (Multi-Channel) Formats Coaxial or Single Differential Pair Interconnect High Speed Serial Input Interface Very Low Latency (<15 µs) Bidirectional Control Interface Channel with I2C Compatible Serial Control Bus Supports up to 8 Stereo I2S or TDM Audio Outputs Supports Audio System Clocks from 10 MHz to 50 MHz Single 1.8V Supply 1.8V or 3.3V I/O Interface 4/4 Dedicated General Purpose Inputs/Outputs AC-Coupled STP or Coaxial Cable up to 15m DC-Balanced & Scrambled Data w/ Embedded Clock Adaptive Cable Equalization At-Speed Link BIST Mode and LOCK Status Pin Automotive Grade Product: AEC-Q100 Grade 2 Qualified Temperature Range: -40°C to 105°C ISO 10605 and IEC 61000-4-2 ESD Compliant The DS90UA102-Q1 Deserializer extracts the clock and level shifts the signals from high-speed low voltage differential signaling to single-ended LVCMOS. The device outputs up to eight digital audio data channels, word/frame sync, bit clock, and system clock. Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices. Adaptive equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces medium-induced deterministic jitter. APPLICATIONS • • • Automotive Infotainment Systems Active Noise Cancellation Systems Distributed Multi-Channel Audio Systems 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Applications Diagram OSC Digital Audio Interface Digital Audio Interface VDDIO VDD (1.8V) (1.8V or 3.3V) VDD (1.8V) Serial Interface 50Q Coaxial, AC-Coupled SCK LRCK BCK DIN[7:0] DOUT+ SCK LRCK BCK DOUT[7:0] RIN+ OEN OSS_SEL PDB DS90UA102-Q1 Deserializer LOCK PASS SCL SDA IDx PDB SCL SDA IDx Digital Audio Interface Digital Audio Interface VDD VDDIO (1.8V or 3.3V) (1.8V) VDD VDDIO (1.8V or 3.3V) (1.8V) Analog In [3:0] 4-Channel Audio ADC Analog In [3:0] TDM I2S/TDM DIN[7] DOUT[7:0] Audio DACs Power Amplifiers I2S DIN[6] Forward Channel FPD-Link III DIN[5] DOUT+ RIN+ DOUTI2S/TDM DSP DS90UA101-Q1 LRCK BCK SCK GPI[3:0] GPO[3:0] RIN- Bi-Directional Bidirectional Back Channel Control Channel DIN[4:0] DS90UA102-Q1 OEN OSS_SEL PDB LRCK BCK SCK GPO[3:0] GPIO[3:0] «««« I2S «««« 4-Channel Audio ADC LRCK BCK SCK Audio DAC or DSP GPO[3:0] GPIO[3:0] GPI[3:0] GPO[3:0] DS90UA101-Q1 Serializer I2S Interface Audio Controller or DSP I2S Interface VDDIO (1.8V or 3.3V) LOCK PASS PDB IDx SCL SDA IDx SCL SDA Figure 1. Typical Applications 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Output Latch RIN- Decoder RIN+ RT Deserializer RT Adaptive Eq. Block Diagram DOUT[7:0] GPO[3:0] GPIO[3:0] LOCK I2C Controller Encoder Decoder BISTEN FIFO Timing and Control PDB OEN SCK Clock Gen CDR PASS SDA SCL IDx Figure 2. Block Diagram Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 3 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com RES0 RES1 RES1 VDDCML PDB VDDIO GPIO3 GPIO2 GPIO1 GPIO0 34 33 32 31 30 29 28 27 26 25 35 IDx 36 VDDR DS90UA102-Q1 Pin Diagram DOUT7 RES0 43 DAP = GND 18 DOUT6 RES0 44 17 VDDD VDDPLL 45 16 DOUT5 RES0 46 15 DOUT4 PASS 47 14 DOUT3 LOCK 48 13 DOUT2 12 19 DOUT1 DS90UA102-Q1 11 42 DOUT0 RIN- 10 VDDIO BCK 20 9 41 LRCK RIN+ 8 GPO0 SCK 21 7 40 VDDIO VDDCML 6 GPO1 BISTEN 22 5 39 OEN CMLOUTN 4 GPO2 OSS_SEL 23 3 38 VDDR CMLOUTP 2 GPO3 SCL 24 1 37 SDA RES0 Figure 3. DS90UA102-Q1 — Top View Pin Descriptions Pin Name Pin # I/O, Type Description Digital Audio Interface SCK 8 Output, LVCMOS System clock output. Recovered system clock fed into the Serializer's SCK pin. LRCK 9 Output, LVCMOS Word clock output. 10 Output, LVCMOS Bit clock output. BCK DOUT[7:0] 11, 12, 13, 14, 15, 16, 18, 19 Outputs, LVCMOS Digital audio data outputs. LVCMOS Parallel Interface GPIO[3:0] 28, 27, 26, 25 Inputs/Outputs, LVCMOS w/ pull down GPO[3:0] 24, 23, 22, 21 Outputs, LVCMOS General purpose I/Os. May be configured as inputs to the back-channel (which can be read by the Serializer), or as local register outputs. General purpose outputs, transported over the forward channel from the Serializer. Control and Configuration SDA 1 Input/Output, Open Drain I2C data input/output line. Must have an external pull-up to VDDIO. DO NOT FLOAT. Recommended pull-up: 4.7 kΩ. SCL 2 Input/Output, Open Drain I2C clock line. Must have an external pull-up to VDDIO. DO NOT FLOAT. Recommended pull-up: 4.7 kΩ. OSS_SEL 4 Input, LVCMOS w/ pull down 4 Output sleep state select. Refer to Table 5. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Pin Name Pin # I/O, Type OEN 5 Input, LVCMOS w/ pull down Description Output enable. Refer to Table 5. BISTEN 6 Input, LVCMOS w/ pull down BIST enable pin. BISTEN = H, BIST mode is enabled. BISTEN = L, BIST mode is disabled. PDB 30 Input, LVCMOS w/ pull down Power down mode input pin. PDB = H device is enabled and is ON. PDB = L, device is powered down. When the device is in the powered down state, the PLL is shutdown, IDD is minimized, and control registers are RESET. IDx 35 Input, Analog Device I2C address select. The IDx pin on the Deserializer is used to assign its I2C device address. See Table 2. DO NOT FLOAT. RIN+ 41 Input, LVDS True serial interface input. The interconnection must be AC-coupled to this pin with a 0.1 µF capacitor. RIN- 42 Input, LVDS Inverting serial interface input. The interconnection must be AC-coupled to this pin with a 0.1 µF capacitor. CMLOUTP 38 Output, LVDS True CML output. Monitor point for equalized input signal. CMLOUTN 39 Output, LVDS Inverting CML output. Monitor point for equalized input signal. Serial Interface Status PASS 47 Output, LVCMOS PASS status output pin. PASS = H: Error-free transmission (applies to BIST and normal operation). PASS = L: One or more parity errors occurred in the received payload. In normal and BIST mode, PASS pin toggles low momentarily for each parity error. In BIST mode only, PASS pin also toggles low momentarily at the end of the BIST if at least one error occurred during the test. Leave open if unused. Otherwise, route to a test point/pad (recommended). LOCK 48 Output, LVCMOS LOCK status output pin. LOCK = H: PLL is locked; Deserializer outputs are active. LOCK = L: PLL is unlocked; Deserializer outputs are not valid with respect to Serializer inputs. Leave open if unused. Otherwise, route to a test point/pad (recommended). Power and Ground VDDR 3, 36 Power 1.8V (±5%) analog core power. VDDIO 7, 20, 29 Power LVCMOS I/O power. 1.8V (±5%) or 3.3V (±10%). VDDD 17 Power 1.8V (±5%) digital power. VDDCML 31, 40 Power 1.8V (±5%) CML receiver and Bidirectional Control Channel power. VDDPLL 45 Power 1.8V (±5%) PLL power. DAP Ground DAP is the large metal contact located at the bottom center of the LLP package. Connect to the GND plane with at least 9 vias. RES0 34, 37, 43, 44, 46 Reserved Reserved. Tie to GND. RES1 32, 33 Reserved Reserved. Leave floating. GND Other Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 5 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) −0.3V to +2.5V Supply Voltage – VDDn (1.8V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to + (VDDIO + 0.3V) LVCMOS I/O Voltage −0.3V to +(VDDCML + 0.3V) CML Driver/Receiver I/O Voltage (VDDCML) Junction Temperature +150°C Storage Temperature −65°C to +150°C Maximum Package Power Dissipation Capacity 1/θJA °C/W above +25° Package Derating: DS90UA102-Q1 48L WQFN θJA(based on 16 thermal vias) 26.9°C/W θJC(based on 16 thermal vias) 4.4°C/W ESD Rating (IEC 61000-4-2) RD = 330Ω, CS = 150 pF Air Discharge (RIN+, RIN-) ≥±25 kV Contact Discharge (RIN+, RIN-) ≥±7 kV ESD Rating (ISO10605) RD = 330Ω, CS = 150/330 pF ESD Rating (ISO10605) RD = 2KΩ, CS = 150/330 pF Air Discharge (RIN+, RIN–) ≥±15 kV Contact Discharge (RIN+, RIN-) ≥±8 kV ESD Rating (HBM) ≥±8 kV ESD Rating (CDM) ≥±1 kV ≥±250 V ESD Rating (MM) For soldering specifications: (1) 6 see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 RECOMMENDED OPERATING CONDITIONS Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) OR 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V VDDn (1.8V) 25 mVp-p VDDIO (1.8V) 25 mVp-p VDDIO (3.3V) 50 mVp-p +105 °C Supply Noise (1) Operating Free Air Temperature (TA) –40 +25 SCK Clock Frequency (STP Cable) 10 50 MHz SCK Clock Frequency (Coaxial Cable) 25 50 MHz (1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 7 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Conditions Min (2) (3) Typ Max Units LVCMOS DC SPECIFICATIONS 3.3V I/O (DES OUTPUTS, GPIO, GPO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.8 V IIN Input Current VIN = 0V or 3.6V VIN = 3.0V to 3.6V -20 +20 µA VOH High Level Output Voltage VDDIO = 3.0V to 3.6V IOH = −4 mA 2.4 VDDIO V VOL Low Level Output Voltage VDDIO = 3.0V to 3.6V IOL = +4 mA GND 0.4 V IOS Output Short Circuit Current VOUT = 0V Deserializer LVCMOS Outputs IOZ TRI-STATE Output Current PDB = 0V, VOUT = 0V or VDD LVCMOS Outputs ±1 –35 -20 mA +20 µA LVCMOS DC SPECIFICATIONS 1.8V I/O (DES OUTPUTS, GPIO, GPO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 1.71V to 1.89V VIL Low Level Input Voltage IIN 0.65 VIN VIN VIN = 1.71V to 1.89V GND 0.35 VIN Input Current VIN = 0V or 1.89V VIN = 1.71V to 1.89V -20 VOH High Level Output Voltage VDDIO = 1.71V to 1.89V IOH = −4 mA VOL Low Level Output Voltage VDDIO = 1.71V to 1.89V Deserializer IOL = +4 mA LVCMOS Outputs IOS Output Short Circuit Current VOUT = 0V Deserializer LVCMOS Outputs IOZ TRI-STATE Output Current PDB = 0V, VOUT = 0V or VDD LVCMOS Outputs V ±1 +20 µA VDDIO 0.45 VDDIO V GND 0.45 V -17 -20 mA +20 µA µA CML RECEIVER DC SPECIFICATIONS (RIN+,RIN-) Input Current IIN RT VIN = VDD or 0V, VDD = 1.89V -20 1 +20 Differential Internal Differential across RIN+ and RINTermination Resistance 80 100 120 Single-ended RIN+ or RIN– Termination Resistance 40 50 60 Ω CML RECEIVER AC SPECIFICATIONS (RIN+,RIN–) |Vswing| Minimum allowable swing for 1010 pattern Line Rate = 1.4 Gbps (Figure 5) 135 (4) mV CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN) Ew Differential Output Eye Opening EH Differential Output Eye Height (1) (2) (3) (4) 8 RL = 100Ω Jitter Frequency>ƒ/40 (Figure 10) 0.45 UI 200 mV The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not verified . Specification is verified by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) Symbol Parameter Conditions Min Typ Max 21 32 Units SUPPLY CURRENT, DIGITAL, PLL, AND ANALOG VDD IDDIOR IDDR IDDRZ IDDIORZ Deserializer (Rx) VDDIO Supply Current (includes load current) Deserializer (Rx) VDDn Supply Current Deserializer (Rx) VDDn Supply Current Powerdown Deserializer (Rx) VDDIO Supply Current Powerdown VDDIO = 1.89V CL = 8pF Worst Case Pattern ƒ = 50 MHz VDDIO = 1.8V CL = 8 pF Random Pattern ƒ = 24.576 MHz 4 ƒ = 12.288 MHz 2 VDDIO = 3.6V CL=8pF Worst Case Pattern ƒ = 50 MHz VDDIO = 3.3V CL = 8pF Random Pattern ƒ = 24.576 MHz 15 ƒ = 12.288 MHz 12 VDDn= 1.89V CL=4pF Worst Case Pattern ƒ = 50 MHz VDDn= 1.8V CL=8pF Random Pattern ƒ = 24.576 MHz 60 ƒ = 12.288 MHz 56 PDB = 0V All other LVCMOS Inputs = 0V VDDIO = 1.89V Default Registers 42 900 VDDIO = 3.6V Default Registers 42 900 VDDIO = 1.89V 8 40 VDDIO = 3.6V 360 800 PDB = 0V All other LVCMOS Inputs = 0V mA 25 63 38 96 mA µA Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 µA 9 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS: Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol tRCP Parameter Receiver Output Clock Period tPDC Conditions STP Cable Pin/Freq. SCK (Figure 9) Coaxial Cable SCK Duty Cycle SCK LVCMOS Low-toVDDIO: 1.71V to 1.89V or 3.0V High Transition Time to 3.6V, CL = 8 pF (lumped load) LVCMOS High-toDefault Registers Low Transition Time (Figure 7), (4) SCK LVCMOS Low-toVDDIO: 1.71V to 1.89V or 3.0V High Transition Time to 3.6V, CL = 8 pF (lumped load) LVCMOS High-toDefault Registers Low Transition Time (Figure 7), (4) DOUT[7:0], GPO[3:0], BCK, LRCK tROS Setup Data to SCK tROH Hold Data to SCK VDDIO: 1.71V to 1.89V or 3.0V to 3.6V, CL = 8 pF (lumped load) Default Registers (Figure 9) DOUT[7:0], GPO[3:0], BCK, LRCK tDD Deserializer Delay Default Registers Register 0x03h b[0] (RRFB = 1) (Figure 8), (4) tDDLT Deserializer Data Lock Time With Adaptive Equalization (Figure 6) tRCJ Receiver Clock Jitter SCK (4) tDPJ Deserializer Period Jitter SCK (5) (4) tDCCJ Deserializer Cycleto-Cycle Clock Jitter SCK (6) (4) tCLH tCHL tCLH tCHL (1) (2) (3) (4) (5) (6) 10 (2) (3) Min Typ Max 20 T 100 20 T 40 40 50 60 1.3 2 2.8 1.3 2 2.8 1 2.5 4 1 2.5 4 0.38 0.5 0.38 0.5 Units ns % ns ns 109 SCK = 50 MHz SCK = 50 MHz SCK = 50 MHz T 112 T 15 22 ms 22 35 ps 180 330 ps 460 730 ps The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not verified . Specification is verified by characterization and is not tested in production. tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples. tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 BIDIRECTIONAL CONTROL BUS TIMING SPECIFICATIONS Bidirectional Control Bus: AC Timing Specifications (SCL, SDA) - I2C Compliant Over recommended supply and temperature ranges unless otherwise specified. (Figure 4) Symbol Parameter Conditions Min Typ Max Units Standard Mode 100 kHz Fast Mode 400 kHz Recommended Input Timing Requirements fSCL SCL Clock Frequency tLOW SCL Low Period Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 4.0 µs tHIGH SCL High Period Fast Mode 0.6 µs tHD:STA Hold time for a start or a repeated start condition Standard Mode 4.0 µs Fast Mode 0.6 µs tSU:STA Set Up time for a start or a repeated start condition Standard Mode 4.7 µs Fast Mode 0.6 tHD:DAT Data Hold Time tSU:DAT Data Set Up Time tSU:STO Set Up Time for STOP Condition tBUF Bus Free time between Stop and Start tr SCL & SDA Rise Time tf SCL & SDA Fall Time µs Standard Mode 0 3.45 µs Fast Mode 0 900 ns Standard Mode 250 Fast Mode 100 ns ns Standard Mode 4.0 µs Fast Mode 0.6 µs Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 1000 ns Fast Mode 300 ns Standard Mode 300 ns Fast Mode 300 ns Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 11 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Bidirectional Control Bus: DC Timing Specifications (SCL, SDA) - I2C Compliant (1) Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units VDDIO V Recommended Input Timing Requirements VIH Input High Level SDA and SCL 0.7*VDDIO VIL Input Low Level SDA and SCL GND VHY Input Hysteresis VOL Output Low Level SDA, IOL=0.5mA IIN Input Current SDA or SCL, VIN=VDDIO OR GND tR SDA Rise Time-READ 430 ns tF SDA Fall Time-READ SDA, RPU = 10kΩ, Cb ≤ 400pF(Figure 4) 20 ns tSU;DAT (Figure 4) 560 ns tHD;DAT (Figure 4) 615 ns tSP CIN (1) 12 0.3*VDDIO >50 SDA or SCL 0 —10 V mV 0.4 V 10 µA 50 ns <5 pF Specification is verified by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 TIMING AND CIRCUIT DIAGRAMS SDA tf tHD;STA tLOW tr tBUF tf tr SCL tSU;STA tHD;STA tHIGH tHD;DAT tSU;STO tSU;DAT START STOP REPEATED START START Figure 4. Bi-directional Control Bus Timing Single-Ended § DOUTV V VOD OD+ VOS OD- DOUT+ Differential V OD+ (DOUT+) - (DOUT-) 0V V OD- Figure 5. Differential Vswing Diagram PDB VDDIO/2 § § tDDLT RIN± TRI-STATE VDDIO/2 § LOCK Figure 6. Deserializer Data Lock Time 80% 80% Deserializer 8 pF lumped 20% 20% tCLH tCHL Figure 7. Deserializer LVCMOS Output Load and Transition Times Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 13 DS90UA102-Q1 SYMBOL N + 3 § § 0V SYMBOL N + 3 § § SYMBOL N + 2 § § RIN± SYMBOL N + 1 § § SYMBOL N www.ti.com § § SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 tDD SCK SYMBOL N - 2 SYMBOL N - 1 § §§ § §§ § §§ SYMBOL N - 3 § §§ § §§ ROUT[7:0] VDDIO/2 SYMBOL N SYMBOL N+1 Figure 8. Deserializer Delay tRCP SCK VDDIO 1/2 VDDIO 1/2 VDDIO 0V ROUT[7:0], BCK, LRCK VDDIO 1/2 VDDIO 1/2 VDDIO 0V tROS tROH Figure 9. Deserializer Output Setup and Hold Times Ew VOD (+) EH 0V EH VOD (-) tBIT (1 UI) Figure 10. CML Output Driver 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 PDB= H OSS_SEL VIH VIL VIH OEN RIN (Diff.) VIL 'RQ¶W&DUH 'RQ¶W&DUH Delay OSS_SEL Delay OEN LOCK = H Delay OSS_SEL PASS DOUT[7:0], GPI[3:0], BCK, LRCK SCK (RFB = L) Delay OEN LOW TRI-STATE LOW TRI-STATE LOW TRI-STATE ACTIVE ACTIVE ACTIVE TRI-STATE LOW TRI-STATE LOW LOW TRI-STATE LOW Figure 11. Output States JITTER AMPLITUDE (UI) 0.65 0.60 0.55 0.50 0.45 1E+04 1E+05 1E+06 1E+07 JITTER FREQUENCY (Hz) Figure 12. Typical Deserializer Input Jitter Tolerance Curve at 1.4Gbps Line Rate Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 15 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com DS90UA102-Q1 REGISTER INFORMATION The table below contains information on the DS90UA102-Q1 control registers. These registers are accessible locally via the I2C control interface, or remotely via the Bidirectional Control Channel. Addresses not listed are reserved. Fields listed as reserved should not be changed from the listed default value. Addr (Hex) 0x00 Name Bits 7:1 DEVICE ID RW 0 DES ID SEL RW I C Device ID Reset 4:2 0x04 ANAPWDN 7-bit address of Deserializer. 0x60'h (0110_000X'b) default. 0: Deserializer DEVICE ID is from IDx. 1: Register I2C DEVICE ID overrides IDx. Reserved. This register can be set only through local I2C access. 1: Analog power-down : Powers down the analog block in the Deserializer. 0: Analog power-up: Powers up the analog block in the Deserializer. RW RSVD Reserved. Digital Reset 1 RW 1: Resets the digital block except for register values. This bit is self-clearing. 0: Normal operation. 0 Digital Reset 0 RW 1: Resets the entire digital block including all register values. This bit is self-clearing. 0: Normal operation. RSVD 0x00 RW 5 4:0 16 RSVD Description 1 7:6 General Configuration 0 Default (Hex) 0xC0 5 0x02 R/W 2 7:6 0x01 Field Reserved. Auto-Clock 1: Output SCK when LOCKED or internal oscillator clock when not LOCKED. 0: Output SCK when LOCKED only. RSVD Reserved. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com Addr (Hex) SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Name Bits Field R/W 7 RX Parity Checker Enable RW Forward channel Parity Checker enable. 1: Enable. 0: Disable. 6 TX CRC Checker Enable RW Back channel CRC Generator enable. 1: Enable. 0: Disable. 5 VDDIO Control RW Auto voltage control. 1: Enable (auto-detect mode). 0: Disable. 4 VDDIO Mode RW VDDIO voltage set. 1: Sets VDDIO mode to 3.3V. 0: Sets VDDIO mode to 1.8V. RW I2C pass-through mode. 1: Pass-through enabled. Refer to I2C PassThrough and Multiple Device Addressing. 0: Pass-through disabled. 0x03 Default (Hex) I2C Pass-Through 3 General Configuration 1 1 0 0x04 EQ Feature Control RW Automatically acknowledge I2C remote writes. This mode should only be used when the system is LOCKED. 1: Enable: When enabled, I2C writes to the Serializer (or any remote I2C slave, if I2C Pass All is enabled) are immediately acknowledged without waiting for the Serializer to acknowledge the write. The accesses are then remapped to address specified in 0x06. 0: Disable. RW Clear parity error counters. This bit is selfclearing. 1: Clear parity error counters. 0: Normal operation. RW SCK clock edge select. 1: Parallel interface data is strobed on the rising clock edge. 0: Parallel interface data is strobed on the falling clock edge. RW Equalization gain: When AEQ bypass is enabled EQ setting is provided by this register. 0x00 = ~0.0 dB. 0x01 = ~4.5 dB. 0x03 = ~6.5 dB. 0x07 = ~7.5 dB. 0x0F = ~8.0 dB. 0x1F = ~11.0 dB. 0x3F = ~12.5 dB. 0xE9 2 7:0 I2C Remote Write Auto Acknowledge Parity Error Reset RRFB EQ Level Description 0x00 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 17 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Addr (Hex) Name Bits 7:1 0x06 0x07 Freeze Device ID 7:1 Serializer Alias ID Default (Hex) Slave ID[0] 7:1 Slave ID[1] 7:1 Description RW This field stores the 7-bit I2C address of the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to SER Alias, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer. This field is automatically configured by the Bidirectional Control Channel once RX LOCK has been detected. Software may overwrite this value, but the Freeze Device ID bit should also be asserted to prevent overwriting by the Bidirectional Control Channel. A value of 0 in this field disables I2C access to the remote Serializer. Refer to I2C PassThrough and Multiple Device Addressing. RW Freeze Serializer Device ID. 1: Prevents auto-loading of the Serializer Device ID from the forward channel. The ID will be frozen at the value written. 0: Allows auto-loading of the Serializer Device ID from the forward channel. RW 0x00 SER Alias 0 18 R/W Remote Serializer Device ID 0 0 0x09 Field SER ID 0 0x08 www.ti.com This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the SER ID register. A value of 0 in this field disables I2C access to the remote Serializer. Refer to I2C PassThrough and Multiple Device Addressing. RSVD Reserved. Slave ID0 This field stores the 7-bit I2C address of remote slave 0, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias0, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 0. A value of 0 in this field disables I2C access to remote slave 0. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave ID1 This field stores the 7-bit I2C address of remote slave 1, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias1, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 1. A value of 0 in this field disables I2C access to remote slave 1. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com Addr (Hex) 0x0A SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Name Slave ID[2] Bits 7:1 0 0x0B Slave ID[3] 7:1 0 0x0C Slave ID[4] 7:1 0 0x0D Slave ID[5] 7:1 0 0x0E Slave ID[6] 7:1 0 Field Slave ID2 R/W RW Default (Hex) 0x00 Description This field stores the 7-bit I2C address of remote slave 2, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias2, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 2. A value of 0 in this field disables I2C access to remote slave 2. Refer to I2C Pass-Through and Multiple Device Addressing. RSVD Reserved. Slave ID3 This field stores the 7-bit I2C address of remote slave 3, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias3, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 3. A value of 0 in this field disables I2C access to remote slave 3. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave ID4 This field stores the 7-bit I2C address of remote slave 4, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias4, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 4. A value of 0 in this field disables I2C access to remote slave 4. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave ID5 This field stores the 7-bit I2C address of remote slave 5, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias5, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 5. A value of 0 in this field disables I2C access to remote slave 5. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave ID6 This field stores the 7-bit I2C address of remote slave 6, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias6, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 6. A value of 0 in this field disables I2C access to remote slave 6. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 19 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Addr (Hex) 0x0F Name Slave ID[7] Bits 7:1 0 0x10 Slave Alias[0] 7:1 0 0x11 Slave Alias[1] 7:1 0 0x12 Slave Alias[2] 7:1 0 0x13 Slave Alias[3] 7:1 0 0x14 Slave Alias[4] 7:1 0 20 www.ti.com Field Slave ID7 R/W RW Default (Hex) 0x00 Description This field stores the 7-bit I2C address of remote slave 7, attached to the remote Serializer. If an I2C transaction (originating from the Deserializer side) is addressed to Slave Alias7, the transaction will be remapped to this address before it is passed across the Bidirectional Control Channel to the remote Serializer, where it is then passed to remote slave 7. A value of 0 in this field disables I2C access to remote slave 7. Refer to I2C Pass-Through and Multiple Device Addressing. RSVD Reserved. Slave Alias ID0 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID0 register. A value of 0 in this field disables I2C access to remote slave 0. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave Alias ID1 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID1 register. A value of 0 in this field disables I2C access to remote slave 1. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave Alias ID2 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID2 register. A value of 0 in this field disables I2C access to remote slave 2. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave Alias ID3 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID3 register. A value of 0 in this field disables I2C access to remote slave 3. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave Alias ID4 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID4 register. A value of 0 in this field disables I2C access to remote slave 4. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com Addr (Hex) 0x15 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Name Slave Alias[5] Bits 7:1 0 0x16 Slave Alias[6] 7:1 0 0x17 Slave Alias[7] 7:1 0 Field Slave Alias ID5 R/W RW Default (Hex) 0x00 Description This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID5 register. A value of 0 in this field disables I2C access to remote slave 5. Refer to I2C Pass-Through and Multiple Device Addressing. RSVD Reserved. Slave Alias ID6 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID6 register. A value of 0 in this field disables I2C access to remote slave 6. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. Slave Alias ID7 This field stores a 7-bit I2C address. Once set, it configures the Deserializer to accept any transaction designated for the I2C address stored in this field. The transaction will then be remapped to the I2C address specified in the Slave ID7 register. A value of 0 in this field disables I2C access to remote slave 7. Refer to I2C Pass-Through and Multiple Device Addressing. RW 0x00 RSVD Reserved. 7:0 Parity Error Threshold Byte 0 0x00 Parity errors threshold on the forward channel during normal information. This sets the maximum number of parity errors that can be counted using register 0x1A. Least significant Byte. RW 0x01 Parity errors threshold on the forward channel during normal operation. This sets the maximum number of parity errors that can be counted using register 0x1B. Most significant Byte. 0x18 Parity Errors Threshold 0x19 Parity Errors Threshold 7:0 Parity Error Threshold Byte 1 0x1A Parity Errors 7:0 Parity Error Byte 0 RW 0x00 Number of parity errors in the forward channel during normal operation. Least significant Byte. 0x1B Parity Errors 7:0 Parity Error Byte 1 RW 0x00 Number of parity errors in the forward channel during normal operation. Most significant Byte. 7:4 Rev-ID 3 RSVD 2 Parity Error R Parity error detector. 1: At least one parity error detected. 0: No parity errors. 1 Signal Detect R 1: Serial input detected. 0: Serial input not detected. 0 Lock R Deserializer's LOCK status. 1: Deserializer LOCKED to recovered clock. 0: Deserializer not LOCKED. 0x1C RW R Revision ID. 0x0000: Production. Reserved. General Status Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 21 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Addr (Hex) Name Bits www.ti.com Field 7 GPIO2 Output Value 6 RSVD R/W RW Default (Hex) Description 0x33 Local GPIO2 Output Value. This value is output on the GPIO2 pin when GPIO2 is enabled, and the local GPIO2 direction is set to output. Reserved. GPIO2 Direction RW Local GPIO2 direction: 1: Input. 0: Output. 5 0x1D 0x1E 0x1F 4 GPIO2 Enable RW GPIO2 enable: 1: Enable GPIO2 operation. 0: TRI-STATE. 3 GPIO3 Output Value RW Local GPIO3 Output Value. This value is output on the GPIO3 pin when GPIO3 is enabled, and the local GPIO3 direction is set to output. 2 RSVD 1 GPIO3 Direction RW Local GPIO3 direction: 1: Input. 0: Output. 0 GPIO3 Enable RW GPIO3 enable: 1: Enable GPIO3 operation. 0: TRI-STATE. 7 GPIO0 Output Value RW Local GPIO0 Output Value. This value is output on the GPIO0 pin when GPIO0 is enabled, and the local GPIO0 direction is set to output. 6 RSVD 5 GPIO0 Direction RW Local GPIO0 direction: 1: Input. 0: Output. 4 GPIO0 Enable RW GPIO0 enable: 1: Enable GPIO0 operation. 0: TRI-STATE. 3 GPIO1 Output Value 2 RSVD 1 GPIO1 Direction RW Local GPIO1 direction: 1: Input. 0: Output. 0 GPIO1 Enable RW GPIO1 enable: 1: Enable GPIO1 operation. 0: TRI-STATE. Allows overriding OEN and OSS_SEL coming from pins. 1: Overrides OEN/OSS_SEL selected by pins. 0: Does NOT override OEN/OSS_SEL selected by pins. GPIO2 and GPIO3 Config GPIO0 and GPIO1 Config OEN and OSS Select RW OEN_OSS Override RW 6 OEN Select RW 5 OSS Select R 0x00 OEN configuration register. OSS_SEL configuration register. RSVD Reserved. BCC Watchdog Timer The BCC Watchdog Timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog timeout value in units of 2ms. This field should not be set to 0. RW BCC Watchdog Control 0xFE 0 Local GPIO1 Output Value. This value is output on the GPIO1 pin when GPIO1 is enabled, and the local GPIO1 direction is set to output. Reserved. 7 7:1 22 Reserved. 0x33 4:0 0x20 Reserved. BCC Watchdog Timer Disable RW Submit Documentation Feedback Bidirectional Control Channel Watchdog Timer enable. 1: Disables BCC Watchdog Timer operation. 0: Enables BCC Watchdog Timer operation. Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com Addr (Hex) SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Name Bits 7 0x21 I2C Pass All R/W Default (Hex) RW I2C Control 1 0x17 RW Internal SDA hold time. This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50ns. 3:0 I2C Filter Depth RW I2C glitch filter depth. This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 10ns. Control channel sequence error detector. This bit indicates a sequence error has been detected in the forward control channel. 1: At least one error has occurred in the forward control channel. 0: No errors have been detected in the forward control channel. 7 Forward Channel Sequence Error R 6 Clear Sequence Error RW 5 RSVD Reserved. SDA Output Delay SDA output delay. This field configures the output delay on the SDA output. Setting this value will increase the output delay in units of 50 ns. Nominal output delay values for SCL to SDA are: 00: 350 ns 01: 400 ns 10: 450 ns 11: 500 ns Clears the Forward Channel Sequence Error bit. RW RW Disable remote writes to local registers. Setting this bit to 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C Master attached to the Serializer. Setting this bit does not affect remote access to I2C slaves at the Deserializer. RW Speed up I2C bus Watchdog Timer. 1: Watchdog Timer expires after approximately 50 microseconds. 0: Watchdog Timer expires after approximately 1 second. I2C Bus Timer Disable RW The I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus is assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL. 1: Disable the I2C bus Watchdog Timer. 0: Enable the I2C bus Watchdog Timer. GPCR[7:0] RW I2C Control 2 0x00 Local Write Disable 2 1 0 General Purpose Control Pass-through all I2C transactions. For an explanation of I2C pass-through, refer to I2C Pass-Through and Multiple Device Addressing. 1: Enable pass-through of all I2C accesses to I2C IDs that do not match the Deserializer I2C ID. The I2C accesses are then remapped to the address specified in register 0x06. 0: Enable pass-through only of I2C accesses to I2C IDs matching either the remote Serializer I2C ID or the remote slave I2C ID. I2C SDA Hold Time 2 0x23 Description 6:4 4:3 0x22 Field 7:0 I C Bus Timer Speedup 0x00 Scratch Register. Used to write and read 8 bits. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 23 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Addr (Hex) Name Bits 7:4 3 0x24 BIST Control 2:1 0 0x25 Parity Error Count 0x3F CML Output Enable 0x41 SCL High Time SCL Low Time 0x4D 24 BIST Clock Source RW BIST clock source: See (Table 1) BIST Enable RW BIST register enable (active if 0x24[3] is set to 0): 1: Enabled. 0: Disabled. CML OUT Enable R 0x00 Number of forward channel parity errors during the BIST. 0x10 Reserved. 1: CML loop-through driver is powered down. 0: CML loop-through driver is powered up. RW RSVD Reserved. SCL High Time 0x82 I2C Master SCL high time. This field configures the high pulse width of the SCL output when the Deserializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to satisfy a minimum (4 μs + 0.3 μs of rise time for cases where rise time is very fast) SCL high time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz. 0x82 I2C Master SCL low time. This field configures the low pulse width of the SCL output when the Deserializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to satisfy a minimum (4.7 µs + 0.3 µs of fall time for cases where fall time is very fast) SCL low time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz. 0x00 Reserved. SCL Low Time 7:2 RSVD 7 6 0x4E BIST configuration select: 1: BIST configured through pin. 0: BIST configured through register bit 0x24[0]. Force Back Channel Error RW RW RW 1: This bit introduces multiple errors into the back channel frame. 0: No effect. RW 1: This bit introduces ONLY one error into the back channel frame. This bit is also self clearing. 0: No effect. CRC Force Error AEQ Test Mode Select EQ Value Reserved. RW 7:0 0 Description BIST Pin Configuration RSVD 7:0 Default (Hex) 0x08 7:5 4 R/W RSVD BIST Error Count 1 0x42 Field 7:0 3:0 0x40 www.ti.com Force One Back Channel Error RSVD 0x20 AEQ Bypass 5:0 RSVD 7:0 AEQ / Manual Eq Readback RW Reserved. Bypass AEQ and use manual EQ. Set value using register 0x04. Reserved. R Submit Documentation Feedback Read back the equalization value (adaptive or manual). Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 FUNCTIONAL DESCRIPTION The DS90UA101-Q1/DS90UA102-Q1 chipset is intended to link digital audio sources with remote audio converters and DSPs. The chipset can operate from a reference clock of 10MHz to 50MHz. The DS90UA101-Q1 device serializes up to an 8 audio inputs and 4 general purpose inputs, along with a bidirectional control channel, into a single high-speed differential pair or single-ended coaxial cable. The high speed serial bit stream contains an embedded clock and DC-balanced information to enhance signal quality and support AC coupling. The DS90UA102-Q1 device receives the single serial data stream and converts it back to digital audio outputs, control channel data, and general purpose outputs (GPOs). The DS90UA101-Q1/DS90UA102-Q1 chipset can accept up to 8 audio data inputs, bit clock (BCK), word clock (LRCK), and an input reference clock (SCK) ranging from 10 MHz to 50 MHz. The control channel function of the chipset provides bidirectional communication between the two ends of the link, such as a digital signal processor (DSP) on one end and an audio digital-analog converter (DAC) on the other. The integrated Bidirectional Control Channel transfers data bidirectionally over the same differential pair used for audio data interface. This interface offers advantages over other chipsets by eliminating the need for additional wires for programming and control. The Bidirectional Control Channel bus is controlled via an I2C port, available on both the Serializer and Deserializer. Transmission Media The DS90UA101-Q1/DS90UA102-Q1 chipset is intended to be used in a point-to-point data link through a shielded twisted pair (STP) or coaxial (coax) cable. The Serializer and Deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connectors) should have a differential impedance of 100Ω, or a single-ended impedance of 50Ω. The maximum length of cable that can be used is dependent on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), and the electrical environment (for example, power stability, ground noise, input clock jitter, SCK frequency, etc). The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. This can be done by measuring the output of the CMLOUTP/N pins. These pins should each be terminated with a 0.1 µF capacitor in series with a 50Ω resistor to GND. Figure 10 illustrates the minimum eye width and eye height that is necessary for bit error free operation. Operation with Audio System Clock as Reference Clock The DS90UA101-Q1/DS90UA102-Q1 chipset is operated using the audio system clock (SCK) from the digital audio source. The audio data, LRCK, and BCK inputs are clocked into the Serializer using SCK. Up to 4 GPI inputs are also sampled and transported along with the digital audio inputs. Figure 13 shows the operation of the Serializer and Deserializer with the reference clock. Serializer Deserializer Forward Channel DOUT+ RIN+ DOUT[7:0] DIN[7:0] LRCK LRCK DOUT- BCK Bidirectional Control Channel SDA DSP BCK RIN- SCL SCK GPI[3:0] GPO[3:0] GPO[3:0] GPIO[3:0] SCK DAC SDA PLL SCL REF Figure 13. Operation with SCK Reference Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 25 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com The Serializer switches over to an internal reference clock when SCK is idle or missing. This frequency is selectable via the device control registers, as shown below (Table 1). Table 1. Internal Oscillator Frequencies for Forward Channel Frame during Normal Operation DS90UA101-Q1 Reg 0x14 [2:1] Frequency (MHz) 00 ~25 01 ~50 10 ~25 11 ~12.5 Line Rate Calculations for the DS90UA101-Q1/DS90UA102-Q1 The following formula is used to calculate the line rate for the DS90UA101-Q1/DS90UA102-Q1 chipset: • Line rate = ƒSCK * 28 For example, for maximum line rate, ƒSCK= 50 MHz, line rate = 50 * 28 = 1.4 Gbps. Serial Frame Format The high speed forward channel is composed of 28 bits of data containing digital audio data, sync signals, I2C and parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, balanced and scrambled. The Bidirectional Control Channel data is transferred over the single serial link along with the high-speed forward data. This architecture provides a full duplex, low speed control path across the serial link together with the high speed forward channel. Serial Audio Formats There are several de-facto industry standards or formats that define the required alignments and signal polarities between the left/right clock (LRCK), bit clock (BCK) and the serial audio data. Hence, this section is dedicated to discussing various serial audio formats. I2S Format An I2S bus uses three signal lines for data transfer – a frame or word clock (LRCK), a bit clock (BCK), and a single or multiple data lines. The device which generates the appropriate BCK and LRCK signals on the bus is called Master, whereas other devices which accept BCK and LRCK as inputs are all slaves. Bit Clock (BCK) The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency must be greater than or equal to the product of the sample rate, the number of bits per sample and the number of channels (which is 2 in normal stereo operation). Word Select (LRCK) The word select line indicates the channel being transmitted: • LRCK = 0; channel 1 (left); • LRCK = 1; channel 2 (right). The LRCK line changes one clock period before the MSB is transmitted (Figure 14). This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. Serial Data (DATA) Serial data is transmitted in two’s complement with the MSB first (as shown in Figure 14). The MSB is transmitted first because the transmitter and receiver may have different word lengths. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. LEFT Channel Data LRCK RIGHT Channel Data BCK DIN 2 1 MSB 0 LSB 2 1 MSB 0 LSB Figure 14. Stereo I2S Format Left Justified Format In this format, MSB of the word appears in synchronization with the LRCK edges. Unlike in I2S mode, there is no lag between Data and LRCK. Left channel data word begins at falling edge of LRCK and right channel data word begins on rising edge of the LRCK signal. Hence, as can be seen from below waveforms (Figure 15), data appears to be left justified. RIGHT Channel Data LRCK LEFT Channel Data BCK DIN 2 MSB 1 0 LSB 2 MSB 1 0 N LSB Figure 15. Left-Justified Format Right Justified Format In this format, LSB of the word appears just before the LRCK edges. Left channel data word may begin at any point depending upon the word length, but LSB of this data word must appear just before the rising edge of the LRCK signal. Similarly, LSB of the right channel data word must appear just before falling edge of the LRCK signal. Hence, as can be seen from below waveforms(Figure 16), data appears to be right justified. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 27 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 LRCK www.ti.com RIGHT Channel Data LEFT Channel Data BCK DIN 0 2 1 0 MSB 2 LSB 1 MSB 0 LSB Figure 16. Right-Justified Format TDM Format There are no well defined rules for TDM format and it can be implemented in large number of ways depending upon the word length, bit clock, number of channels to be multiplexed, etc. For example, let’s assume that word clock signal (LRCK) period = 256 * bit clock (BCK) time period. In this case, we can multiplex 4 channels with maximum word length of 64 bits each, or 8 channels with maximum word length of 32 bits each. Figure 17 illustrates the multiplexing of 8 channels with 24 bit word length, in a format similar to I2S. Pulse width of LRCK can be used to define a clock period for BCK or to define a slot period, i.e., the period for which individual channel can be active on the shared data line. If the number of audio channels is more than 8, DS90UA101-Q1/DS90UA102-Q1 can easily support multiplexed data with additional devices to multiplex and de-multiplex the data. The number of channels multiplexed on each data line must be selected as a power of 2, that is, 2/ 4/ 8. t1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)t LRCK BCK I2S Mode DIN1 (Single) Ch 1 t32 BCKst Ch 2 t32 BCKst Ch 3 t32 BCKst Ch 4 t32 BCKst Ch 5 t32 BCKst Ch 6 t32 BCKst Ch 7 t32 BCKst Ch 8 t32 BCKst 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 0 0 0 0 0 0 0 0 23 22 Figure 17. TDM Format Error Detection The chipset provides error detection operations for validating data integrity in long distance transmission and reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data transmission error checking. The error detection operating modes support data validation of the following signals: • Bidirectional Control Channel data across the serial link • Parallel audio/sync data across the serial link The chipset provides 1 parity bit on the forward channel and 4 CRC bits on the back channel for error detection purposes. The DS90UA101-Q1/DS90UA102-Q1 chipset checks the forward and back channel serial links for errors and stores the number of detected errors in two 8-bit registers in the Serializer and the Deserializer, respectively. 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the Deserializer. If there is a loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on the forward channel, the PASS pin will go low momentarily. To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer. Bidirectional Control Bus and I2C S Register Address Slave Address 7-bit Address A C K Bus Activity: Slave Slave Address S 0 N A C K 7-bit Address A C K Stop SDA Line Start Bus Activity: Master Start The I2C compatible interface allows programming of the Serializer, Deserializer, or an external remote device through the Bidirectional Control Channel. For example, an audio module connected to the Deserializer can communicate with the ADC connected to the Serializer using the Bidirectional Control Channel. Register programming transactions to/from the chipset are employed through the clock (SCL) and data (SDA) lines. These two signals have open drain I/Os and both lines must be pulled-up to VDDIO by an external resistor. Pull-up resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the output and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The DS90UA101-Q1/DS90UA102-Q1 I2C bus data rate supports up to 400 kbps according to I2C fast mode specifications. Figure 18, Figure 19, Figure 20, Figure 21 show I2C waveforms of read/write bytes, basic operation, and start/stop conditions. P 1 A C K Data SDA Line S Register Address Slave Address 7-bit Address Data P 0 A C K A C K A C K Bus Activity: Slave Stop Bus Activity: Master Start Figure 18. Read Byte Figure 19. Write Byte SDA 1 2 START 6 MSB LSB R/W Direction Bit Acknowledge from the Device 7-bit Slave Address SCL ACK LSB MSB 7 8 9 N/ACK Data Byte *Acknowledge or Not-ACK 1 2 8 Repeated for the Lower Data Byte and Additional Data Transfers 9 STOP Figure 20. Basic Operation Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 29 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com SDA SCL S P STOP condition START condition, or START repeat condition Figure 21. Start and Stop Conditions IDx Address Decoder on the Deserializer The IDx pin (Figure 22) on the Deserializer is used to decode and set the I2C address of the Deserializer. There are 4 possible I2C addresses that can be set on the Deserializer. The pin must be pulled to VDD (1.8V, not VDDIO) with a 10 kΩ resistor and a pull down resistor RID) of the recommended value to set the I2C address of the Deserializer (Table 2). The recommended maximum resistor tolerance is 1%. 1.8V 10kQ VDDIO IDx RPU RPU RID HOST Deserializer SCL SCL SDA SDA To other Devices Figure 22. IDx Address Select Table 2. Resistor Values for IDx on DS90UA102-Q1 Deserializer IDx Resistor Value Resistor RID (kΩ) (1%Tolerance) 7-Bit Address 8-Bit Address (0 appended) 0 0x60 0xC0 3 0x61 0xC2 11 0x62 0xC4 100 0x63 0xC6 Note: The I2C address of the Deserializer can also be set using 0x00[7:1] once 0x00[0] is set to 1. 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 I2C Pass-Through I2C pass-through is the feature that provides a way to access remote devices at the other end of the serial interface. For example, when the I2C Master is connected to the Deserializer and I2C pass-through is enabled on the Deserializer, any I2C traffic targeted for the remote Serializer or remote slave will be allowed to pass through the Deserializer to reach those respective devices. See Figure 23 for an example of this function: • If Master (DSP) transmits an I2C transaction for SER A, then DES A with I2C pass-through enabled will transfer that I2C command to SER A. Responses from SER A will travel from SER A --> DES A --> DSP. • If Master transmits an I2C transaction for address 0xA0, then DES A with I2C pass-through enabled will transfer that I2C command to SER A, which will then transfer it to remote slave Device A. Responses from Device A will travel from Device A --> SER A --> DES A --> DSP. • As for DES B with I2C pass-through disabled, any I2C commands for SER B or Device B will NOT be passed on the I2C bus to SER B/Device B. Serializer A Digital Audio Source DIN[7:0], BCK,LRCK SCK SDA SCL Device A Remote Slave ID: (0xA0) DOUT[7:0], BCK,LRCK, SCK I2C SER A: Remote I2C Master Proxy Serializer B Digital Audio Source Deserializer A I2C DES A: Local I2C Slave Pass-Through Enabled Device B Remote Slave ID: (0xA0) DSP Deserializer B DIN[7:0], BCK,LRCK SCK SDA SCL SDA SCL DOUT[7:0], BCK,LRCK, SCK I2C SER B: Remote I2C Master Proxy I2C SDA SCL DES B: Local I2C Slave Pass-Through Disabled Master Figure 23. I2C Pass-Through To setup I2C pass-through on the Serializer, set 0x03[2] = 1 and configure registers 0x06, 0x07, 0x08, and 0x09 as needed (Deserializer I2C ID, Deserializer Alias ID, remote slave I2C ID, remote slave Alias ID, respectively). Refer to Multiple Device Addressing for information about Alias IDs and refer to DS90UA102-Q1 REGISTER INFORMATION for information to set these registers. To communicate with the remote Deserializer from the Serializer side, registers 0x06 and 0x07 must be configured (register 0x06 is auto-loaded by default if there is LOCK). To communicate with the remote slave connected to the remote Deserializer, configure registers 0x08 and 0x09. To setup I2C pass-through on the Deserializer, set 0x03[3] = 1 and configure registers 0x06 - 0x17 as needed. To communicate with the remote Serializer from the Deserializer side, registers 0x06 and 0x07 must be configured (register 0x06 is auto-loaded by default if there is LOCK). To communicate with one or more remote slaves connected to the remote Serializer, configure 0x08 - 0x17 accordingly. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 31 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Multiple Device Addressing Some applications require multiple devices with the same fixed address to be accessed on the same I2C bus. The DS90UA101-Q1/DS90UA102-Q1 provides slave ID aliasing to generate different target slave addresses when connecting two or more identical devices remotely. Instead of addressing their actual I2C addresses, each remote device can be addressed through a unique alias ID by programming the Slave Alias ID register on the Serializer/Deserializer. By addressing the Slave Alias IDs, I2C slaves with identical, fixed addresses can now be addressed independently. On the DS90UA101-Q1, up to 1 Slave Alias ID index is supported. On the DS90UA102-Q1, up to 8 Slave Alias IDs can be supported. The Audio Module/DSP (I2C Master) must keep track of the alias list in order to properly address the correct device. Refer to Figure 24 for an example of this function: • There is a local I2C bus between Audio Module, DES A, and DES B. Audio Module is the I2C Master, and DES A and DES B are I2C slaves. • The I2C protocol is bridged from DES A to SER A and from DES B to SER B. SER A is the master of its own local I2C bus, and Source A and its µC/EEPROM are slaves on this bus. SER B is also the master of its local I2C bus, and Source B and its µC/EEPROM are the slaves. • Audio Module can now address remote slaves connected to SER A and SER B independently. • Case 1: If Audio Module transmits to I2C slave 0xA0, DES A (address 0xC0) will forward the transaction to SER A, which then forwards it to remote slave Source A. Responses from Source A will travel from Source A --> SER A --> DES A --> Audio Module. • Case 2: If Audio Module transmits to slave address 0xA4, DES B (address 0xC2) will recognize that 0xA4 is mapped to 0xA0 and will transmit the command to SER B, which then forwards it to remote slave Source B. Responses from Source B will travel from Source B --> SER B --> DES B --> Audio Module. • Case 3: If Audio Module sends command to address 0xA6, DES B (address 0xC2) will forward the transaction to SER B, which then forwards it to Source B's µC/EEPROM. Responses from Source B's µC/EEPROM will travel from Source B's µC/EEPROM --> SER B --> DES B --> Audio Module. Source A Serializer A Slave ID: (0xA0) Digital Audio Source DIN[7:0], BCK, LRCK, SCK DOUT[7:0], BCK, LRCK, SCK 2 SDA SCL I C SER A: ID[x] (0xB0) PC/ EEPROM Slave ID: (0xA2) Source B Serializer B Slave ID: (0xA0) Digital Audio Source Deserializer A DES A: ID[x] (0xC0) SLAVE ID0 (0xA0) SLAVE ALIAS ID0 (0xA0) SLAVE ID1 (0xA2) SLAVE ALIAS ID1 (0xA2) PC/ EEPROM Slave ID: (0xA2) Audio Module Deserializer B DOUT[7:0], BCK, LRCK, SCK DIN[7:0], BCK, LRCK, SCK SDA SCL SDA SCL 2 I C 2 I C SER B: ID[x] (0xB2) 2 I C SDA SCL DES B: ID[x] (0xC2) SLAVE ID0 (0xA0) SLAVE ALIAS ID0 (0xA4) SLAVE ID1 (0xA2) SLAVE ALIAS ID1 (0xA6) DSP Master Figure 24. Multiple Device Addressing 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 NOTE Note: The alias ID must be set in order to communicate with any remote device. For example: • When there is only one SER/DES pair and no remote slaves: if I2C Master on the DES side wants to communicate with the remote SER, I2C pass-through must be enabled on the DES and the SER Alias ID must also be set before the I2C Master can communicate with the remote SER (the SER ID is automatically configured by default if there is LOCK). • When there is only one SER/DES pair and one remote slave connected to the SER: if I2C Master on the DES side (with pass-through enabled) wants to communicate with the remote slave, the Slave ID and Slave Alias ID must be set before the I2C Master can communicate with the remote slave, even if there is only one remote slave. Slave Clock Stretching To communicate and synchronize with remote devices on the I2C bus through the Bidirectional Control Channel, the chipset utilizes bus clock stretching (holding the SCL line low) during data transmission. On the 9th clock of every I2C transfer (before the ACK signal), the local I2C slave pulls the SCL line low until a response is received from the remote I2C bus located on the other end of the serial interface. The slave device will not control the clock and only stretches it until the remote peripheral has responded. The I2C Master must support slave clock stretching in order to communicate with remote devices. General Purpose Inputs, Outputs (GPIs, GPOs, GPIOs) Descriptions There are 4 dedicated general purpose inputs (GPIs) on the DS90UA101-Q1 and 4 dedicated general purpose outputs (GPOs) on the DS90UA102-Q1. Inputs to the GPI pins on the Serializer are fed to the GPO outputs on the Deserializer. The maximum GPI data rate is defined by the SCK source (up to 50 Mbps). In addition, there are also 4 GPOs on the DS90UA101-Q1 and 4 GPIOs on the DS90UA102-Q1. The GPOs on the Serializer can be configured as outputs for the input signals that are fed into the Deserializer GPIOs. The GPIO maximum data rate is up to 66 kbps when configured for communication between Deserializer GPIO to Serializer GPO. Both the GPOs on the Serializer and GPIOs on the Deserializer can also behave as outputs whose values are set from local registers. LVCMOS VDDIO Option 1.8V/3.3V Deserializer outputs are user configurable to provide compatibility with 1.8V and 3.3V system interfaces. Power Up Requirements and PDB Pin The Deserializer is active when the PDB pin is driven HIGH. Driving the PDB pin LOW powers down the device and clears all control register configurations to default values. The PDB pin must be held low until the power supplies (VDDn and VDDIO) have settled to the recommended operating voltage. This can be done by driving PDB externally, or an external RC network can be connected to the PDB pin to ensure PDB arrives after all the power supplies have stabilized. Powerdown The PDB pin's function on the Deserializer is to ENABLE or powerdown the device. This pin can be controlled by the system and can be used to disable the DES to save power. When PDB = HIGH, the DES will lock to the input stream and assert the LOCK pin (HIGH) and output valid data. When PDB = LOW, all outputs are in TRISTATE. SCK Clock Edge Select (RRFB) The RRFB selects which edge of the output clock that the data is strobed on. If RRFB register is 1, data is strobed on the rising edge of SCK. If RRFB register is 0, data is strobed on the falling edge of SCK. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 33 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com SCK ROUT TRFB: 0 TRFB: 1 Figure 25. Programmable SCK Strobe Select Built In Self Test (BIST) An optional at-speed built in self test (BIST) feature supports the testing of the high speed serial link and lowspeed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for system diagnostics. BIST Configuration and Status The DS90UA101-Q1/DS90UA102-Q1 chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is controlled through pins on the DS90UA102-Q1. BIST can be configured via registers using BIST Control Register 0x24, also on the DS90UA102-Q1. Pin based configuration is defined as follows: • BISTEN (on DS90UA102-Q1) = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode. • GPIO3 and GPIO2 of DS90UA102-Q1: Defines the BIST clock source (SCK vs. various internal oscillator frequencies). See Table 3 below. Table 3. BIST Pin Configuration on DS90UA102-Q1 Deserializer (1) (1) DS90UA102-Q1 Deserializer GPIO[3:2] Oscillator Source BIST Frequency (MHz) 00 External SCK 01 Internal ~25 10 Internal ~50 11 Internal ~12.5 Note: These pin settings will only be active when 0x24[3] = 1 and BIST is on. The BIST mode provides various options for the clock source. Either external pins (GPIO3 and GPIO2 of DES) or register 0x24 on DES can be used to configure the BIST to use SCK or various internal oscillator frequencies as the clock source. Refer to Table 4 below for BIST register settings. Table 4. BIST Register Configuration on DS90UA102-Q1 Deserializer (1) (1) DS90UA102-Q1 Deserializer 0x24[2:1] Oscillator Source BIST Frequency (MHz) 00 External SCK 01 Internal ~50 10 Internal ~25 11 Internal ~12.5 Note: These register settings will only be active when 0x24[3] = 0 and BIST is on. The BIST status can be monitored real time on the PASS pin. For every frame with error(s), the PASS pin toggles low momentarily. If two consecutive frames have errors, PASS will toggle twice to allow counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status momentarily (pass = no errors, fail = one or more errors). The BIST result can also be read through I2C for the number of frames that errored. The status register retains results until it is reset by a new BIST session or a device reset. For all practical purposes, the BIST status can be monitored from the BIST Error Count Register 0x25 on the DS90UA102-Q1 Deserializer. 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 Sample BIST Sequence (Refer to Figure 26) Step 1: BIST mode is enabled via the BISTEN pin on the DS90UA102-Q1 Deserializer, or through the Deserializer control registers. The clock source is selected through the GPIO3 and GPIO2 pins as shown in Table 3. Step 2: The DS90UA101-Q1 Serializer BIST start command is activated through the back channel. Step 3: The BIST pattern is generated and sent through the serial interface to the Deserializer. Once the Serializer and Deserializer are in the BIST mode and the Deserializer acquires LOCK, the PASS pin of the Deserializer goes high and BIST starts checking the data stream. If an error in the payload is detected the PASS pin will switch low momentarily. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 4: To stop the BIST mode, the Deserializer BISTEN pin is set low and the Deserializer stops checking the data. The final test result is not maintained on the PASS pin. To check the number of BIST errors, check the BIST Error Count register, 0x25 on the Deserializer. The link returns to normal operation after the Deserializer BISTEN pin is low. Figure 27 below shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission, adaptive equalization, etc.), thus they may be introduced by greatly extending the cable length, increasing the frequency, or by reducing signal condition enhancements (Rx equalization). Normal Step 1: DES in BIST BIST Wait Step 2: Wait, SER in BIST BIST start Step 3: SER/DES in BIST ± monitor PASS BIST stop Step 4: DES/SER in Normal, check register 0x25 on DES Figure 26. AT-Speed BIST System Flow Diagram DES Outputs BISTEN (DES) LOCK SCK (RFB = L) Case 1 - Pass SSO DOUT[7:0] DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal Case 2 - Fail X = bit error(s) DATA (internal) BIST Test BIST Duration BIST Result Held Normal Figure 27. BIST Timing Diagram Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 35 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL) When PDB is driven HIGH, the Deserializer’s CDR PLL begins locking to the serial input. After the DS90UA102Q1 completes its LOCK sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock have been recovered from the serial input and are available on the parallel bus and SCK outputs. The states of the outputs are based on the serial interface input to the Deserializer, OEN, and OSS_SEL setting as shown below (Table 5). See Figure 11. Table 5. Output States (1) (2) Inputs Outputs Serial Interface PDB Input to DES OEN OSS_SEL LOCK PASS DATA SCK X 0 X X Z Z Z Z X 1 0 0 L or H L L L X 1 0 1 L or H Z Z Z Static 1 1 0 L L L L/Internal Oscillator (Register bit enable 0x02[5]) Static 1 1 1 L H L L Active 1 1 0 H L L L Active 1 1 1 H Valid Valid Valid (1) (2) X: Don't Care. Z: TRI-STATE. Deserializer – Adaptive Input Equalization(AEQ) The receiver inputs provide an adaptive input equalization filter in order to compensate for signal degradation from the interconnect components. The level of equalization can also be manually selected via register controls. The equalized output can be seen using the CMLOUTP/CMLOUTN pins on the Deserializer. There are limits to the amount of loss that can be compensated. These limits are defined by the gain curve of the equalizer shown in Figure 28. This figure illustrates the maximum allowable interconnect loss for coax/STP cable with the equalizer at various gain settings. In order to determine the maximum cable reach, other factors that affect signal integrity such as jitter, skew, ISI, crosstalk, etc. need to be taken into consideration. 25 EFFECTIVE GAIN (dB) 20 15 DES Equalizer Gain (dB) VOD-Vswing Loss - STP 10 VOD-Vswing Loss - COAX Allowable Interconnect Loss - STP Allowable Interconnect Loss - COAX 5 0 100 200 300 400 500 600 700 SERIAL LINE FREQUENCY (MHz) Figure 28. Maximum Equalizer Gain vs. Line Frequency (STP) EMI Reduction : Deserializer Staggered Output The receiver staggers output switching to provide a random distribution of transitions within a defined window. Output transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI. 36 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 APPLICATIONS INFORMATION AC Coupling The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced coding scheme. External AC coupling capacitors must be placed in series with the serial interface signal path as illustrated in Figure 29 or Figure 30. Applications utilizing STP cable require a 0.1 μF coupling capacitor on both outputs (DOUT+, DOUT–). Applications utilizing single-ended 50Ω coaxial cable require a 0.1 μF capacitor on the true serial interface output (DOUT+). The unused data pin (DOUT-) requires a 0.0 47 μF capacitor coupled to a 50Ω resistor to GND. DOUT+ RIN+ DOUT- RIN- SER DES Figure 29. AC-Coupled Connection (STP) DOUT+ RIN+ SER DES DOUT- 50Q 50Q RIN- Figure 30. AC-Coupled Connection (Coaxial) For high-speed serial transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. Typical Application Connection Figure 31 and Figure 32 show typical application connections of the DS90UA102-Q1 Deserializer. The serial interface inputs must have external 0.1 µF coupling capacitors connected to the high-speed interconnect. The Deserializer has internal termination. Bypass capacitors are placed near the power supply pins. Ferrite beads should also be used for effective noise suppression. The digital audio electrical interface is LVCMOS format. The VDDIO pin may be connected to 3.3V or 1.8V. Device I2C address select is configured via the IDx pin. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 37 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com DS90UA102-Q1 1.8V VDDD C3 C11 C4 C12 C5 C13 VDDIO VDDIO C8 VDDR C16 C18 VDDIO C9 VDDR VDDIO C10 1.8V VDDPLL C6 FB1 C14 C17 1.8V VDDCML FB2 C7 C19 C15 VDDCML SCK LRCK BCK DOUT0 DOUT1 DOUT2 DOUT3 Digital Audio Interface DOUT4 DOUT5 DOUT6 DOUT7 C1 RIN+ Serial Interface RINC2 GPIO0 GPIO1 GPIO2 GPIO3 GPIO Interface PDB OEN OSS_SEL BISTEN GPO0 GPO1 GPO2 GPO3 GPO Interface LOCK PASS 1.8V 10 kQ IDx RID VDDIO RPU 2 IC Bus Interface RPU SCL SDA RES0 DAP (GND) NOTE: C1 - C2 = 0.1 µF (50 WV) C3 - C10 = 0.01 µF C11 - C16 = 0.1 µF C17 - C18 = 4.7 µF C19 = 22 µF RPU = 4.7 kQ RID (see IDx Resistor Value Table) FB1, FB2: Impedance = 1 kQ (@ 100 MHz) low DC resistance (<1Q) All RES0 pins should be tied to GND All RES1 pins should be left floating Figure 31. Typical Connection Diagram (STP Cable) 38 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 DS90UA102-Q1 www.ti.com SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 DS90UA102-Q1 1.8V VDDD C3 C11 C4 C12 C5 C13 VDDIO VDDIO C8 VDDR C16 C18 VDDIO C9 VDDR VDDIO C10 1.8V VDDPLL C6 FB1 C14 C17 1.8V VDDCML C7 FB2 C19 C15 VDDCML SCK LRCK BCK DOUT0 DOUT1 DOUT2 DOUT3 Digital Audio Interface DOUT4 DOUT5 DOUT6 DOUT7 C1 RIN+ Serial Interface RIN50Q C2 GPIO0 GPIO1 GPIO2 GPIO3 GPIO Interface PDB OEN OSS_SEL BISTEN GPO0 GPO1 GPO2 GPO3 GPO Interface LOCK PASS 1.8V 10 kQ IDx RID VDDIO RPU 2 IC Bus Interface RPU SCL SDA RES0 DAP (GND) NOTE: C1 = 0.1 µF (50 WV) C2 = 0.047 µF (50 WV) C3 - C10 = 0.01 µF C11 - C16 = 0.1 µF C17 - C18 = 4.7 µF C19 = 22 µF RPU = 4.7 kQ RID (see IDx Resistor Value Table) FB1, FB2: Impedance = 1 kQ (@ 100 MHz) low DC resistance (<1Q) All RES0 pins should be tied to GND All RES1 pins should be left floating Figure 32. Typical Connection Diagram (Coax Cable) PCB Layout and Power System Considerations Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 39 DS90UA102-Q1 SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50 µF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential lines of 100Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the LLP style package is provided in TI Application Note AN-1187. Interconnect Guidelines See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – – S = space between the pair – – 2S = space between pairs – – 3S = space to LVCMOS signal • Minimize the number of Vias • Use differential connectors when operating above 500 Mbps line speed • Maintain balance of the traces • Minimize skew within the pair Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instrument web site at: www.ti.com/lvds 40 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA102-Q1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) DS90UA102TRHSJQ1 ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UA102Q DS90UA102TRHSRQ1 ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UA102Q DS90UA102TRHSTQ1 ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UA102Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90UA102TRHSJQ1 WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS90UA102TRHSRQ1 WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS90UA102TRHSTQ1 WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UA102TRHSJQ1 WQFN RHS 48 2500 367.0 367.0 38.0 DS90UA102TRHSRQ1 WQFN RHS 48 1000 367.0 367.0 38.0 DS90UA102TRHSTQ1 WQFN RHS 48 250 213.0 191.0 55.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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