Freescale Semiconductor, Inc. HYBRID MCU/DSP 56852 120 MIPS Hybrid Processor Freescale Semiconductor, Inc... TARGET APPLICATIONS • Full duplex feature phones • Voice activated toys • Voice recognition and command • Musical effects equipment • Karaoke systems • Voice and audio processing • General purpose applications • Automotive hands-free BENEFITS • 120 MIPs at under $3 in high volume • Hybrid MCU/DSP architecture, removes need for separate MCU in many cases • Large linear address spaces, up to 4MB program and data, supporting complex communications stacks • Available in a space saving 81MAPBGA package • Supported by Metrowerks Codewarrior IDE, allowing rapid application development in C • Non intrusive debug via JTAG/OnCE port • Processor Expert™ rapid application design (RAD) tool available including algorithms and drivers 56852 16-BIT DIGITAL SIGNAL PROCESSORS The first device in the 56800E family, the 56852 sets a new price per performance standard, offering 120 MIPS below $3.00 at high volume. The 56852 integrates 12 KB of program SRAM and 8 KB of data SRAM, a quad timer module with two external outputs, a serial peripheral interface (SPI) multiplexed with an improved synchronous serial interface (ISSI), and a serial communication interface (SCI/UART). With 20 KB on-chip SRAM and multiple serial peripherals in an 81-pin MBGA package, the 56852 can easily be integrated into a previously designed system where a DSP co-processor is needed and system board real estate is at a premium. However, with up to 4 MB program or up to 12 MB of data addressing space for off-chip memory, the 56852 is also a powerful stand-alone processor ideal for telephony applications, speech processing and recognition, embedded modems, audio processing, such as 3D virtualization and other digital effects, echo cancellation, magnetic and smart card readers, and feature phones. COP/Watchdog • 120 MIPS at 120MHz • Interrupt Controller • 12 KB Program SRAM • General purpose 16-bit Quad Timer • 8 KB Data SRAM • JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging • 2 KB Boot ROM • Access up to 4 MB of program memory or up to 12 MB of data memory • One Serial Peripheral Interface (SPI) or one Improved Synchronous Serial Interface (ISSI) • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs 12 KB SRAM SPI or ISSI SCI Up to 11 GPIO 16-Bit Quad Timer • Up to 11 GPIO ENERGY INFORMATION Program Memory 2 KB Boot ROM • 81-pin MAPBGA package • One Serial Communication Interface (SCI) Ext Memory I/F Prog Chip Selects • Computer Operating Properly (COP)/Watchdog Timer 56800E Core 120 MIPS Data Memory PLL 8 KB SRAM JTAG/EOnCE For More Information On This Product, Go to: www.freescale.com • Wait and Stop modes available Freescale Semiconductor, Inc. 56800E CORE FEATURES HYBRID MCU/DSP The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. Features of the 56800E core include: 56852 PRODUCT DOCUMENTATION DSP56800E Reference Manual Freescale Semiconductor, Inc... DSP56852 User’s Manual DSP56852 Technical Data Sheet DSP56852 Product Brief Detailed description of the 56800E architecture, 16-bit DSP core processor and the instruction set • Efficient 16-bit hybrid controller engine with dual Harvard architecture • Four internal data buses and one external data bus Order Number: DSP56800ERM/D • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Instruction set supports both DSP and controller functions Detailed description of memory, peripherals, and interfaces of the 56852 • Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) • Four hardware interrupt levels Order Number: DSP56852UM/D • Four 36-bit accumulators, including extension bits • Controller-style addressing modes and instructions for compact code • 16-bit bidirectional shifter • Efficient C compiler and local variable support Electrical and timing specifications, pin descriptions, and package descriptions Order Number: DSP56852/D Summary description and block diagram of the core, memory, peripherals and interfaces Order Number: DSP56852PB/D AWARD-WINNING DEVELOPMENT ENVIRONMENT • Parallel instruction set with unique addressing modes • Hardware DO and REP loops • Software subroutine and interrupt stack with depth limited only by memory • Three internal address buses and one external address bus • JTAG/Enhanced OnCE debug programming interface 56852 MEMORY FEATURES • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Off-Chip Memory Expansion • On-chip Memory: • Chip Select Logic for glueless interface to ROM and SRAM – 12 KB Program SRAM • Processor Expert (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. • The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. • Five software interrupt levels • Access up to 4 MB of program memory or up to 12 MB data memory – 8 KB Data SRAM – 2 KB Boot ROM 56852 PERIPHERAL CIRCUIT FEATURES • General Purpose 16-bit Quad Timer with two external pins* • One Serial Communication Interface (SCI)* • One Serial Port Interface (SPI) or one Improved Synchronous Serial Interface (ISSI) module* • Interrupt Controller • JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging • 81-pin MAPBGA package • Up to 11 GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O • Computer Operating Properly (COP)/Watchdog Timer ORDERING INFORMATION PART SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER DSP56852 DSP56852 1.8V, 3.3V 1.8V, 3.3V MAP Ball Grid Array (MBGA) MAP Ball Grid Array (MBGA) 81 81 120 120 DSP56852VF120 SPAK56852VF120 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56852PB/D REV 3 For More Information On This Product, Go to: www.freescale.com