HD-LINX ™ GS1510 HDTV Serial Digital Deformatter PRELIMINARY DATA SHEET DESCRIPTION • SMPTE 292M compliant When interfaced to the Gennum GS1545 HDTV Equalizing Receiver or GS1540 Non-Equalizing Receiver, the GS1510 performs the final conversion to word aligned data. The device performs NRZI decoding and de-scrambling as per SMPTE 292M and word-aligns to the incoming data stream. Line based CRCs are calculated on the incoming data stream and are compared against the CRCs embedded within the data stream. • standards detection/indication for SMPTE 292M levels A/B,C,D/E,F,G/H,I,J/K,L/M • NRZI decoding and SMPTE descrambling with BYPASS option • line CRC calculation, comparison • selectable line based CRC re-Insertion • H, V, F timing reference signal (TRS) extraction • selectable flywheel for noise immune H, V, F extraction • selectable automatic switch line handling • selectable TRS and line number re-insertion • selectable active picture illegal code re-mapping HVF timing information is extracted from the data stream. A selectable internal HVF flywheel provides superior noise immunity against TRS signal errors. The device also detects and indicates the input video signal standard. The GS1510 can detect and re-map illegal code words contained within the active portion of the video signal. Prior to exiting the device, TRS, Line Numbers and CRCs based on internal calculations may be re-inserted into the data stream. • configurable FIFO LOAD pulse • 20 bit 3.3V CMOS input data bus • optimized input interface to GS1545 or GS1540 • single +3.3V power supply ORDERING INFORMATION • 5V tolerant I/O PART NUMBER PACKAGE TEMPERATURE GS1510-CQR 128 pin MQFP 0°C to 70°C APPLICATIONS SMPTE 292M Serial Digital Interfaces. WB_NI BP_DSC BP_FR TRS_Y/C FW_EN/DIS FAST_LOCK 2 F_E/S RESET 2 MUTE CODE PROTECT 3 TRS_INS LN_INS CRC_INS 3 DATA_IN DATA_OUT [19:10] TRS DETECTION CRC CALCULATION [19:0] INPUT BUFFER DESCRAMBLE FRAME FLYWHEEL CRC COMPARISON STANDARD DETECTION ILLEGAL CODE REMAPPING TRS, LNUM, AND CRC INSERTION TRS EXTRACTION (LUMA) DATA_OUT [9:0] (CHROMA) PCLK_IN 3 [H:V:F] 3 FIFO_L LN_ERR SAV_ERR EAV_ERR 4 VD_STD [3:0] 2 OEN LINE_CRC_ERR [Y:C] BLOCK DIAGRAM Revision Date: November 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com Document No. 522 - 47 - 00 GS1510 FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage -0.5V to +4.6V Input Voltage Range (any input) -0.5V < VIN < 5.5V 0°C ≤ TA ≤ 70°C Operating Temperature Range GS1510 -40°C ≤ TS ≤ 125°C Storage Temperature Range Lead Temperature (soldering 10 seconds) 260°C DC ELECTRICAL CHARACTERISTICS VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.0 3.3 3.6 V - 402 480 mA Positive Supply Voltage VDD Supply Current ΙDD Input Logic LOW Voltage VIL ILEAKAGE < 10µA - - 0.8 V Input Logic HIGH Voltage VIH ILEAKAGE < 10µA 2.1 3.3 5.0 V Output Logic LOW Voltage VOL VDD = 3.0 to 3.6V, IOL= 4mA - 0.2 0.4 V Output Logic HIGH Voltage VOH VDD = 3.0 to 3.6V, IOH = -4mA 2.6 - - V ƒ = 74.25MHz, TA = 25°C NOTES AC ELECTRICAL CHARACTERISTICS VDD = 3.0 to 3.6V, TA = 0°C to 70°C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Clock Input Frequency FHSCI - 74.25 80 MHz Input Data Setup Time tSU 2.5 - - ns 50% levels Input Data Hold Time tIH 1.5 - - ns 50% levels 40 - 60 % Input Clock Duty Cycle Output Data Hold Time tOH With 15pF load 2.0 - - ns Output Enable Time tOEN With 15pF load - - 8 ns Output Disable Time tODIS With 15pF load - - 9 ns tOD With 15pF load - - 10 ns tROD/tFOD With 15pF load - - 2.5 ns Output Data Delay Time Output Data Rise/Fall Time Also supports 74.25/1.001MHz 20% to 80% levels 2 GENNUM CORPORATION 522 - 47 - 00 GENNUM CORPORATION VDD GND VDD GND DATA_IN[9] DATA_IN[8] DATA_IN[7] DATA_IN[6] DATA_IN[5] DATA_IN[4] DATA_IN[3] DATA_IN[2] DATA_IN[1] DATA_IN[0] VDD GND DATA_IN[13] DATA_IN[12] DATA_IN[11] DATA_IN[10] 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 LN_ERR 65 38 VDD SAV_ERR 66 37 GND EAV_ERR 67 36 OEN VDD 68 35 TN GND 69 34 FIFO_L TEST 70 33 LINE_CRC_ERR_Y NC 71 32 LINE_CRC_ERR_C NC 72 31 VD_STD[0] NC 73 30 VD_STD[1] NC 74 29 VD_STD[2] NC 75 28 VD_STD[3] NC 76 27 NC NC 77 26 NC VDD 78 25 VDD GND 79 24 GND NC 80 23 F VDD 81 22 V GND 82 21 H NC 83 20 VDD NC 84 19 GND NC 85 18 RESET NC 86 17 FAST_LOCK NC 87 16 CRC_INS NC 88 15 LN_INS NC 89 14 GND VDD 90 13 TRS_INS GND 91 12 TRS_Y/C VDD 92 11 WB_NI VDD 93 10 BP_DSC GND 94 9 BP_FR GND 95 8 CODE_PROTECT VDD 96 7 FW_EN/DIS VDD 97 6 MUTE VDD 98 5 F_E/S VDD 99 4 GND VDD 100 3 VDD VDD 101 2 GND GND 102 1 PCLK_IN GS1510 TOP VIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GS1510 DATA_IN[19] DATA_IN[18] DATA_IN[17] DATA_IN[16] DATA_IN[15] DATA_IN[14] VDD GND DATA_OUT[6] DATA_OUT[5] DATA_OUT[4] DATA_OUT[3] DATA_OUT[2] DATA_OUT[1] DATA_OUT[0] VDD GND DATA_OUT[8] DATA_OUT[7] VDD GND DATA_OUT[14] DATA_OUT[13] DATA_OUT[12] DATA_OUT[11] DATA_OUT[10] DATA_OUT[9] DATA_OUT[19] DATA_OUT[18] DATA_OUT[17] DATA_OUT[16] DATA_OUT[15] PIN CONNECTIONS 3 522 - 47 - 00 PIN DESCRIPTIONS NUMBER 1 SYMBOL TIMING TYPE DESCRIPTION PCLK_IN Synchronous wrt PCLK_IN Input Input Clock. The device uses PCLK_IN for clocking the input data stream into DATA_IN[19:0]. This clock is generated by the GS1545 or GS1540 GND Gnd Ground power supply connections. 3, 20, 25, 38, 47, 51, 59, 68, 78, 81, 90, 93, 109, 115, 127 VDD Power Positive power supply connections. GS1510 2, 4, 14, 19, 24, 37, 46, 50, 58, 69, 79, 82, 91, 94, 110, 116, 128 5 F_E/S Nonsynchronous Input Control Signal Input. Used to control where the FIFO_L signal is generated. When F_E/S is high, the GS1510 generates FIFO_L signal at EAV. When F_E/S is low, the GS1510 generates FIFO_L signal at SAV. See Fig. 4 for timing information. 6 MUTE Synchronous wrt PCLK_IN Input Control Signal Input. Used to enable or disable blanking of the LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT[9:0]). When MUTE is low, the device sets the accompanying LUMA and CHROMA data to their appropriate blanking levels. When MUTE is high, the LUMA and CHROMA data streams pass through this stage of the device unaltered. 7 FW_EN/DIS Nonsynchronous Input Control Signal Input. Used to enable or disable the internal flywheel. When FW_EN/DIS is high, the internal flywheel is enabled. When FW_EN/DIS is low, the internal fly-wheel is disabled. 8 CODE_PROTECT Nonsynchronous Input Control Signal Input. Used to enable or disable re-mapping of out-of-range words contained in the active portion of the video signal. When this signal is high, the device re-maps out-ofrange words contained within the active portion of the video signal into CCIR-601 compliant words. Values between 000-003 are re-mapped to 004. Values between 3FC and 3FF are re-mapped to 3FB. When this signal is low, out-of-range words in the active video region pass through the device unaltered. 9 BP_FR Nonsynchronous Input Control Signal Input. Used to enable or disable word boundary framing. When BP_FR is low internal framing is enabled. When BP_FR is high internal framing is bypassed. 10 BP_DSC Nonsynchronous Input Control Signal Input. Used to enable or disable the SMPTE 292M descrambler. When BP_DSC is low, the internal SMPTE 292M descrambler is enabled. When BP_DSC is high, the internal SMPTE 292M de-scrambler is bypassed. 11 WB_NI Nonsynchronous Input Control Signal Input. Used to enable or disable noise immune operation of the word boundary framer. When WB_NI is high, noise-immune word boundary alignment is enabled. The device switches to a new word boundary only when it has detected two consecutive identical new TRS positions. When WB_NI is low, the device re-aligns the word boundary position at every instance of a TRS. 12 TRS_Y/C Nonsynchronous Input Control Signal Input. Used to control whether LUMA or CHROMA TRS IDs are detected and used. When TRS_Y/C is high, the device detects and uses TRS signals embedded in the LUMA channel. When TRS_Y/C is low, the device detects and uses TRS signals embedded in the CHROMA channel. 4 GENNUM CORPORATION 522 - 47 - 00 PIN DESCRIPTIONS NUMBER TIMING TYPE DESCRIPTION 13 TRS_INS Nonsynchronous Input Control Signal Input. Used to enable or disable re-insertion of the TRS into the data stream. When TRS_INS is high, the device re-inserts TRS into the incoming data stream based on the internal calculation. The original TRS packets are set to the blanking levels. If the flywheel is enabled, TRS calculated by the flywheel is used for insertion. When TRS_INS is low, the device will not re-insert TRS even if errors in TRS signals are detected. 15 LN_INS Nonsynchronous Input Control Signal Input. Used to enable or disable re-insertion of the line number into the data stream. When LN_INS is high, the device re-inserts the line number into the incoming data stream based on the internal calculation. The original line number packets are set to the blanking levels. If the flywheel is enabled, the line number calculated by the flywheel is used for insertion. When LN_INS is low, the device will not re-insert the line number. 16 CRC_INS Nonsynchronous Input Control Signal Input. Used to enable or disable re-insertion of the CRC into the data stream. When CRC_INS is high, the device is enabled to re-insert line CRCs based on the internal calculation. When CRC_INS is low, the device will not re-insert the CRCs. 17 FAST_LOCK Synchronous wrt PCLK_IN Input Control Signal Input. Used to control the flywheel synchronization when a switch line occurs. When a low to high transition occurs on the FAST_LOCK signal, the internal flywheel will immediately re-synchronize to the next valid EAV or SAV TRS in the incoming data stream. See Fig. 5 for timing information. 18 RESET Nonsynchronous Input Control Signal Input. Used to reset the system state registers to their default 720p parameters. When RESET is high, the fly wheel, TRS Detection, and ANC Detection operate normally. When RESET is low, the flywheel, TRS Detection, and ANC Detection are reset to the 720p parameters after a rising edge on PCLK_IN. The read and write counters are not affected. 21 H Synchronous wrt PCLK_IN Output Control Signal Input. This signal indicates the Horizontal blanking period of the video signal. Refer to Fig. 2 for timing information of H relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. 22 V Synchronous wrt PCLK_IN Output Control Signal Input. This signal indicates the Vertical blanking period of the video signal. Refer to Fig. 2 for timing information of V relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. 23 F Synchronous wrt PCLK_IN Output Control Signal Input. This signal indicates the ODD/EVEN field of the video signal. Refer to Fig. 2 for timing information of F relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. When locked and the input signal is of a progressive scan nature, F stays low at all times. NC N/A N/A VD_STD[3:0] Synchronous wrt PCLK_IN Output 26,27,71-77,80, No Connect. Do not connect these pins. 83-89 28, 29, 30, 31 Control Signal Output. VD_STD[3:0] indicates which input video standard the device has detected. The GS1510 will indicate all of the formats in SMPTE292M (see Table 1) plus it will indicate an unknown interlace or progressive scan format. 5 GENNUM CORPORATION 522 - 47 - 00 GS1510 SYMBOL PIN DESCRIPTIONS NUMBER TIMING TYPE DESCRIPTION 32 LINE_CRC_ERR_C Synchronous wrt PCLK_IN Output Status Signal Output. Indicates a difference in the calculated versus embedded CRC in the CHROMA channel. When LINE_CRC_ERR_C is high, it indicates that the GS1510 has detected a difference between the line based CRCs it calculates for the CHROMA channel and the line based CRCs embedded within the CHROMA channel. When LINE_CRC_ERR_C is low, the embedded and calculated CRCs match. Refer to Fig. 6 for timing information of LINE_CRC_ERR_C. 33 LINE_CRC_ERR_Y Synchronous wrt PCLK_IN Output Status Signal Output. Indicates a difference in the calculated versus embedded CRC in the LUMA channel. When LINE_CRC_ERR_Y is high, it indicates that the GS1510 has detected a difference between the line based CRCs it calculates for the LUMA channel and the line based CRCs embedded within the LUMA channel. When LINE_CRC_ERR_Y is low, the embedded and calculated CRCs match. Refer to Fig. 6 for timing information of LINE_CRC_ERR_Y. 34 FIFO_L Synchronous wrt PCLK_IN Output Status Signal Output. Used to control an external FIFO(s). FIFO_L is normally high, but is set low for the EAV or SAV word depending on the state of F_E/S. Refer to Fig. 4 for timing information of FIFO_L relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT[9:0]). 35 TN 36 OEN DATA_OUT[9:0] 39, 40, 41, 42, 43, 44, 45, 48, 49, 52 53, 54, 55, 56, 57, 60, 61, 62, 63, 64 (CHROMA channel) DATA_OUT[19:10] (LUMA channel) TEST Test Pin. Used for test purposes only. This pin must be connected to VDD for normal operation Nonsynchronous Input Control Signal Input. Used to enable the DATA_OUT[19:0] output bus or set it to a high Z state. When OEN is low, the LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) busses are enabled. When OEN is high, these busses are in a high Z state. Synchronous wrt PCLK_IN Output CHROMA Output Data Bus. DATA_OUT [9] is CHROMA_OUT[9] which is the MSB of the CHROMA output signal (pin 52). DATA_OUT [0] is CHROMA_OUT[0] which is the LSB of the CHROMA output signal (pin 39). Synchronous wrt PCLK_IN Output LUMA Output Data Bus. DATA_OUT [19] is LUMA_OUT[9] which is the MSB of the LUMA output signal (pin 64). DATA_OUT [10] is LUMA_OUT[0] which is the LSB of the LUMA output signal (pin 53). 65 LN_ERR Synchronous wrt PCLK_IN Output Status Signal Output. Used to indicate a Line Number error or a mismatch between the embedded line number and the flywheel line number when the flywheel is enabled. When LN_ERR is high, a line number error is detected or the internal flywheel indicates mismatching line numbers. Refer to Fig. 3 for timing information of LN_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) Since LN_ERR depends on the sequence of line numbers, a line number error will actually cause LN_ERR to go high for two lines. 66 SAV_ERR Synchronous wrt PCLK_IN Output Status Signal Output. Indicates a TRS error or a mismatch between the embedded TRS and the flywheel TRS when the flywheel is enabled. This signal is set high when an error in the SAV TRS is detected or when the internal flywheel indicates there is a mismatching SAV TRS. Refer to Fig. 3 for timing information of SAV_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]). 6 GENNUM CORPORATION 522 - 47 - 00 GS1510 SYMBOL PIN DESCRIPTIONS NUMBER TIMING TYPE DESCRIPTION 67 EAV_ERR Synchronous wrt PCLK_IN Output Status signal output. Indicates a TRS error or a mismatch between the embedded TRS and the flywheel TRS when the flywheel is enabled. This signal is set high when an error in the EAV TRS is detected or when the internal flywheel indicates there is a mismatching EAV TRS. Refer to Fig. 3 for timing information of EAV_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]). 70 TEST Test pin. Used for test purposes only. This pin must be connected to GND for normal operation. VDD N/A N/A Must be connected to VDD for normal operation. GND N/A N/A Must be connected to GND for normal operation. DATA_IN [19:0] Synchronous wrt PCLK_IN Input 92, 96, 97, 98, 99,100,101 95, 102 103,104,105, 106, 107, 108, 111, 112, 113, 114, 117, 118, 119,120, 121, 122, 123, 124, 125, 126 TEST Input data bus. DATA_IN [19] is the MSB of the signal (pin 103). DATA_IN [0] is the LSB of the signal (pin 126). This data is typically scrambled and not word aligned. DETAILED DESCRIPTION Progressive Scan Standards Indication (VD_STD[3]=0) 1. DATA INPUT AND OUTPUTS Data enters and exits the device on the rising edge of PCLK_IN as shown in Figures 1 and 2. This data can be scrambled or unscrambled and framed or unframed. 2. DESCRAMBLER AND FRAMER Both the descrambler and framer can be enabled or disabled independently of each other to allow the input to remain scrambled or unscrambled. If the data is unscrambled, it can be word aligned (framed) or passed through unaltered. VD_STD[3:0] DESCRIPTION 0000 720p (60 & 60/1.001Hz → L/M) [SMPTE296M] 0001 Reserved 0010 1080p (30 & 30/1.001Hz → G/H) [SMPTE274M] 0011 Reserved 0100 1080p (25Hz → I) [SMPTE274M] 0101 Reserved 0110 1080p (24 & 24/1.001Hz → J/K) [SMPTE274M] 0111 Unknown Progressive with F = 0 always. 3. STANDARDS INDICATION VD_STD[3:0] indicates the standard that the device has detected. The states of VD_STD[3:0] are shown in the following standards indication tables. Note the following in the above tables: SMPTE260M is 1125 lines/frame Interlaced Standards Indication (VD_STD[3]=1) SMPTE274M is 1125 lines/frame VD_STD[3:0] DESCRIPTION 1000 1080i (30 & 30/1.001Hz → D/E) [SMPTE274M] 1001 Reserved 1010 1080i (25Hz → F) [SMPTE274M] 1011 Reserved 1100 1080i (25Hz → C) [SMPTE295M] 1101 Reserved 1110 1035i (30 & 30/1.001Hz → A/B) [SMPTE260M] 1111 Unknown Interlaced with F switching 0/1 SMPTE295M is 1250 lines/frame SMPTE296M is 750 lines/frame See Table 1 for more specific details on the source format parameters. 7 GENNUM CORPORATION 522 - 47 - 00 GS1510 SYMBOL 5. AUTOMATIC SWITCH LINE LOCK HANDLING The flywheel logic will check the incoming video data for valid video lines. If the incoming data represents a valid line, the flywheel remains in sync with the incoming data. If the incoming data represents an invalid line, the flywheel will use the stored timing information for the past valid line to generate the output HVF timing signals until three (3) consecutive lines having identical timing are detected. In this case, the new timing information will be saved and the flywheel operation is updated to this new timing. Mismatches between the HVF information decoded from the data stream and that indicated by the flywheel will trigger the EAV_ERR and SAV_ERR signals as shown in Figure 3. HVF output timing is shown in Figure 2. The automatic switch line lock is based on the assumption that the switching of video sources will only cause the H signal to be out of alignment whereas V and F signals remain in sync; i.e. switching between video sources of the same format. Therefore, when in the automatic switch line lock mode (FAST_LOCK transitions for low to high), the flywheel positive H signal transition will align with the detected positive H signal transition. Timing for the FAST_LOCK signal is shown in Figure 5. TABLE 1: Source Format Parameters Reference SMPTE Standard 260m 260m 295m 274m 274m 274m 274m 274m 274m 274m 274m 296m 296m A B C D E F G H I J K L M Lines/Frame 1125 1125 1250 1125 1125 1125 1125 1125 1125 1125 1125 750 750 Words/Active Line 1920 1920 1920 1920 1920 1920 1920 1920 1920 1920 1920 1280 1280 Total Active Lines 1035 1035 1080 1080 1080 1080 1080 1080 1080 1080 1080 720 720 Words/Total Line (each channel Y, Cb/Cr) 2200 2200 2376 2200 2200 2640 2200 2200 2640 2750 2750 1650 1650 Frame Rate (Hz) 30 30/M 25 30 30/M 25 30 30/M 25 24 24/M 60 60/M Fields /Frame 2 2 2 2 2 2 1 1 1 1 1 1 1 Data Rate Divisor 1 M 1 1 M 1 1 M 1 1 M 1 M Format ID (each channel Y, Cb/Cr) NOTE: M=1.001 in the above table. 8 GENNUM CORPORATION 522 - 47 - 00 GS1510 4. FLY WHEEL OPERATION PCLK_IN DATA_IN DATA DATA DATA tSU tIH DATA DATA DATA GS1510 DATA_OUT DATA tOH tOD Fig. 1 Synchronous I/O Timing PCLK_IN DATA_OUT[19:10] (LUMA) 3FF 000 000 XYZ (EAV ID) YLN0 3FF 000 000 XYZ (SAV ID) DATA_OUT[9:0] (CHROMA) 3FF 000 000 XYZ (EAV ID) CLN0 3FF 000 000 XYZ (SAV ID) H V F Fig. 2 HVF Timing PCLK_IN DATA_OUT (Luma or Chroma depending on the state of TRS_Y/C) Correct/Incorrect Line Number Correct/Incorrect ID 3FF 000 000 XYZ (EAV-ID) LN0 LN1 Correct/Incorrect ID 3FF 000 000 XYZ (SAV-ID) EAV_ERR SAV_ERR LN_ERR Fig. 3 EAV_ERR, SAV_ERR and LN_ERR Timing PCLK_IN DATA_OUT[19:10] (LUMA) 3FF 000 000 XYZ (EAV-ID) 3FF 000 000 XYZ (SAV-ID) DATA_OUT[9:0] (CHROMA) 3FF 000 000 XYZ (EAV-ID) 3FF 000 000 XYZ (SAV-ID) FIFO_L (F_E/S=1) FIFO_L (F_E/S=0) Fig. 4 FIFO_L Timing 9 GENNUM CORPORATION 522 - 47 - 00 DATA_IN (Luma or Chroma depending on the state of TRS_Y/C) EAV ANC SPACE SAV ACTIVE PICTURE EAV ANC SPACE Switch Line SAV ACTIVE PICTURE Switch Line + 1 FAST_LOCK GS1510 A Low to High Transition in the Active Picture of a Line Forces the GS1500 to Resynchronize to the next valid TRS ID Fig. 5 FAST_LOCK Timing PCLK_IN DATA_OUT[19:10] (LUMA) 3FF 000 000 XYZ (EAV-ID) YLN0 YLN1 YCCR0 YCCR1 3FF 000 000 XYZ (EAV-ID) CLN0 CLN1 CCCR0 CCCR1 LINE_CRC_ERR_Y DATA_OUT[9:0] (CHROMA) LINE_CRC_ERR_C Fig. 6 Luma and Chroma LINE_CRC_ERR Timing 10 GENNUM CORPORATION 522 - 47 - 00 PACKAGE DIMENSIONS 23.20 ±0.25 20.0 ±0.10 18.50 REF GS1510 17.20 ±0.25 12.50 REF 14.0 ±0.10 3.00 MAX 0.50 BSC 0.27 ±0.08 2.80 ±0.25 12 TYP 0.75 MIN 0 -7 0.30 MAX RADIUS 0-7 0.13 MIN. RADIUS 0.88 ±0.15 128 pin MQFP 1.6 REF All dimensions in millimetres CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION REVISION NOTES: Updated Absolute Maximum Ratings; Updated AC and DC Electrical Characteristics Tables; Updated Figure 4. DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change. GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 For latest product information, visit www.gennum.com GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright August 1999 Gennum Corporation. All rights reserved. Printed in Canada. 11 522 - 47 - 00