HD74AC373/HD74ACT373 Octal Transparent Latch with 3-State Output REJ03D0273–0200Z (Previous ADE-205-394 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High, the bus output is in the high impedance state. Features • Eight Latches in a Single Package • 3-State Outputs for Bus Interfacing • Outputs Source/Sink 24 mA • HD74AC373 has TTL-Compatible Inputs • Ordering Information: Ex. HD74AC373 Part Name HD74AC373P Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) DIP-20 pin DP-20N, -20NEV P HD74AC373FPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel) HD74AC373RPEL SOP-20 pin (JEDEC) FP-20DBV RP EL (1,000 pcs/reel) HD74AC373TELL TSSOP-20 pin T ELL (2,000 pcs/reel) TTP-20DAV — Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Rev.2.00, Jul.16.2004, page 1 of 9 HD74AC373/HD74ACT373 Pin Arrangement OE 1 20 VCC O0 2 19 O7 D0 3 18 D7 D1 4 17 D6 O1 5 16 O6 O2 6 15 O5 D2 7 14 D5 D3 8 13 D4 O3 9 12 O4 Gnd 10 11 LE (Top view) Logic Symbol D0 D 1 D 2 D 3 D4 D5 D 6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 Pin Names D0 – D 7 LE OE O0 – O 7 Data Inputs Latch Enable Input Output Enable Input 3-State Latch Outputs Rev.2.00, Jul.16.2004, page 2 of 9 HD74AC373/HD74ACT373 Truth Table Inputs Outputs OE LE On Dn H X X Z L L H H L H L H L L X O0 H L Z X O0 : : : : : High Voltage Level Low Voltage Level High Impedance Immaterial Previous O0 before Low-to-High Transition of Clock Functional Description The HD74AC373/HD74ACT373 contains eight D-type latches with 3-state standard outputs. When the Latch Enable (LE) input is High, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is Low, the latches store the information that was present on the D inputs setup time proceding the High-to-Low transition of LE. The 3-state standard outputs are controlled by the Output Enable (OE) input. When OE is Low, the standard outputs are in the 2-state mode. When OE is High, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram D1 D0 D D2 D G O D3 D G O D4 D G O D5 D G O D6 D G O D7 D G O D G O G O LE OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Absolute Maximum Ratings Item Supply voltage DC input diode current Symbol Ratings Unit Condition VCC IIK –0.5 to 7 –20 V mA VI mA V VI = Vcc+0.5V DC input voltage 20 –0.5 to Vcc+0.5 DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C Rev.2.00, Jul.16.2004, page 3 of 9 VI = –0.5V HD74AC373/HD74ACT373 Recommended Operating Conditions: HD74AC373 Item Symbol Ratings Unit Supply voltage Input and Output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V DC Characteristics: HD74AC373 Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND 3 State current IOZ 5.5 — — ±0.5 — ±5.0 µA IOLD 5.5 — — — 86 — mA VIN(OE) = VIL, VIH VIN = VCC or GND VOUT = VCC or GND VOLD = 1.1 V IOHD ICC 5.5 5.5 — — — — — 8.0 –75 — — 80 mA µA VOHD = 3.85 V VIN = VCC or ground Dynamic output current* Quiescent supply current IOL = 24 mA *Maximum test duration 2.0 ms, one output loaded at a time. Recommended Operating Conditions: HD74ACT373 Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Ta tr, tf –40 to +85 8 °C ns/V Rev.2.00, Jul.16.2004, page 4 of 9 Condition VCC = 4.5V VCC = 5.5V HD74AC373/HD74ACT373 DC Characteristics: HD74ACT373 Item Input voltage Output voltage Symbol Ta = 25°°C VIH 4.5 min. 2.0 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.0 — VIL 5.5 4.5 2.0 — 1.5 1.5 — 0.8 2.0 — — 0.8 VOH 5.5 4.5 — 4.4 1.5 4.49 0.8 — — 4.4 0.8 — 5.5 4.5 5.4 3.94 5.49 — — — 5.4 3.80 — — 5.5 4.5 4.94 — — 0.001 — 0.1 4.80 — — 0.1 5.5 4.5 — — 0.001 — 0.1 0.32 — — 0.1 0.37 — — — — 0.32 ±0.1 — — 0.37 ±1.0 VOL VCC (V) Unit V Condition VOUT = 0.1 V or VCC–0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL IOL = 24 mA Input current IIN 5.5 5.5 IOL = 24 mA µA VIN = VCC or GND 3 State current IOZ 5.5 — — ±0.5 — ±5.0 µA ICC/input current ICCT 5.5 — 0.6 — — 1.5 mA VIN = VIL, VIH VOUT = VCC or GND VIN = VCC–2.1 V Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics: HD74AC373 Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Unit Propagation delay Dn to On tPLH 3.3 5.0 1.0 1.0 10.0 7.0 13.5 9.5 1.0 1.0 15.0 10.5 ns Propagation delay Dn to On tPHL 3.3 5.0 1.0 1.0 9.5 7.0 13.0 9.5 1.0 1.0 14.5 10.5 ns Propagation delay LE to On tPLH 3.3 5.0 1.0 1.0 10.0 7.5 13.5 9.5 1.0 1.0 15.0 10.5 ns Propagation delay LE to On tPHL 3.3 5.0 1.0 1.0 9.5 7.0 12.5 9.5 1.0 1.0 14.0 10.5 ns Output enable time tZH 3.3 5.0 1.0 1.0 9.0 7.0 11.5 8.5 1.0 1.0 13.0 9.5 ns Output enable time tZL 3.3 5.0 1.0 1.0 8.5 6.5 11.5 8.5 1.0 1.0 13.0 9.5 ns Output disable time tHZ 3.3 5.0 1.0 1.0 10.0 8.0 12.5 11.0 1.0 1.0 14.5 12.5 ns Output disable time tLZ 3.3 5.0 1.0 1.0 8.0 6.5 11.5 8.5 1.0 1.0 12.5 10.0 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 5 of 9 HD74AC373/HD74ACT373 AC Characteristics: HD74AC373 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF tPLH VCC (V)*1 Min 5.0 1.0 Typ 8.5 Max 10.0 1.0 Max 11.5 ns Propagation delay Dn to On Propagation delay LE to On tPHL 5.0 1.0 8.0 10.0 1.0 11.5 ns tPLH 5.0 1.0 8.5 11.0 1.0 11.5 ns Propagation delay LE to On Output enable time tPHL 5.0 1.0 8.0 10.0 1.0 11.5 ns tZH 5.0 1.0 8.0 9.5 1.0 10.5 ns Output enable time Output disable time tZL tHZ 5.0 5.0 1.0 1.0 7.5 9.0 9.0 11.0 1.0 1.0 10.5 12.5 ns ns Output disable time tLZ 5.0 1.0 7.5 8.5 1.0 10.0 ns Item Propagation delay Dn to On Note: Symbol Min Unit 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74AC373 Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Dn to LE Hold time, HIGH or LOW Dn to LE LE pulse width, HIGH Note: Symbol VCC (V)*1 Typ tsu 3.3 3.5 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 6.0 Unit ns th 5.0 3.3 2.0 –3.0 4.0 0.0 4.5 0.0 ns tw 5.0 3.3 –1.5 4.0 0.0 5.5 0.0 6.0 ns 2.0 4.0 4.5 5.0 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74ACT373 Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Dn to LE Hold time, HIGH or LOW Dn to LE LE pulse width, HIGH Note: Symbol VCC (V)*1 Typ 5.0 3.0 tsu Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 7.0 8.0 ns Unit th 5.0 0.0 0.0 1.0 ns tw 5.0 2.0 7.0 8.0 ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 6 of 9 Symbol CIN CPD Typ 4.5 40.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC373/HD74ACT373 Package Dimensions As of January, 2003 Unit: mm 24.50 25.40 Max 6.30 11 1 7.00 Max 20 10 2.54 ± 0.25 0.51 Min 1.27 Max 0.48 ± 0.10 2.54 Min 5.08 Max 1.30 0.89 7.62 + 0.11 0.25 – 0.05 0˚ – 15˚ Package Code JEDEC JEITA Mass (reference value) DP-20N — Conforms 1.26 g Unit: mm 24.50 25.40 Max 1 7.00 Max 11 6.30 20 10 1.30 2.54 ± 0.25 *0.48 ± 0.08 0.51 Min 1.27 Max 2.54 Min 5.08 Max 0.89 7.62 *0.25 ± 0.06 0˚ – 15˚ *NI/Pd/AU Plating Rev.2.00, Jul.16.2004, page 7 of 9 Package Code JEDEC JEITA Mass (reference value) DP-20NEV — Conforms 1.26 g HD74AC373/HD74ACT373 As of January, 2003 Unit: mm 12.6 13 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0˚ – 8 ˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 20 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-20DAV — Conforms 0.31 g As of January, 2003 Unit: mm 12.8 13.2 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 ± 0.10 0.935 Max *0.25 ± 0.05 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0˚ – 8˚ 0.57 0.70 +– 0.30 0.15 0.12 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 8 of 9 Package Code JEDEC JEITA Mass (reference value) FP-20DBV Conforms — 0.52 g HD74AC373/HD74ACT373 As of January, 2003 Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.20 ± 0.05 1.0 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 9 of 9 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-20DAV — — 0.07 g Sales Strategic Planning Div. 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