HD74AC74 Dual D-Type Positive Edge-Triggered Flip-Flop REJ03D0277–0200Z (Previous ADE-205-361 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Features Asynchronous Inputs: Low input to SD (Set) sets Q to High level Low input to CD (Clear) sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC74P DIP-14 pin DP-14, -14AV P — HD74AC74FPEL SOP-14 pin (JEITA) FP-14DAV FP EL (2,000 pcs/reel) HD74AC74RPEL SOP-14 pin (JEDEC) FP-14DNV RP EL (2,500 pcs/reel) HD74AC74TELL TSSOP-14 pin TTP-14DV T ELL (2,000 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement CD1 1 D1 2 CP1 3 14 VCC CP1 D1 SD1 CD1 Q1 Q1 SD1 4 12 D2 11 CP2 Q1 5 D2 CP2 10 SD2 Q1 6 CD2 SD2 9 Q2 GND 7 Q2 Q2 (Top view) Rev.2.00, Jul.16.2004, page 1 of 7 13 CD2 8 Q2 HD74AC74 Logic Symbol D1 SD1 Q1 D2 CP1 SD2 Q2 CP2 CD1 Q1 CD2 Q2 Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q 2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs Truth Table (Each Half) Inputs SD L H L H H H H L X : : : : Q0 (Q0) : CD H L L H H H High Voltage Level Low Voltage Level Immaterial CP X X X L Outputs Q D X X X H L X H L H H L Q0 Q L H H L H Q0 Low-to-High Clock Transition Previous Q (Q) before Low-to-High Transition of Clock Logic Diagram SD D Q CP Q CD Please note that this diagram is provised only for the understanding of logic operations and should not be used to estimate propagation delays. Rev.2.00, Jul.16.2004, page 2 of 7 HD74AC74 Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK –0.5 to 7 –20 V mA VI 20 –0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C VI = –0.5V Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V DC Characteristics Item Input Voltage Symbol Unit Condition min. 2.1 typ. 1.5 max. — min. 2.1 max. — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V — 40 µA VIN = VCC or ground VOH VOL Input leakage current Dynamic output current* Ta = –40 to +85°°C 3.0 VIH VIL Output voltage Ta = 25°°C Vcc (V) Quiescent supply 5.5 — — 4.0 ICC current *Maximum test duration 2.0 ms, one output loaded at a time. Rev.2.00, Jul.16.2004, page 3 of 7 V VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA HD74AC74 AC Characteristics Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay fmax VCC (V)*1 Min 3.3 100 Typ 125 Max — 95 — MHz tPLH 5.0 3.3 140 1.0 160 8.0 — 12.0 125 1.0 — 13.0 ns 1.0 1.0 6.0 10.5 9.0 12.0 1.0 1.0 10.0 13.5 ns Symbol CDn or SDn to Qn or Qn Propagation delay Ta = –40°C to +85°C CL = 50 pF Min Max Unit tPHL 5.0 3.3 CDn or SDn to Qn or Qn Propagation delay tPLH 5.0 3.3 1.0 1.0 8.0 8.0 9.5 13.5 1.0 1.0 10.5 16.0 ns CPn to Qn or Qn Propagation delay tPHL 5.0 3.3 1.0 1.0 6.0 8.0 10.0 14.0 1.0 1.0 10.5 14.5 ns 5.0 1.0 6.0 10.0 1.0 10.5 CPn to Qn or Qn Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements Ta = +25°C CL = 50 pF Item Set-up time, HIGH or LOW Symbol VCC (V)*1 Typ tsu 3.3 1.5 Dn to CPn Hold time, HIGH or LOW th 5.0 3.3 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 4.0 4.5 ns 1.0 –2.0 3.0 0 3.0 0 ns tw 5.0 3.3 –1.5 3.0 0 5.5 0 7.0 ns trec 5.0 3.3 2.5 –2.5 4.5 0 5.0 0 ns 5.0 CDn or SDn to CP Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V –2.0 0 0 Dn to CPn CPn or CDn or SDn Pulse width Recovery time Unit Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 4 of 7 Symbol CIN CPD Typ 4.5 35.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC74 Package Dimensions As of January, 2003 Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 + 0.10 0.25 – 0.05 0˚ – 15˚ Package Code JEDEC JEITA Mass (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 *0.48 ± 0.08 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 *0.25 ± 0.06 0˚ – 15˚ *NI/Pd/AU Plating Rev.2.00, Jul.16.2004, page 5 of 7 Package Code JEDEC JEITA Mass (reference value) DP-14AV Conforms Conforms 0.97 g HD74AC74 As of January, 2003 Unit: mm 10.06 10.5 Max 8 5.5 14 1 1.42 Max *0.20 ± 0.05 2.20 Max 7 *0.40 ± 0.06 1.15 0˚ – 8 ˚ 0.10 ± 0.10 1.27 0.20 7.80 +– 0.30 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-14DAV — Conforms 0.23 g As of January, 2003 Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 *0.40 ± 0.06 0.11 0.14 +– 0.04 0˚ – 8˚ 1.27 0.67 0.60 +– 0.20 0.15 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 7 Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g HD74AC74 As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 1.0 *0.20 ± 0.05 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 7 of 7 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.83 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-14DV — — 0.05 g Sales Strategic Planning Div. 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