HI3197 Data Sheet October 1998 10-Bit, 125 MSPS D/A Converter • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits • Conversion Rate HI3197JCQ -20 to 75 125 MSPS (PECL) 100 MSPS (TTL) • Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL • Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ) • Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s • Clock, Reset Input Level: TTL and PECL Compatible 2:1 Multiplexed Input Function • 1/2 Frequency-Divided Clock Output Possible by the BuiltIn Clock Frequency Divider Circuit Ordering Information PART NUMBER 4356.1 Features The HI3197 is a high-speed D/A converter which can perform the multiplexed input of the two system 10-bit data. The maximum conversion rate achieves 125 MSPS. The multiplexed operation is possible by the 1/2 frequencydivided clock or by halving the frequency of the clock with the clock frequency divider circuit having the reset pin in the IC. The data input is TTL; the clock input pin and reset input pin can select either TTL or PECL according to the application. TEMP. RANGE (oC) File Number • Voltage Output (50Ω Load Drive Possible) PACKAGE PKG. NO. 48 Ld MQFP/ PQFP Q48.7x7-S • Single Power Supply or ±Dual Power Supplies • Polarity Switching Function of Reset Signal Applications • LCD • DDS • HDTV • Communications (QPSK, QAM) Pinout DGND2 C3 C2 C1 AVCC0 DVCC2 AOUTN VREF AGND2 AOUTP PS 41 20 DVCC1 42 43 19 CLKN/E CLKP/E CLK/T 18 DIV2OUT 44 17 45 16 DIV2IN DB0 (LSB) 46 15 DB1 47 48 14 DB2 13 9 10 11 12 DB3 DA7 DA6 1 2 3 DA3 DA2 (MSB) DA9 DA8 DA4 DGND1 DA5 NC 4 5 6 7 8 DB4 21 DB5 RESET/T 40 DB7 DB6 RESETP/E 22 (MSB) DB9 DB8 23 VOCLP DA1 RESETN/E 38 39 37 (LSB) DA0 36 35 34 33 32 31 30 29 28 27 26 25 24 AGND2 R POLARITY INV 1 VSET AVCC2 HI3197 (MQFP) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI3197 Block Diagram VREF 34 VSET BGR 35 CURRENT CONT. + - 36 AVCC2 30 AVCC0 32 AOUTP 31 AOUTN 37 AGND2 33 AGND2 18 DIV2OUT AGND2 DVCC1 42 DVCC2 29 D/A 10-BIT DA0 TO DA9 1 TO 6 45 TO 48 10-BIT RO = 50Ω INPUT LATCH 10-BIT LATCH MUX 10-BIT DB0 TO DB9 7 TO 16 10-BIT 10-BIT INPUT LATCH AGND2 D DIV2IN 17 Q Q CLK/T 19 CLKP/E 20 CLKN/E 21 RESET/T 22 RESETP/E 23 RESETN/E 24 R POLARITY 39 2 44 25 26 27 28 41 40 38 DGND1 DGND2 C1 C2 C3 PS INV VOCLP HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO SYMBOL I/O 1 to 6 45 to 48 DA0 to DA9 I 7 to 16 DB0 to DA9 TYPICAL VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION TTL Side A Data Input. DVCC1 I TTL Side B Data Input. 1 6 TO 45 TO 48 VREF 7 TO 16 DGND1 17 DIV2IN I TTL 1/ Frequency-Divided Clock Input. 2 Use this pin for MUX.1A or MUX.2 mode. Leave open for other modes. DVCC1 17 VREF DGND1 18 DIV2OUT O TTL DVCC1 1/ Frequency-Divided Clock Out2 put. The signal with the 1/2 fre- quency divided clock (DIV2OUT) is output for MUX.1A mode. Leave open for other modes. 18 DGND1 19 CLK/T I TTL Clock Input. Use this pin when the clock is input in the TTL level. At this time, leave Pins 20 and 21 open. DVCC1 19 VREF DGND1 20 CLKP/E I PECL 21 CLKN/E I PECL DVCC1 20 21 DGND1 3 Clock Input. Use this pin when the clock is input in PECL level. At this time, leave Pin 19 open. CLKP/E Complementary Input. When left open, this pin goes to the threshold potential. Operation is possible only with CLKP/E, but complementary input is recommended to attain fast and stable operation. HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO SYMBOL I/O 22 RESET/T I TYPICAL VOLTAGE LEVEL TTL (Continued) EQUIVALENT CIRCUIT DESCRIPTION DVCC1 VREF 22 DGND1 23 RESETP/E I PECL 24 RESETN/E I PECL DVCC1 23 24 Reset signal input. When the multiple HI3197 are operated at a time for MUX.1A or MUX.1B mode, the start timing of the internal 1/2 frequency divider circuits should be matched. At this time, the reset signal is used; when the reset signal is the TTL level, Pin 22 is used and Pins 23 and 24 are left open. When the reset signal is the PECL level, Pins 23 and 24 are used and Pin 22 is left open. For the PECL level, operation is possible only with RESETP/E as with the case for the clock. The reset signal polarity can be set by Pin 39 (RPOLARITY). Leave the reset pin open when the other modes are used. DGND1 25 DGND2 Single Power Supply: GND Dual Power Supplies: -5V 26 C1 I TTL 27 C2 I TTL 28 C3 I TTL Digital Power Supply. Function setting. DVCC1 26 VREF 27 28 DGND1 29 DVCC2 30 AVCC0 31 OUTN Single Power Supply: +5V Dual Power Supplies: GND Digital Power Supply. Analog Output Power Supply. O AVCC0 AVCC0 - VFS RO RO 31 32 32 AOUTP O AVCC0 - VFS D/A Negative Output. The inversion of the D/A positive output pin is output. Terminate the inversion without pin with 50Ω when the inversion output is not used and the positive output is terminated with 50Ω. D/A positive output. AGND2 33 AGND2 Single Power Supply: GND Dual Power Supplies: -5V 4 Analog Ground. HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO SYMBOL I/O 34 VREF O TYPICAL VOLTAGE LEVEL (Continued) EQUIVALENT CIRCUIT AGND +1.2V DESCRIPTION Analog Reference Voltage Output. AVCC2 34 AGND2 35 VSET I AGND2 + 0.7V to AGND2 + 1.03V Full scale adjustment. AVCC2 35 36 AVCC2 Single Power Supply: +5V Dual Power Supplies: GND Analog Power Supply. 37 AGND2 Single Power Supply: GND Dual Power Supplies: -5V Analog Power Supply 38 VOCLP I Clamp Voltage DVCC1 38 TTL Output High Level Clamp. The TTL level signal is output from the DIV2OUT pin for MUX.1A mode. The TTL high level voltage is clamped to the value approximately equivalent to the voltage supplied to this pin. Leave the VOCLP pin open for other modes. DGND1 39 P Polarity I TTL Reset signal polarity switching. At high level, the reset polarity is active high; at low level, active low. DVCC1 39 DGND1 5 VREF HI3197 Pin Descriptions and I/O Pin Equivalent Circuits PIN NO SYMBOL I/O 40 INV I TYPICAL VOLTAGE LEVEL (Continued) EQUIVALENT CIRCUIT DESCRIPTION TTL Analog Output polarity inversion. The analog output is inverted at low level. DVCC1 40 VREF DGND1 41 PS I TTL DVCC1 Power saving. Power saving at low level. Normally pull up the PS pin to high level as this pin is open low. 41 DGND1 42 DVCC1 43 NC 44 DGND1 5V Digital Power Supply. No connection. 0V 6 Digital Ground. HI3197 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVCC0 , AVCC2 , DVCC2) . . . . . . . . . . -0.5 to +7.0V AGND2, DGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0 to +0.5V DVCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V AVCC2 - AGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V AVCC0 - AGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V DVCC2 - DGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V Input Voltage VSET, . . . . . . . . . . . . . . . . . . . . . . . . AGND2 -05 to AVCC2 + 0.5V TTL Pin . . . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 0.5V PECL Pin, . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 0.5V PS. . . . . . . . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 0.5V (Others), VOCLP . . . . . . . . . . . . . . . . . DGND1 -0.5 to DVCC1 + 5V Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . .1.4W (When mounted on a glass fabric base epoxy board with 76mm x 114mm, 1.6mm thick) Maximum Junction Temperature (Hermetic Package or Die) . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Recommended Operating Conditions WITH A SINGLE POWER SUPPLY Supply Voltage AVCC0 , AVCC2 . . . . . . . . . . . . . . . . . . . . . AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1. . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . MIN TYP MAX +4.75 -0.05 +4.75 -0.05 -4.75 -0.05 +5.0 0 +5.0 0 +5.0 0 +5.25V +0.05V +5.25V +0.05V +5.25V +0.05V Recommended Operating Conditions WITH DUAL POWER SUPPLIES Supply Voltage AVCC0 , AVCC2 . . . . . . . . . . . . . . . . . . . . . AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1. . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND2. . . . . . . . . . . . . . . . . . . . . . . . . . . MIN TYP MAX -0.05 -5.50 4.75 -0.05 -0.05 -5.50 0 -5.0 5.0 0 0 -5.0 +0.05V -4.75V +5.25V +0.05V +0.05V -4.75V (Applying to Single and Dual Power Supplies) MIN TYP MAX AGND2 + 1.03V Analog Input Voltage, VSET . . .AGND2 + 0.7 Digital Input Voltage PECL, VIH . . . . . . . . . . . . . . .DGND1 + 2.6 DVCC1 PECL, VIL . . . . . . . . . . . . . . . VIH - 0.8 VIH - 0.4V TTL, VIH . . . . . . . . . . . . . . . . .DGND1 + 2.0 TTL, VIL . . . . . . . . . . . . . . . . . DGND1 + 0.8V PS, VIH. . . . . . . . . . . . . . . . . .DGND1 + 2.0 PS, VIL . . . . . . . . . . . . . . . . . . DGND1 + 0.8V Other, VOCLP . . . . . . . . . . . .DGND1 + 2.7 DVCC1 Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4ns (Min) Load Resistance, RL . . . . . . . . . . . . . . . . . . Analog Output Full Scale Voltage RL ≥ 10kΩ, VFS . . . . . . . . . . . . . . . . . . . . . RL = 50Ω, VFS . . . . . . . . . . . . . . . . . . . . . . MIN 50 TYP 50 MAX ≥10kΩ 1.5 0.75 2.0 1.0 2.2V 1.2V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. VSUPPLY = ±5V, AV = +1, RL = 100Ω Electrical Specifications PARAMETER SYMBOL Resolution TEST CONDITIONS n Maximum Conversion Rate MIN TYP MAX UNITS - 10 - Bit fCECL PECL Operation - - 125 MSPS fCTTL TTL Operation - - 100 MSPS VFS = 1V - - ±1.2 LSB - - -0.85 to 0.5 LSB Integral Linearity Error INL Differential Linearity Error DNL DNL AOUTP Transitions from 0000111111 - 0001000000 - - -1.2 to 0.5 LSB DNL AOUTN Transitions from 1111000000 - 1110111111 - - -1.2 to 0.5 LSB Output Full-Scale Voltage VFS RL = 50Ω 0.75 1 1.05 V RL ≥ 10kΩ 1.5 2.0 2.2 V Compliance Voltage VOC(MIN): (AVCC0-VFS - DVCC2) ≥ -2.V, VOC(MAX): (AVCC0-VOF - DVCC2) ≥ 1.5 VOC Measured to DVCC2 -2.1 - 1.5 V ANALOG OUTPUT 7 HI3197 VSUPPLY = ±5V, AV = +1, RL = 100Ω (Continued) Electrical Specifications PARAMETER SYMBOL Output Zero Offset Voltage VOF TEST CONDITIONS MIN TYP MAX UNITS RL ≥ 10kΩ, VSET = AGND2 + 0.9375V 0 - 20 mV RL = 50Ω, VSET = AGND2 + 0.9375V 0 - 10 mV Output Resistance RO - 50 - Ω Output Capacitance CO - 10 - pF VSET = AGND2 + 0.9375V -4 - 4 % of FS VFS = 1V at 25oC - - 60 ppm/ oC 0.85 - 1.05 ns Absolute Amplitude Error EG Absolute Amplitude Error Temperature Characteristics TCG Analog Output Rise Time tr Analog Output Fall Time tf RL = 50Ω, VFS = 1V, 10 - 90% 0.75 - 0.85 ns Settling Time tSET - - 3.5 ns Glitch Energy GE - 1.5 5.0 pVS REFERENCE VREF Pin Voltage VREF IREF = 1mA VREF Temperature Drift AGND2+1.18 AGND2+1.25 AGND2+1.32 - VREF Multiplying Bandwidth 100mVP-P Sinewave at -3dB Digital Input (TTL Pin) Digital Output (DIV2OUT TTL Pin) Digital Input (PECL Pin) Digital Input Current (PS) Clamp Pin Input Current (VOCLP) Digital Input Capacitance - V 250 ppm/ oC 50 - - MHz VIH 2 - - V VIL - - 0.8 V VTH - 1.5 - V IIH VIH = 3.5V -1 - 1 µA IIL VIL = 0.2V -2 - 0 µA VOH IOH = -2mA 2.4 - - V VOL IOL = 1mA - - 0.5 V IOZ VO = 5V 10 - 100 µA IOZ VO = 0V -1 - 1 µA tr 0.8 to 2.4V (CL = 10pF) 1.0 - 1.5 ns tf 2.4 to 0.8V (CL = 10pF) 0.6 - 1.2 ns VIH DVCC1 - 1.5 - DVCC1 - 0.5 V VIL DVCC1 - 3.2 - DVCC1 - 1.4 V IIH VIH = DVCC1 - 0.8V 0 - 20 µA IIL VIL = DVCC1 - 1.5V -30 - 0 µA VIH 2 - - V VIL - - 0.8 V IIH VIH = 3.5V -1 - 100 µA IIL VIL = 0.2V -1 - 0 µA ICCLP VCCLP = DVCC1 ICCLP VCCLP = 2.4V CIN - - 5 µA -60 - -10 µA - 3 5 pF CURRENT CONSUMPTION Supply Current (Operating) ICC 8 63 96 129 mA DICC1 Total Operating 7 15.5 24 mA DICC2 13 19 25 mA AICC2 6 8.5 11 mA AICC0 37 53 68 mA HI3197 VSUPPLY = ±5V, AV = +1, RL = 100Ω (Continued) Electrical Specifications PARAMETER SYMBOL Supply Current (PS Mode) NOTE: The current consumption in power saving mode does not include the voltage reference (VREF) current. When using the internal reference the additional current IREF = VREF / RREF should be added to the table values for an accurate estimate of total standby current. AC Specifications TEST CONDITIONS MIN TYP MAX UNITS ICC Power Saving Mode - 0.432 4 mA DICC1 Power Saving Mode - 0.38 1.5 mA DICC2 Power Saving Mode - 0.001 0.2 mA AICC2 Power Saving Mode - 0.05 0.3 mA AICC0 Power Saving Mode - 0.001 2 mA MUX.1A and MUX.1B Modes CLK SIGNAL LEVEL PECL RESET SIGNAL LEVEL PARAMETER SYMBOL TTL PECL CONDITIONS PECL TTL TTL MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fC 125 - - 100 - - 125 - - MSPS Clock High Pulse Width tPW1 3.5 - - 4.5 - - 3.5 - - ns Clock Low Pulse Width tPW0 3.5 - - 3.0 - - 3.5 - - ns MUX.1A MODE Maximum Conversion Rate Reset Signal Setup Time tS-RST 0 - - 1.0 - - 4.0 - - ns Reset Signal Hold Time tH-RST 1.0 - - 3.0 - - 0 - - ns DIV2OUT Output Delay tD-DIV 5.5 6.5 8 8.0 9.5 12.0 5.5 6.5 8 ns DIV2OUT to DIV2IN Maximum Delay Time 2T-tm - - 2T - 7 - - 2T - 7 - - 2T - 7 ns tS 1.0 - - 1.0 - - 1.0 - - ns tH 5.0 - - 5.0 - - 5.0 - - ns tPD (A) - 4 - - 4 - - 4 - CLK Data Input Setup Time Data Input Hold Time Analog Output Pipeline Delay CL = 10pF tPD (B) - 5 - - 5 - - 5 - CLK tDO 5.0 5.5 6.0 6.5 7.5 8.5 5.0 5.5 6.0 ns fC 125 - - 100 - - 125 - - MSPS Clock High Pulse Width tPW1 3.5 - - 4.5 - - 3.5 - - ns Clock Low Pulse Width tPW0 3.5 - - 3.0 - - 3.5 - - ns Analog Output Delay MUX.1B MODE Maximum Conversion Rate Reset Signal Setup Time tS-RST 0 - - 1.0 - - 4.0 - - ns Reset Signal Hold Time tH-RST 1.0 - - 3.0 - - 0 - - ns Data Input Setup Time tS 1.0 - - 1.0 - - 1.0 - - ns Data Input Hold Time tH 4.0 - - 6.0 - - 4.0 - - ns Analog Output Pipeline Delay tPD (A) - 2 - - 2 - - 2 - CLK tPD (B) - 3 - - 3 - - 3 - CLK tDO 5.0 5.5 6.0 6.5 7.5 8.5 5.0 5.5 6.0 ns Analog Output Delay AC Specifications MUX.2, SEL.A, and SEL.B Modes CLK SIGNAL LEVEL PECL RESET SIGNAL LEVEL PARAMETER SYMBOL CONDITIONS TTL (NOTE 2) (NOTE 2) MIN TYP MAX MIN TYP MAX UNITS fC 125 - - 100 - - MSPS Clock High Pulse Width tPW1 3.5 - - 4.5 - - ns Clock Low Pulse Width tPW0 3.5 - - 3.0 - - ns DIV2IN Signal Setup Time tS-DIV 4.5 - - 2.0 - - ns MUX.2 MODE Maximum Conversion Rate 9 HI3197 AC Specifications MUX.2, SEL.A, and SEL.B Modes CLK SIGNAL LEVEL PECL RESET SIGNAL LEVEL PARAMETER SYMBOL DIV2IN Signal Hold Time Data Input Setup Time Data Input Hold Time Analog Output Pipeline Delay CONDITIONS TTL (NOTE 2) MIN TYP (NOTE 2) MAX MIN TYP MAX UNITS tH-DIV 0 - - 3.5 - - ns tS 1.0 - - 1.0 - - ns tH 5.0 - - 5.0 - - ns tPD (A) - 2 - - 2 - CLK tPD (B) - 3 - - 3 - CLK tDO 5.0 5.5 6.0 6.5 7.5 8.5 ns fC 125 - - 100 - - MSPS Clock High Pulse Width tPW1 3.5 - - 4.5 - - ns Clock Low Pulse Width tPW0 3.5 - - 3.0 - - ns C2 Signal Setup Time tS-C2 1.0 - - 1.0 - - ns C2 Signal Hold Time tH-C2 2.5 - - 3.5 - - ns Data Input Setup Time tS 1.0 - - 1.5 - - ns Data Input Hold Time tH 2.0 - - 3.5 - - ns tPD (A) - 1 - - 1 - CLK tPD (B) - 1 - - 1 - CLK tDO 5.0 5.5 6.0 6.5 7.5 8.5 ns Analog Output Delay SEL. A, SEL. B MODES Maximum Conversion Rate Analog Output Pipeline Delay Analog Output Delay NOTE: 2. The RESET signal is not input in MUX.2, SEL. A, or SEL. B modes. Electrical Characteristics Measurement Circuits +5V DVCC1 10 DGND1 DVCC2 AVCC2 AVCC0 DA0 TO DA9 AOUTP 50Ω 10-BIT DATA INPUT 10 HI3197 DB0 TO DB9 DVM (DIGITAL VOLTMETER) AOUTN 50Ω VSET CLK/T 937.5mV 1MHz TTL CLK C1 C2 C3 DGND2 AGND2 PC -5V -5V +5V FIGURE 1. DIFFERENTIAL LINEARITY ERROR, INTEGRAL LINEARITY ERROR 10 HI3197 Electrical Characteristics Measurement Circuits (Continued) +5V I1 I2 I3 ICC = I1 + I2 + I3 + I4 DICC1 = I1 DICC2 = I2 ALCC2 = I3 ALCC0 = I4 I4 DVCC1 DVCC2 AVCC2 AVCC0 HIGH FOR ALL SIDE A DATA 10 DA0 TO DA9 AOUTP 10 DB0 TO DB9 AOUTN LOW FOR ALL SIDE B DATA HI3197 VSET CLK/T 1MHz TTL CLK +5V 937.5mV DIV2IN DIV2OUT DGND1 DGND2 AGND2 PS C1 C2 C3 FIGURE 2. CURRENT CONSUMPTION +5V DGND1 DVCC2 AVCC2 AVCC0 DVCC1 HIGH FOR ALL SIDE A DATA 10 DA0 TO DA9 10 DB0 TO DB9 LOW FOR ALL SIDE B DATA AOUTP V 50Ω HI3197 CLK/T AOUTN V 1MHz TTL CLK 50Ω +5V PS C1 C2 C3 DGND2 AGND2 VSET 937.5mV -5V -5V +5V FIGURE 3. ANALOG OUTPUT CHARACTERISITCS, OUTPUT FULL-SCALE ABSOLUTE AMPLITUDE ERROR, OUTPUT ZERO OFFSET VOLTAGE 11 HI3197 Electrical Characteristics Measurement Circuits (Continued) OSCILLOSCOPE +5V DGND1 DVCC2 AVCC2 AVCC0 AOUTP DVCC1 DA0 TO DA9 DB0 TO DB9 10 DPG (DIGITAL PATTERN GENERATOR) 10 50Ω 50Ω AOUTN HI3197 CLKP/E VREF CLKN/E 100MHz PECL CLK C1 DGND2 AGND2 C2 C3 +5V VSET -5V -5V FIGURE 4. ANALOG OUTPUT RISE TIME, ANALOG OUTPUT FALL TIME, SETTLING TIME AND GLITCH ENERGY +5V OSCILLOSCOPE DGND1 DVCC2 AVCC2 AVCC0 DVCC1 HIGH FOR ALL SIDE A DATA HIGH FOR ALL SIDE B DATA 50Ω 10 DA0 TO DA9 AOUTP 10 DB0 TO DB9 AOUTN AVCC0 (= 0V) CLKP/E CLKN/E VREF AOUTP OUTPUT V 1mA 20MHz PECL CLK 0.1µF VSET +5V PS C1 VFS 50Ω HI3197 C2 C3 DGND2 AGND2 50Ω VSET PIN OUTPUT 100mVP-P AGND2 +937.5mV -5V +5V -5V FIGURE 5. REFERENCE/CONTROL AMPLIFIER CHARACTERISITCS, VREF PIN OUTPUT VOLTAGE, VREF PIN OUTPUT VOLTAGE IN POWER SAVING MODE, MULTIPLYING BANDWIDTH 12 HI3197 Electrical Characteristics Measurement Circuits (Continued) AVCC0 AVCC0 - VOF AOUTP OUTPUT (INV = 1) AVCC0 - VFS (AVCC0 - VOF) - (AVCC0 - VFS) = 1 LSB 1023 V(n + 1) - V(n) D.L.E. = I.L.E. = V (n + 1) -1 1 LSB (V(n) - n x 1 LSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 LSB V (n) 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 D9 DATA INPUT CODE (MSB) 0 D0 (LSB) FIGURE 6. TABLE 1. I/O CORRESPONDENCE TABLE DATA INPUT CODE INV = 1 (MSB) D9 ANALOG OUTPUT LEVEL INV = 0 (LSB) D0 (MSB) D9 (LSB) D0 AOUTP AOUTN 1111111111 0000000000 AVCC0 - VOF AVCC0 - VFS • • • • • • • • • • • • 0000000000 1111111111 AVCC0 - VFS AVCC0 - VOF 13 HI3197 Description of Operation The HI3197 has four types of operation modes to support various applications. The operation mode is set by switching the function setting pins (C1, C2 and C3). The HI3197 can input data divided into two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplex the data, and output it as an analog signal, making it possible to halve the data rate. This lets the HI3197 support the TTL data input level in contrast to the ECL data input level for conventional high-speed D/A converters. The clock signal and reset signal input levels can be selected from either TTL or PECL according to the application. (However, setting both signals to either TTL or PECL input level is recommended.) MUX.1A Mode Set C1, C2 and C3 all Low for this mode. In MUX.1A mode, the frequency of the clock input from the clock input pin is halved internally, and the 1/2 frequencydivided signal is output at TTL level from the DlV2OUT pin. Data synchronized with the DlV2OUT signal (the signal output from the DlV2OUT pin) can be obtained by operating the HI3197 front-end system with the DlV2OUT signal. The timing at which the data output delay of the HI3197 front-end system matches with the hold time during HI3197 data input can be easily set by inputting this synchronized data to the data input pins and the DlV2OUT signal to the DlV2lN pin. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplexed, and extracted as analog output. When using the multiple HI3197 in MUX.1A mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in Figure 7. As a countermeasure, the MUX.1A mode has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See Figure 7 for the detailed timing. TABLE 2. OPERATING MODES C1 C2 C3 CLK IN (MSPS) DATA IN (Mbps) AOUT (Mbps) MUX.1A 0 0 0 125 62.5 125 Outputs CLK/2 at TTL Level MUX Operation by the Internal CLK/2 MUX.1B 0 0 1 125 62.5 125 High Impedance MUX Operation by the Internal CLK/2 MUX.2 0 1 0 125 62.5 125 High Impedance MUX Operation by DIV2IN SELE.A 1 0 0 125 125 125 High Impedance D/A Conversion of Side A Data Input SELE.B 1 1 0 125 125 125 High Impedance D/A Conversion of Side B Data Input MODE DIV2OUT PIN DESCRIPTION OF OPERATION CLOCK INPUT PIN CLOCK INPUT 1/2 tD - DIV DIV2OUT PIN (DIV2OUT SIGNAL) DIV2IN PIN 10-BIT DATA A HI3197 FRONT-END SYSTEM DA0 TO DA9 10-BIT 10-BIT DATA B DB0 TO DB9 10-BIT DATA INPUT PINS FRONT-END SYSTEM DATA OUTPUT DELAY II HI3197 DATA INPUT HOLD TIME FIGURE 7A. MUX.1A 14 HI3197 (MUX.1A MODE) HI3197 CLK HI3197 CLK CLK DIV2OUT DIV2OUT HI3197 DIV2OUT CLKDIV2OUT FIGURE 7B. MUX.1A EXAMPLE WHEN NOT USING THE RESET SIGNAL CLK RESET SIGNAL (WHEN ACTIVE LOW) HI3197 CLK CLK DIV2OUT DIV2OUT RESET HI3197 CLKDIV2OUT RESET SIGNAL DIV2OUT RESET FIGURE 7C. MUX.1A EXAMPLE WHEN USING THE RESET SIGNAL FIGURE 7. MUX.1A MODE MUX.1B Mode Set C1 and C2 Low and C3 High for this mode. In MUX.1B mode, the frequency of the clock input from the clock input pin is halved internally, and the data is loaded by this 1/2 frequency-divided signal. The 1/2 frequency-divided signal cannot be observed at this time, so the data is actually loaded by observing the clock and reset signals to estimate the rising edge of the internally 1/2 frequency-divided signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay after loading by the clock. 15 Like MUX.1A mode, when using the multiple HI3197 in MUX.1B mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below. As a countermeasure, the MUX.1B mode also has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See Figure 8 for the detailed timing. HI3197 HI3197 (MUX. 1B MODE) CLOCK INPUT PIN CLOCK 1/2 tH-RST RESET SIGNAL (WHEN ACTIVE LOW) tS-RST RESET INPUT PIN INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL (THIS SIGNAL CANNOT BE OBSERVED) tS tH DA0 TO DA9 DB0 TO DB9 DATA INPUT SIGNAL AFTER THE RESET IS RELEASED, THE INTERNAL 1/2 FREQUENCY-DIVIDED SIGNAL COMMENCES AT THE FIRST CLOCK EDGE, SO BE SURE TO INPUT THE DATA IN A MANNER THAT SATISFIES THE SETUP TIME (TS) AND HOLD TIME (TH) WITH RESPECT TO THIS CLOCK EDGE. FIGURE 8A. CLK HI3197 CLK CLK INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL HI3197 CLK INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL FIGURE 8B. EXAMPLE WHEN NOT USING THE RESET SIGNAL CLK HI3197 CLK CLK RESET SIGNAL (WHEN ACTIVE LOW) INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL RESET HI3197 INTERNALLY 1/2 FREQUENCY-DIVIDED SIGNAL CLK RESET SIGNAL RESET FIGURE 8C. EXAMPLE WHEN USING THE RESET SIGNAL FIGURE 8. MUX.1B MODE 16 HI3197 MUX.2 Mode SELECT.A Mode and SELE.B Mode Set C1 and C3 Low and C2 High for this mode. Set C1 High and C2 and C3 Low for SELE.A mode. In MUX.2 mode, the clock is input to the clock input pin, and the signal with a cycle half that of the clock (hereafter, DlV2lN signal) is input to the DlV2IN pin at TTL level. The DlV2lN signal is internally latched by the clock, so consideration must be given to the setup time (tS_DIV) and hold time (tH_DIV) with respect to the clock. In addition, the data is loaded by the DlV2lN signal, so consideration must also be given to the setup time (tS) and hold time (tH) with respect to the DlV2IN signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data `is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay from the clock that loads the DIV2IN signal. See Figure 9 for the detailed timing. In SELE.A mode, the clock is input to the clock input pin, and the data is input to the system A (DA0 to DA9) data input pins. Set C1 and C2 High and C3 Low for SELE.B mode. In SELE.B mode, the clock is input to the clock input pin, and the data is input to the system B (DB0 to DB9) data input pins. In either mode, consideration must be given to the setup time, (tS) and hold time (tH) with respect to the clock. Also, the data is output as an analog signal with a 1-clock pipeline delay after loading by the clock. Switching between SELE.A mode and SELE.B mode is done by switching the C2 pin between High and Low levels. Also, the mode can be switched at high speed in sync with the clock by inputting the switching signal (02 signal) to the C2 pin. The C2 signal is internally latched by the clock, so consideration must be given to the setup time (tS_C2) and hold time (tH_C2) with respect to the clock. See Figure 10 for the detailed timing. tPD (B) CXA3197 (MUX.2 MODE) tPD (A) 0 1 2 3 CLOCK INPUT PIN CLOCK tS_DIV DIV2IN SIGNAL tS A0 SYSTEM A DATA DIV2IN INPUT PIN tH_DIV tH A1 A2 B1 B2 DA0 TO DA9 DB0 TO DB9 SYSTEM B DATA B0 ANALOG OUTPUT SIGNAL A1 B0 A0 B1 FIGURE 9. MUX.2 MODE tPD (A) 0 tPD (B) 0 1 CXA3197 (SELE.A MODE/SELE.B MODE) 1 CLOCK INPUT PIN CLOCK tA_C2 tH_C2 C2 INPUT PIN C2 SIGNAL tS tH DA0 TO DA9 SYSTEM A DATA A0 A1 A2 A6 A8 SELECT B3 SYSTEM B DATA ANALOG OUTPUT SIGNAL A0 A1 B5 B4 A2 B3 DB0 TO DB9 B7 B4 B5 A6 FIGURE 10. SELECT A MODE AND SELECT B MODE 17 HI3197 Block Diagram and Timing Charts CLK RESET R Q D Q CLK/2 (INTERNAL) DIV2OUT DIV2IN INPUT DATA A INPUT LATCH A LATCH INPUT LATCH B LATCH MUX INPUT DATA B DAC LATCH ANALOG OUT FIGURE 11A. BLOCK DIAGRAM (MUX.1A MODE) tPD tPD (A) tPW1 tPW0 CLK tS-RST 0 tH-RST 1 2 4 3 5 ACTIVE HIGH RESET ACTIVE LOW tD-DIV CLK/2 (INTERNAL) tM DIV2OUT TO DIV2IN tS 2t-tM tH INPUT DATA A N$ N$ N N+2 N+4 INPUT DATA B N$ N$ N+1 N+3 N+5 tDO N$ N$ N$ N$ N+1 N tDO FIGURE 11B. TIMING CHART (MUX.1A MODE) CLK PECL ±1/2 LSB 2.0V 2.0V TTL 0.8V 0.8V ANALOG OUTPUT ±1/2 LSB tDO tSET FIGURE 11C. TIMING JUDGMENT POINTS NOTE: In MUX.1A mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit and the CLK/2 can be output at TTL level (D1V201.~). CLK/2 can be reset by the reset signal. 18 HI3197 Block Diagram and Timing Charts (Continued) CLK R Q RESET CLK/2 D Q (INTERNAL) INPUT LATCH A INPUT DATA A LATCH MUX DAC ANALOG OUT INPUT LATCH B INPUT DATA B FIGURE 12A. BLOCK DIAGRAM (MUX.1B MODE) tPD (B) tPW1 tPW0 CLK RESET (ACTIVE HIGH) tS-RST tH-RST tPD (A) 0 1 2 3 (ACTIVE HIGH) (ACTIVE LOW) D-FF OUT CLK/2 (INTERNAL) tS tH INPUT DATA A N-2 N N+2 N+4 N+6 N+8 INPUT DATA B N-1 N+1 N+3 N+5 N+7 N+9 tDO N N+1 N+2 N+3 N+4 N+5 tDO FIGURE 12B. TIMING CHART (MUX.1B MODE) NOTE: In MUX.1B mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal. 19 HI3197 Block Diagram and Timing Charts (Continued) CLK R Q DIV2IN A INPUT DATA A CLK/2 D Q (INTERNAL) LATCH INPUT LATCH A LATCH MUX DAC ANALOG OUT B INPUT DATA B INPUT LATCH B LATCH FIGURE 13A. BLOCK DIAGRAM (MUX.2 MODE) tPD (B) tPW1 tPW0 tPD (A) CLK tS-DIV tH-DIV 0 1 2 3 DIV1IN tH tS M/S DATA A N-2 N N+2 N+4 N+6 N+8 M/S DATA B N-1 N+1 N+3 N+5 N+7 N+9 tDO N+3 N N+1 N+4 N+5 N+2 tDO FIGURE 13B. TIMING MODE (MUX.2 MODE) NOTE: In MUX.2 mode, the 1/2 frequency-divided clock signal (DlV2lN) and Data A and Data B, which are synchronized with DlV2lN, are provided simultaneously. These signals are internally multiplexed and the resulting signal can be analog output. 20 HI3197 Block Diagram and Timing Charts (Continued) CLK C2 LATCH INPUT DATA A INPUT LATCH A SELECT INPUT DATA B LATCH ANALOG OUT DAC INPUT LATCH B FIGURE 14A. BLOCK DIAGRAM (SELE.A, SELE.B MODE) tPW1 tPW0 CLK tPD (B) tPD (A) 0 1 0 tH-C2 1 tS-C2 C2 tS tH INPUT DATA A N - 2 N N+2 N+4 N+6 N+8 INPUT DATA B N - 1 N+1 N+3 N+5 N+7 N+9 SELE. A C2 M/S OUT SELE. B tDO tDO N-4 N+5 N N+7 N+2 N-2 FIGURE 14B. TIMING CHART (SELE.A, SELE.B MODE) NOTE: In SELE.A and SELE.B modes, input Data A or Data B is selected and the selected data can be analog output. When C1 = 1 and C3 = 0, Data A is selected for C2 = 0, and Data B is selected for C2 = 1. 21 HI3197 Typical Performance Curves 1100 OUTPUT FULL-SCALE VOLTAGE (mV) OUTPUT FULL-SCALE VOLTAGE (mV) 1100 RL = 50Ω 1000 900 800 700 0.65 0.84 VSET PIN VOLTAGE (V) 950 7 1260 1240 0 50 25 AMBIENT TEMPERATURE (oC) 75 ANALOG OUTPUT AMPLITUDE (dB) FIGURE 17. VREF PIN VOLTAGE vs AMBIENT TEMPERATURE 75 RL = 50Ω VSET = AGND2 + 937.5mW 6 5 4 3 -25 0 50 25 AMBIENT TEMPERATURE (oC) FIGURE 18. OUTPUT ZERO OFFSET VOLTAGE vs AMBIENT TEMPERATURE 0 -3 1 10 VSET PIN INPUT FREQUENCY (MHz) FIGURE 19. MULTIPLYING BANDWIDTH 22 25 0 50 AMBIENT TEMPERATURE (oC) FIGURE 16. OUTPUT FULL-SCALE VOLTAGE vs AMBIENT TEMPERATURE OUTPUT ZERO OFFSET VOLTAGE (mV) VREF PIN VOLTAGE (mV) 1000 900 -25 1280 1220 -25 1050 1.03 FIGURE 15. OUTPUT FULL-SCALE VOLTAGE vs VSET PIN VOLTAGE RL = 50Ω VSET = AGND2 + 937.5mW 100 75 HI3197 Application Circuit The circuit shown below is the basic circuit when the analog output is terminated with the external resistance of 50Ω in the dual ±5V power supplies for MUX.2 mode. The analog output full scale voltage VFS is obtained with the following equation: R = RO //RL RO : Output impedance ( = 50Ω) V SET 63 V FS = --------------- x 15 + ------ x R 375 64 RL : External termination resistance R2 Here, V SET = ---------------------- V REF R1 + R2 ( V REF ≈ 1.2V ) -5V (A) 0V (D) +5V (A) ( R1 + R2 ≥ 1.2k Ω ) 0V(A) VOCLP AGND2 INV POLARITY PS DVCC1 NC VSET 35 DA3 VREF 34 DA2 AGND2 33 5 DA1 AOUTP 32 6 DA0 (LSB) AOUTN 31 7 DB9 (MSB) AVCC0 30 8 DB8 DVCC2 29 9 DB7 C3 28 10 DB6 C2 27 0V(A) R1 R2 -5V(A) -5V(A) 0V(A) 0V(A) RL RL 0V(A) 0V(D) 0V(A) -5V(D) RESETN/E RESETP/E RESET/T CLKN/E DIV2N CLKP/E DGND2 25 CLK/T C1 26 12 DB4 DIV2OUT 11 DB5 DB3 DB0 TO DB9 DGND1 DA4 3 DB0 (LSB) ETC. DA8 2 DB1 LATCH (MSB) DA9 DA5 4 RAM AVCC2 36 1 DB2 DA0 TO DA9 DA7 DA6 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 130 +5V(D) 82 TTL CLK/2 0V(D) 82 130 PECL CLK VBB NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil Corporation cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 23 HI3197 Notes on Use • The HI3197 has PECL and TTL input pins for the clock and reset inputs. When the clock is input at PECL level, it is recommended to also input the reset signal at PECL level. Likewise, when the clock is input at TTL level, it is recommended to also input the reset signal at TTL level. • The input signal impedance should be properly matched to ensure the stable HI3197 operation at high speed. Particularly when ringing appears in the input clock in the MUX.1A and MUX.1B modes. If this ringing exceeds the clock input threshold value, the internal 1/2 frequency divider circuit may misoperate. • All TTL input pins of the HI3197 except for the PS pin go to High level when left open, and only the PS pin goes to Low level when left open. Set the PS pin to High level to operate the IC. When the PECL input pins are left open, the P (positive) side goes to High level and the N (negative) side goes to Low level. The PECL input pins are complementary, so be sure to use the P and N sides together. • When the clock and reset input signal level is TTL, ***/T pins should be used and ***/E pins left open. When the clock and reset input signal level is PECL, ***/E pins should be used and ***/T pins left open. • The power supply and grounding have a profound influence on converter characteristics. The power supply and grounding method are particularly important during highspeed operation. General points for caution are as follows: - The ground pattern should be as wide as possible. It is recommended to make the power supply and ground wider at an inner layer using a multi-layer board. To prevent a DC offset from being generated between the analog and digital power supply patterns, it is recommended to connect the patterns at one point via a ferrite-bead filter, etc. 24 - When using the HI3197 with a single power supply, connect DGND1 and DGND2 to a common digital ground, and AGND2 to an analog ground. Also, DVCC1 and DVCC2 should use a common digital power supply, and AVCC2 should be connected to an analog power supply. AVCC0 serves as the analog output reference, so while it does not need to share the analog power supply, it should be used within the range that satisfies the analog output compliance voltage. - When using the HI3197 with dual power supply, connect DGND1 and DVCC2 to the digital ground, and AVCC2 to the analog ground. DVCC1 uses a positive digital power supply (+5V, typ.), DGND2 uses a negative digital power supply (-5V, typ.), and AGND2 uses a negative analog power supply (-5V, typ.). Like when using a single power supply, the AVCC0 pin can be used within the range that satisfies the analog output compliance voltage. However, connecting it to the analog ground and using the analog ground as the reference for the analog output is recommended. • Ground the power supply pins as close to each pin as possible with a 0.1µF or more ceramic chip capacitor. When using a single power supply, connect DVCC1 and DVCC2 to the digital ground, and AVCC2 and AVCC0 to the analog ground. When using dual power supply, connect DVCC1 and DGND2 to the digital ground, and AGND2 to the analog ground. In this case, when using AVCC0 within the range that satisfies the compliance voltage, be sure to also connect the AVCC0 pin to the analog ground using a ceramic chip capacitor. • The HI3197 is designed with an analog output impedance of 50Ω. The analog outputs are wired with a characteristic impedance of 50Ω, and waveforms free of reflection can be obtained by terminating the analog outputs with 50Ω. Even when using only one of either AOUTP or AOUTN, if one analog output is terminated with 50Ω, be sure to also terminate the other analog output with 50Ω. (See Application Circuit Diagram) HI3197 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D Q48.7x7-S D1 48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES E E1 e MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.056 0.066 1.40 1.70 - A1 0.000 0.007 0.00 0.20 - B 0.006 0.010 0.15 0.26 5 D 0.347 0.362 8.80 9.20 2 D1 0.272 0.279 6.90 7.10 3, 4 E 0.347 0.362 8.80 9.20 2 E1 0.272 0.279 6.90 7.10 3, 4 L 0.012 0.027 0.30 0.70 N 48 48 e 0.020 BSC 0.500 BSC 6 Rev. 1 4/95 PIN 1 NOTES: -H- SEATING PLANE A 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 0.10 0.004 -C- 0.24 M B 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. A1 0o-10o L 0.107/0.177 0.004/0.007 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 25 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029