I GNS D ES W E T OR N DU C ED F TE PRO 080A D N I TU I P4 MME BSTSheet ER H U ECO E SData B R M T NO T NU SIBL POS SIL PAR R I N TE HIP4080 ® 80V/2.5A Peak, High Frequency Full Bridge FET Driver February, 2003 Features The HIP4080 is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4080 includes an input comparator, used to facilitate the “hysteresis” and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the HIP4080 is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. HIP4080 can also drive medium voltage brush motors, and two HIP4080s can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability. • Drives N-Channel FET Full Bridge Including High Side Chop Capability • Bootstrap Supply Max Voltage to 95VDC • Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of 10ns (Typ) • User-Programmable Dead Time • Charge-Pump and Bootstrap Maintain Upper Bias Supplies • DIS (Disable) Pin Pulls Gates Low • Input Logic Thresholds Compatible with 5V to 15V Logic Levels Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. • Very Low Power Consumption The similar HIP4081 IC allows independent control of all 4 FETs in an Full Bridge configuration. • Medium/Large Voice Coil Motors Applications • Full Bridge Power Supplies See also, Application Note AN9324 for the HIP4080. • Switching Power Amplifiers Similar part, HIP4080A, includes under voltage circuitry which doesn’t require the circuitry shown in Figure 30 of this data sheet. • High Performance Motor Controls Ordering Information • Battery Powered Vehicles PART NUMBER TEMP. RANGE (oC) PACKAGE FN3178.11 PKG. NO. HIP4080IP -40 to 85 20 Lead PDIP E20.3 HIP4080IB -40 to 85 20 Lead SOIC M20.3 • Noise Cancellation Systems • Peripherals • U.P.S. Pinout HIP4080 (20-LEAD PDIP, SOIC) TOP VIEW 1 BHB 1 HEN 2 19 BHS DIS 3 18 BLO VSS 4 17 BLS OUT 5 16 VDD IN+ 6 15 VCC 20 BHO IN- 7 14 ALS HDEL 8 13 ALO LDEL 9 12 AHS AHB 10 11 AHO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIP4080 Application Block Diagram 80V 12V BHO BHS HEN LOAD BLO DIS HIP4080 IN+ ALO IN- AHS AHO GND GND Functional Block Diagram (1/2 HIP4080) HIGH VOLTAGE BUS ≤ 80VDC AHB 10 CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 2 DIS 3 CBS AHS VDD 16 HEN AHO 11 12 TURN-ON DELAY DBS 15 OUT IN+ 5 6 IN_ 7 HDEL 8 LDEL 9 VSS 4 DRIVER TURN-ON DELAY + - VCC ALO 13 ALS 14 2 TO VDD (PIN 16) CBF +12VDC BIAS SUPPLY HIP4080 Typical Application (Hysteresis Mode Switching) 80V 1 BHB BHO 20 12V 2 HEN BHS 19 DIS 3 DIS BLO 18 4 VSS BLS 17 5 OUT VDD 16 6V IN 6 IN+ VCC 15 7 IN- ALS 14 8 HDEL ALO 13 9 LDEL LOAD 12V AHS 12 10 AHB AHO 11 GND + 6V GND 3 HIP4080 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHBVAHS, BHS -0.3V to VAHS, BHS +16VVoltage on Voltage on ALO, BLO. . . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns All Voltages relative to pin 4, VSS, unless otherwise specified. Thermal Resistance (Typical, Note 1) . . . . . . . . . . . . . . . θJA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Power Dissipation at 85oC SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470mW DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . +8V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . -500µA to -50µA Operating Ambient Temperature Range . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = 25oC, Unless Otherwise Specified TJ = - 40oC TO 125oC TJ = 25oC PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current IDD IN- = 2.5V, Other Inputs = 0V 8 10.5 13 7 14 mA VDD Operating Current IDDO Outputs switching f = 500kHz 9 11 14 8 15 mA VCC Quiescent Current ICC IN- = 2.5V, Other Inputs = 0V, IALO = IBLO = 0 - 25 80 - 100 µA VCC Operating Current ICCO f = 500kHz, No Load 1 1.5 2.0 0.8 3 mA IN- = 2.5V, Other Inputs = 0V, IAHO = IBHO = 0, VDD = VCC = VAHB = VBHB = 10V -50 -30 -15 -60 -10 µA f = 500kHz, No Load 0.5 0.9 1.3 0.4 1.7 mA - 0.02 1.0 - 10 µA IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V Over Common Mode Voltage Range -10 0 +10 -15 +15 mV IIB 0 0.5 2 0 4 µA IOS -1 0 +1 -2 +2 µA Input Common Mode Voltage Range CMVR 1 - VDD -1.5 1 VDD -1.5 V Voltage Gain AVOL 10 25 - 10 - V/mV AHB, BHB Quiescent Current Qpump Output Current IAHB, IBHB AHB, BHB Operating Current IAHBO, IBHBO AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage IHLK VAHB VAHS VBHB VBHS VAHS = VBHS = VAHB = VBHB = 95V INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage VOS Input Bias Current Input Offset Current 4 HIP4080 Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = 25oC, Unless Otherwise Specified (Continued) TJ = - 40oC TO 125oC TJ = 25oC PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS OUT High Level Output Voltage VOH IN+ > IN-, IOH = -300µA VDD -0.4 - - VDD - 0.5 - V OUT Low Level Output Voltage VOL IN+ < IN-, IOL = 300µA - - 0.3 - 0.4 V High Level Output Current IOH VOUT = 6V -9 -7 -4 -11 -2 mA Low Level Output Current IOL VOUT = 6V 8 10 12 5 14 mA Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V - 35 - - - mV INPUT PINS: DIS Input Voltage Hysteresis Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V - 35 - - - mV INPUT PINS: HEN Input Voltage Hysteresis Low Level Input Current IIL VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 µA High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA IHDEL = ILDEL = -100µA 4.9 5.1 5.3 4.8 5.4 V TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL,V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage VOL IOUT = 100mA .70 0.85 1.0 0.5 1.1 V High Level Output Voltage VCC - VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V Peak Pull-up Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A Peak Pull-down Current IO - VOUT = 12V 1.7 2.4 3.3 1.3 3.6 A Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF, and TA = 25oC, Unless Otherwise Specified TJ = - 40oC TO 125oC TJ = 25oC PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) TLPHL - 40 70 - 90 ns Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) THPHL - 50 80 - 110 ns Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) TLPLH RHDEL = RLDEL = 10K - 45 70 - 90 ns Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) THPLH RHDEL = RLDEL = 10K - 70 110 - 140 ns Rise Time Tr - 10 25 - 35 ns Fall Time Tf - 10 25 - 35 ns Turn-on Input Pulse Width TPWIN-ON RHDEL = RLDEL = 10K 50 - - 50 - ns Turn-off Input Pulse Width TPWIN-OFF RHDEL = RLDEL = 10K 40 - - 40 - ns 5 HIP4080 Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF, and TA = 25oC, Unless Otherwise Specified (Continued) TJ = - 40oC TO 125oC TJ = 25oC PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW - 45 75 - 95 ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 55 85 - 105 ns TDLPLH - 35 70 - 90 ns TREF-PW 160 260 380 140 420 ns TUEN - 335 500 - 550 ns Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO) HEN-AHO, BHO Turn-off, Propagation Delay THEN-PHL RHDEL = RLDEL = 10K - 35 70 - 90 ns HEN-AHO, BHO Turn-on, Propagation Delay THEN-PLH RHDEL = RLDEL = 10K - 60 90 - 110 ns TRUTH TABLE INPUT OUTPUT IN+ > IN- HEN DIS ALO AHO BLO BHO X X 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 Pin Descriptions PIN NUMBER SYMBOL 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 4 VSS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Non-inverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL DESCRIPTION High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 6 HIP4080 Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. 7 HIP4080 Timing Diagrams THPHL TDT TLPLH DIS = 0 HEN = 1 IN+ > IN- ALO AHO BLO BHO THPLH TLPHL TDT Tr Tf (10% - 90%) (90% - 10%) FIGURE 1. BI-STATE MODE THEN-PHL THEN-PLH DIS = 0 HEN IN+ > INALO AHO BLO BHO FIGURE 2. HIGH SIDE CHOP MODE TDLPLH TDIS TREF-PW DIS HEN = 1 IN+ > INALO AHO BLO BHO TUEN FIGURE 3. DISABLE FUNCTION 8 HIP4080 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL= 100K, and TA = 25oC, Unless Otherwise Specified 13 12.5 12.0 SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 14.0 10.0 8.0 6.0 12.0 11.5 11.0 4.0 10.5 2.0 8 10 12 VDD SUPPLY VOLTAGE (V) 10 14 600 800 1000 FIGURE 5. IDDO , NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) 30.0 5.0 ICC SUPPLY CURRENT (mA) 25.0 20.0 15.0 10.0 5.0 0.0 125oC 75oC 4.0 25oC 0oC 3.0 -40oC 2.0 1.0 0.0 0 100 200 300 400 500 600 700 800 900 1000 0 100 SWITCHING FREQUENCY (kHz) 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE COMPARATOR INPUT CURRENT (µA) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) FLOATING SUPPLY BIAS CURRENT (mA) 400 SWITCHING FREQUENCY (kHz) FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE FLOATING SUPPLY BIAS CURRENT (mA) 200 1.8 1.4 1.0 0.6 0.2 1.0 0.5 -0.2 0 200 400 600 800 1000 FREQUENCY (kHz) FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY 9 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERATURE AT VCM = 5V 120 HIP4080 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL= 100K, and TA = 25oC, Unless Otherwise Specified (Continued) -180 LOW LEVEL INPUT CURRENT (µA) LOW LEVEL INPUT CURRENT (µA) -90 -100 -110 -120 -50 -190 -200 -210 -220 -230 -25 0 25 50 75 100 -40 125 -20 0 JUNCTION TEMPERATURE (oC) 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 80 15.0 PROPAGATION DELAY (ns) NO-LOAD FLOATING CHARGE PUMP VOLTAGE 20 14.0 13.0 12.0 11.0 70 60 50 40 30 10.0 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE 10 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE HIP4080 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL= 100K, and TA = 25oC, Unless Otherwise Specified (Continued) 80 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 400 380 360 340 320 300 -40 70 60 50 40 30 -20 0 20 40 60 80 100 120 -40 -20 JUNCTION TEMPERATURE (oC) 40 60 80 100 120 FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE 375 80 PROPAGATION DELAY (ns) REFRESH PULSE WIDTH (ns) 20 JUNCTION TEMPERATURE (oC) FIGURE 14. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE 325 275 225 175 -40 0 70 60 50 40 30 20 -20 0 20 40 60 80 JUNCTION TEMPERATURE (oC) FIGURE 16. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE 11 100 120 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE 120 HIP4080 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL= 100K, and TA = 25oC, Unless Otherwise Specified (Continued) 90.0 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 90.0 80.0 70.0 60.0 50.0 80.0 70.0 60.0 50.0 40.0 40.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 JUNCTION TEMPERATURE (oC) PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 80 100 120 90.0 80.0 70.0 60.0 50.0 80.0 70.0 60.0 50.0 40.0 40.0 -20 0 20 40 60 80 100 -40 120 -20 0 JUNCTION TEMPERATURE (oC) 12.5 12.5 TURN-ON RISE TIME (ns) 13.5 11.5 10.5 9.5 8.5 0 20 40 60 80 JUNCTION TEMPERATURE (oC) 100 120 FIGURE 22. GATE DRIVE FALL TIME TF vs TEMPERATURE 12 40 60 80 100 120 FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE 13.5 -20 20 JUNCTION TEMPERATURE (oC) FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE GATE DRIVE FALL TIME (ns) 60 FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE 90.0 -40 40 JUNCTION TEMPERATURE (oC) FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE -40 20 11.5 10.5 9.5 8.5 -40 -20 0 20 40 60 80 JUNCTION TEMPERATURE (C) 100 120 FIGURE 23. GATE DRIVE RISE TIME TR vs TEMPERATURE HIP4080 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL= 100K, and TA = 25oC, Unless Otherwise Specified (Continued) 1500 1250 5.5 VCC - VOH (mV) HDEL, LDEL INPUT VOLTAGE (V) 6.0 5.0 1000 750 -40oC 0oC 500 25oC 4.5 250 75oC 125oC 0 4.0 -40 -20 0 20 40 60 80 100 6 120 8 JUNCTION TEMPERATURE (oC) FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE 12 14 FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA 1500 GATE DRIVE SINK CURRENT (A) 3.5 1250 1000 VOL (mV) 10 BIAS SUPPLY VOLTAGE (V) 750 -40oC 0oC 500 25oC 250 75oC 125oC 0 6 3.0 2.5 2.0 1.5 1.0 0.5 0.0 8 10 12 BIAS SUPPLY VOLTAGE (V) 14 FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA 13 6 7 8 9 10 11 12 13 14 15 16 VDD , VCC , VAHB, VBHB (V) FIGURE 27. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE HIP4080 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL= 100K, and TA = 25oC, Unless Otherwise Specified (Continued) 500 LOW VOLTAGE BIAS CURRENT (mA) GATE DRIVE SINK CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 200 100 10,000 50 3,000 20 1,000 10 100 5 2 1 0.5 0.2 0.1 6 7 8 9 10 11 12 13 14 15 16 1 2 VDD, VCC , VAHB , VBHB (V) 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY VOLTAGE FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 1000 150 120 200 100 DEAD-TIME (ns) LEVEL-SHIFT CURRENT (µA) 500 50 20 10 80V 5 60V 60 30 40V 2 90 20V 1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE HIP4080 Power-up Application Information The HIP4080 H-Bridge Driver IC requires external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-Bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. The HIP4080 does not have an input protocol like the HIP4081 that keeps both lower power MOSFETs off other than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming DIS is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 32. Pulling LDEL to VDD will indefinitely delay the lower turn-on delays through the input comparator and will 14 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (kΩ) 250 FIGURE 31. MINIMUM DEAD-TIME vs DEL RESISTANCE keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e. DIS = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure 32. HIP4080 1 BHB VDD VDD ENABLE 56K 2N3906 56K VDD 8.2V RDEL 100K 100K BHS 19 3 DIS BLO 18 4 VSS BLS 17 5 OUT VDD 16 6 IN+ VCC 15 7 IN- ALS 14 8 HDEL ALO 13 9 LDEL 0.1µF RDEL BHO 20 2 HEN 10 AHB AHS 12 AHO 11 FIGURE 32. VDD 12V, FINAL VALUE 8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE) DIS LDEL 5.1V t1 =10ms t2 NOTES: 2. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+ and IN- pins must cycle at least once. 3. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. FIGURE 33. TIMING DIAGRAM FOR FIGURE 32 15 IN2 IN1 POWER SECTION +12V B+ 2 1 + C6 JMPR5 CONTROL LOGIC SECTION R29 16 CD4069UB 13 U2 12 JMPR2 4 V SS 5 OUT/BLI 6 IN+/ALI IN+/ALI CD4069UB 5 U2 6 CD4069UB 11 U2 10 JMPR4 3 IN-/AHI CW 1 3 AO 2 +12V DD R23 VCC 15 ALS 14 1 Q2 BO C2 3 13 2 12 R24 11 1 Q4 3 CX CY R30 C5 R31 COM ALS BLS O VDD VDD NOTES: ENABLE O 4. Circuit inside dashed area must be hardwired and is not included on the evaluation board. TO DIS 56K 56K 5. Device CD4069UB PIN 7 = COM, Pin 14 = +12V. 2N3906 8.2V 3 U2 4 CD4069UB 100K 9 U2 8 I 0.1MFD CD4069UB FIGURE 34. HIP4080 EVALUATION PC BOARD SCHEMATIC 6. Components L1, L2, C1, C2, CX, CY, R30, R31, are not supplied. refer to Application Note for description of input logic operation to determine jumper locations for JMPR1 - JMPR4. HIP4080 C3 1 L2 C1 CR1 2 1 2 Q3 L1 BLS 17 16 V AHO 3 2 CW CD4069UB 10 AHB R34 R33 C8 Q1 3 7 IN-/AHI 8 HDEL ALO 9 LDEL AHS JMPR3 HEN/BHI 1 R22 C4 U1 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 OUT/BLI 2 CR2 HIP4080/81 JMPR1 U2 R21 DRIVER SECTION C1 R26 COM C8 C6 R28 B+ CR2 AO + R32 JMPR5 R29 C7 17 + R27 +12V GND Q1 C4 BHO U1 Q3 1 R22 1 O IN2 ALS ALO Q4 1 1 R21 AHO O CY CX FIGURE 35. HIP4080 EVALUATION BOARD SILKSCREEN R31 R34 R30 CR1 R33 BLS C3 C5 ALS HDEL LDEL L2 C2 Q2 R23 BO HIP4080 JMPR1 JMPR2 JMPR3 JMPR4 I BLO BLS L1 IN1 HIP4080/81 R24 DIS U2 HIP4080 Supplemental Information for HIP4080 and HIP4081 Power-Up Application prior to DIS reaching its threshold level of 1.7V while VDD/VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low. The HIP4080 and HIP4081 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. HIP4080 The HIP4080 does not have an input protocol like the HIP4081 that keeps both lower power MOSFETs off other than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming DIS is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 37. Pulling LDEL to VDD will indefinitely delay the lower turn-on delays through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e., DIS = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure 37. HIP4081 The HIP4081 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the DIS pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 36. As the VDD/VCC supply ramps from zero up, the DIS voltage is below its input threshold of 1.7V due to the R1/R2 resistor divider. When VDD/VCC exceeds approximately 9V to 10V, DIS becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low R1 15K ENABLE R2 3.3K ENABLE 1 BHB BHO 20 2 BHI BHS 19 3 DIS BLO 18 4 VSS BLS 17 5 BLI VDD 16 6 ALI VCC 15 6 ALI VCC 15 7 AHI ALS 14 7 AHI ALS 14 8 HDEL ALO 13 8 HDEL ALO 13 9 LDEL AHS 12 10 AHB R1 15K R2 3.3K 1 BHB BHS 19 3 DIS BLO 18 4 VSS BLS 17 5 BLI VDD 16 9 LDEL AHO 11 BHO 20 2 BHI AHS 12 10 AHB AHO 11 1 BHB BHO 20 FIGURE 36. VDD VDD ENABLE 56K 2N3906 56K VDD 8.2V 100K 100K 0.1µF FIGURE 37. 18 RDEL RDEL 2 HEN BHS 19 3 DIS BLO 18 4 VSS BLS 17 5 OUT VDD 16 6 IN+ VCC 15 7 IN- ALS 14 8 HDEL ALO 13 9 LDEL AHS 12 10 AHB AHO 11 HIP4080 Timing Diagrams VDD 12V, FINAL VALUE 8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE) VDD 12V, FINAL VALUE 8.5V TO 10.5V (ASSUMES 5% RESISTORS) DIS ALI, BLI LDEL 5.1V DIS t1 1.7V NOTE: =10ms t2 NOTE: 7. ALI and/or BLI may be high after t1, whereupon the ENABLE pin may also be brought high. FIGURE 38. 8. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the undervoltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+ and IN- pins must cycle at least once. FIGURE 39. 19 HIP4080 Small Outline Plastic Packages (SOIC) N INDEX AREA H 0.25(0.010) M M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e µα A1 B 0.25(0.010) M 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e C B S 0.050 BSC 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 20 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 N NOTES: MILLIMETERS α 20 0o 1.27 20 8o 0o 6 7 8o Rev. 0 12/93 HIP4080 Dual-In-Line Plastic Packages (PDIP) N E20.3 (JEDEC MS-001-AD ISSUE D) 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 N/2 INCHES -B-AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - C L B 0.014 0.022 0.356 0.558 - eA B1 0.045 0.070 1.55 1.77 8 C 0.008 0.014 D 0.980 1.060 24.89 C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.204 0.355 - 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e eA 0.100 BSC 0.300 BSC eB - L 0.115 N 2.54 BSC 20 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 20 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6 7 4 9 Rev. 0 12/93 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21