HT6576A Advanced SCSI CHIP Features • • • • • Support the ANSI X3.131-1986 standard Asynchronous transfer rate to 5 Mbyte/sec Support initiator and target mode 0.8um CMOS process • • On chip 48mA single-ended drivers and receivers Non internal clock needed 44pins PLCC package Block Diagram 1 14th July ’97 HT6576A Pin Diagram Pin Description Host Interface Signal Pin No Pin Name I/O Description 14~16 A0~A2 I Address Lines 17 CS I Chip Select, active low 11 DACK I DMA Acknowledge, active low 9 DRQ O DMA Request 24~28, 20~22 D0~D7 10 EOP I End of Process, active low 19 IOR I I/O Read, active low 18 IOW I I/O Write, active low 8 IRQ O Interrupt Request 13 READY O Ready 7 RESET I Reset, active low I/O Data Lines 2 14th July ’97 HT6576A SCSI Interface Signals Pin No Pin Name I/O Description 33 ACK I/O Acknowledge, active low 6 ATN I/O Attention, active low 4 BSY I/O Busy, active low 30 C/D I/O Control/Data, active low 32 I/O I/O Input/Output, active low 29 MSG I/O Message, active low 34 REQ I/O Request, active low 2 RST I/O Reset, active low 37~41, 43, 44, 1 DB0–DB7 I/O SCSI Data Bus, active low 35 DBP I/O SCSI Parity Bit, active low 5 SEL I/O Select, active low VSS 3, 12, 31, 36, 42 VDD 23 Registers Address 0 Current SCSI data register(READ ONLY) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB2 DB1 DB0 The SCSI bus parity is checked at the beginning of the read cycle. Output data register(WRITE ONLY) DB7 DB6 DB5 DB4 DB3 3 14th July ’97 HT6576A Address 1: Initiator command register WRITE 7 6 5 ASSERT TRI–STATE RESERVED RST 4 3 2 1 0 ASSERT ACK ASSERT BSY ASSERT SEL ASSERT ATN ASSERT DATA • BIT 7: ASSERT RST WHEN SET, THE RST SIGNAL IS ASSERTED ON THE SCSI BUS • BIT 6: TRI–STATE (TEST MODE) • BIT 5: RESERVED (0) • BIT 4: ASSERT ACK WHEN SET, THE ACK SIGNAL IS ASSERTED ON THE SCSI BUS • BIT 3: ASSERT BSY WHEN SET, THE BSY SIGNAL IS ASSERTED ON THE SCSI BUS • BIT 2: ASSERT SEL WHEN SET, THE SEL SIGNAL IS ASSERTED ON THE SCSI BUS • BIT 1: ASSERT ATN WHEN SET, THE ATN SIGNAL IS ASSERTED ON THE SCSI BUS • BIT 0: ASSERT DATA WHEN SET, This bit allows the contents of the output data register to be enabled as chip outputs on SCSI signal DB0–DB7 READ 7 6 5 4 3 2 1 0 RET ARBIT PROGRESS LOST ARBIT ACK BSY SEL ATN ASSERT DATA Address 2: Mode register READ/WRITE 7 6 5 4 3 2 1 0 LOCK DMA TARGET MODE ENABLE PARITY ENABLE PARITY ENABLE EOP MONITOR CHECK BUSY DMA IRQ MODE ARBIT • BIT 7: BLOCK MODE DMA • BIT 6: TARGET MODE When set, the chip operates as an SCSI bus target device. • BIT 5: ENABLE PARITY CHECKING When set, data received on the SCSI data bus is checked for odd parity. 4 14th July ’97 HT6576A • BIT 4: ENABLE PARITY INTERRUPT When set, this bit causes the IRQ signal to be asserted if a parity error is detected. • BIT 3: ENABLE EOP INTERRUPT When set, this bit causes the IRQ signal to be asserted if EOP is received from the DMA controller. • BIT 2: MONITOR BUSY When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for at least a bus settle delay. • BIT 1: DMA MODE • BIT 0: Arbitrate When set, this bit starts the arbitration process. Address 3: Target command register 7 6 5 4 3 2 1 0 LAST BYTE X X X ASSERT REQ ASSERT MSG ASSERT C/D ASSERT I/O R R/W R/W R/W R/W • BIT 7: LAST BYTE SEND (READ ONLY) • BIT 3: ASSERT REQ WHEN SET, THE REQ SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE) • BIT 2: ASSERT MSG WHEN SET, THE MSG SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE) • BIT 1: ASSERT C/D WHEN SET, THE C/D SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE) • BIT 0: ASSERT I/O WHEN SET, THE I/O SIGNAL IS ASSERTED ON THE SCSI BUS (IN TAGRTE MODE) Address 4: Current SCSI Bus Register READ 7 6 5 4 3 2 1 0 RST BSY REQ MSG C/D I/O SEL DBP WRITE –SELECT ENABLE REGISTER 7 6 5 4 3 2 1 0 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 5 14th July ’97 HT6576A Address 5: Bus And Status READ 7 6 END DMA WRITE 5 DMA REQUEST 4 PARITY ERROR 3 IRQ 2 PHASE MATCH 1 BUS ERROR 0 ATN ACK –START DMA SEND 7 6 5 4 3 2 1 0 X X X X X X X X Address 6: Input Data READ 7 6 5 4 3 2 1 0 LDB7 LDB6 LDB5 LDB4 LDB3 LDB2 LDB1 LDB0 LATCH SCSI DATA. The register represent the complement of the active low SCSI data bus. WRITE –START DMA TARGET RECEIVE 7 6 5 4 3 2 1 0 X X X X X X X X Address 7: READ –RESET PARITY/INTERRUPT 7 6 5 4 3 2 1 0 X X X X X X X X WRITE –START DMA INITIATOR RECEIVE 7 6 5 4 3 2 1 0 X X X X X X X X 6 14th July ’97 HT6576A Interrupts SELECTION/RESELECTION • SEL= ACTIVE LOW • BSY IS FALSE FOR AT LEAST 400NS • HT6576A DEVICE ID (SELECT REGISTER) is active on the SCSI bus will generate IRQ. END OF PROCESS (EOP) INTERRUPT • EOP= ACTIVE LOW • DACK= ACTIVE LOW • IOR OR IOW= ACTIVE LOW • DMA MODE • ENABLE EOP IRQ⇒ GENERATE EOP IRQ SCSI BUS RST/IRQ When An SCSI RST active low, the IRQ is generated. PARITY ERROR IRQ An IRQ is generated for a received parity error if enable parity checking bit and the enable parity interrupt bit are set. BUS PHASE MISMATCH IRQ If the DMA MODE bit is active and a phase mismatch occurs when REQ from false to true, an interrupt is generated LOSS OF BSY/IRQ • MONITOR BSY bit= 1 • BSY= ACTIVE LOW FOR 400ns WILL GENERATE IRQ 7 14th July ’97 HT6576A Electrical Characteristics D.C. Characteristics (Ta=25°C) Absolute Maximum Ratings Symbol Parameter Min. Max. Unit Tstg Storage Temperature –55 150 °C VDD Supply Voltage –0.5 7.0 V VIN Input Voltage VSS–0.5 VDD+0.5 V ESD Electrostatic Discharge –5000 5000 V (Ta=25°C) Operating Conditions Symbol Parameter Min. Max. Unit VDD Supply Voltage 4.75 5.25 V IDD Supply Current — 20 mA Ta Operating Free-Air 0 70 °C (Ta=25°C) SCSI Signals Symbol Characteristic Condition Min. Max. Unit VIH Input High Voltage — 2.0 VDD+0.5 V VIL Input Low Voltage — VSS–0.5 0.8 V VOL Output Low Voltage IOL=48mA VSS 0.5 V VHYS Hysteresis — 200 450 mV IOL Output Low Current VOL=0.5 48 — mA IIH Input High Leakage VIH= 5.25V — 50 µA IIL Input Low Leakage VIL=VSS — –50 µA 8 14th July ’97 HT6576A (Ta=25°C) Microprocessor Data Bus D0-D7 Symbol Characteristic Condition Min. Max. Unit VIH Input High Voltage — 2.0 VDD+0.5 V VIL Input Low Voltage — VSS–0.5 0.8 V VOH Output High Voltage IOH=–4.0mA 2.4 VDD V VOL Output Low Voltage IOL=8.0mA VSS 0.4 V IOH Output High Current VOH=VDD–0.5V –4.0 — mA IOL Output Low Current VOL=0.4V 8.0 — mA IIH Input High Leakage VIH=5.25V — 10 µA IIL Input Low Leakage VIL=VSS — –10 µA ITL Tri-State Leakage –10 10 µA — (Ta=25°C) A0~A2, CS, EOP, IOR, IOW, RESET Symbol Characteristic Condition Min. Max. Unit VIH Input High Voltage — 2.0 VDD+0.5 V VIL Input Low Voltage — VSS–0.5 0.8 V IIH Input High Leakage VIH=5.25V 10 — µA IIL Input Low Leakage VIL=VSS –10 — µA Min. Max. Unit DRQ, IRQ, READY, Symbol Characteristic Condition VOH Output High Voltage IOH=–4.0mA 2.4 VDD V VOL Output Low Voltage IOL=8.0mA VSS 0.4 V IOH Output High Current VOH=VDD–0.5V –4.0 — mA IOL Output Low Current VOL=0.4V 8.0 — mA 9 14th July ’97 HT6576A Timing Diagram Initiator Send Name Description Min. Max. Unit t1 SCSI Data setup time to ACK active 40 — ns t2 Data Bus held time from IOW inactive 10 — ns t3 IOW active time 30 — ns t4 DACK active, to DRQ inactive — 20 ns t5 ACK active to next DRQ active — 45 ns t6 EOP active time 30 — ns 10 14th July ’97 HT6576A Initiator Receive Name Description Min. Max. Unit t1 IOR inactive to next REQ active 50 — ns t2 REQ active to ACK active 50 — ns t3 IOR inactive to ACK inactive 10 — ns t4 ACK inactive time 50 — ns t5 Data Bus hold time from IOR inactive 10 — ns t6 Data Bus valid time from IOR active — 20 ns t7 REQ active to DRQ active — 25 ns t8 DACK active to DRQ inactive — 20 ns t9 DACK inactive to next DRQ active 20 — ns t10 EOP active time 30 — ns 11 14th July ’97 HT6576A Target Send (Non-block mode) Name Description Min. Max. Unit t1 SCSI data hold time from IOW inactive — 30 ns t2 SCSI data setup time to REQ active 40 — ns t3 ACK active to REQ inactive — 30 ns t4 Data Bus setup time to IOW inactive 10 — ns t5 Data Bus hold time from IOW inactive 10 — ns t6 IOW active time 30 — ns t7 DACK active to DRQ inactive — 20 ns t8 IOW inactive to DACK inactive 0 — ns t9 ACK active to next DRQ active — 45 ns 12 14th July ’97 HT6576A Target Receive (Non-block mode) Name Description Min. Max. Unit t1 ACK inactive to next REQ active 50 — ns t2 ACK active to REQ inactive — 30 ns t3 IOR inactive to next REQ active 50 — ns t4 Data Bus setup time to IOR active — 20 ns t5 Data Bus hold time from IOR inactive 10 — ns t6 IOR active time 30 — ns t7 DACK active to DRQ inactive — 20 ns t8 IOR inactive to DACK inactive 0 — ns 13 14th July ’97 HT6576A PIO Timing t1 t3 t2 t2 D7~0 A2~0 CS IOR t4 t4 IOW RESET DACK DRQ Name Description Min. Max. Unit t1 Data valid time from IOR active — 20 ns t2 Data hold time from IOR inactive 10 — ns t3 Data setup time to IOW inactive 10 — ns t4 IOR or IOW active time 30 — ns 14 14th July ’97