3.3V SDRAM Modules HYS64V32220GD(L) 256MB PC100/PC133 144 pin SO-DIMM SDRAM Modules Datasheet • 144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for notebook applications • Two bank 32M x 64 (256 MByte) non-parity module organisation • Performance: -7.5 -8 PC133 3-3-3 PC100 2-2-2 Units fCK Clock frequency (max.) 133 100 MHz tAC Clock access time 5.4 6 ns • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Eight 256Mbit SDRAM components in TSOP54 packages with 16M x 16 organisation in two memory banks • 8192 refresh cycles every 64 ms • Standard and Low-Power “L” versions • Gold contact pad, JEDEC MO-190 outline dimensions • This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical specifications • The -7.5 (PC133-333) module version is fully backward compatible to PC100-222 operation • Importante Notice: This SO-DIMM module is based on 256Mbit SDRAM technology and can be used in applications only, where 256Mbit addressing is supported. INFINEON Technologies 1 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules This INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use 256Mbit SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint. Product Spectrum: Speed HYS64V32220GD-7.5-C2 HYS64V32220GD-8-C2 32M x 64 HYS64V32220GDL-7.5-C2 HYS64V32220GDL-8-C2 SDRAMs used PC133-333 PC100-222 8 16Mx16 PC133-333 PC100-222 RowAddr. Bank Select 13 BA0, BA1 Column Refresh Addr. Period 8k 9 7,8 µs Note: All partnumbers end with a place code, designating the die revision. Example: HYS64V32220GD-8-C2, indicating Rev.C2 dies are used for SDRAM components. Card Dimensions: Organisation 32M x 64 PCB-Board INTEL Rev. 1.0/1.2 L x H x T [mm] 67.60 x 31.75 x 3.80 Pin Names A0-A11 Address Inputs DQMB0 -DQMB7 Data Mask BA0,BA1 Bank Selects CS0, CS1 Chip Select DQ0 - DQ63 Data Input/Output Vcc Power (+3.3 Volt) RAS Row Address Strobe Vss Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read / Write Input SDA Serial Data Out for Presence Detect CKE0, CKE1 Clock Enable N.C. No Connection CLK0, CLK1 Clock Input INFINEON Technologies 2 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules Pin Configuration Front Side PIN # Back Side PIN # Front Side PIN # Back Side PIN # 1 VSS 2 VSS 73 NC 3 DQ0 4 DQ32 75 Vss 76 Vss 5 DQ1 6 DQ33 77 NC 78 NC 7 DQ2 8 DQ34 79 NC 80 NC 9 DQ3 10 DQ35 81 Vcc 82 Vcc 11 VCC 12 Vcc 83 DQ16 84 DQ48 13 DQ4 14 DQ36 85 DQ17 86 DQ49 15 DQ5 16 DQ37 87 DQ18 88 DQ50 17 DQ6 18 DQ38 89 DQ19 90 DQ51 19 DQ7 20 DQ39 91 Vss 92 Vss 21 Vss 22 Vss 93 DQ20 94 DQ52 23 DQMB0 24 DQMB4 95 DQ21 96 DQ53 25 DQMB1 26 DQMB5 97 DQ22 98 DQ54 27 Vcc 28 Vcc 99 DQ23 100 DQ55 29 A0 30 A3 101 Vcc 102 Vcc 31 A1 32 A4 103 A6 104 A7 33 A2 34 A5 105 A8 106 BA0 35 Vss 36 Vss 107 Vss 108 Vss 37 DQ8 38 DQ40 109 A9 110 BA1 39 DQ9 40 DQ41 111 A10 112 A11 41 DQ10 42 DQ42 113 Vcc 114 Vcc 43 DQ11 44 DQ43 115 DQMB2 116 DQMB6 45 Vcc 46 Vcc 117 DQMB3 118 DQMB7 47 DQ12 48 DQ44 119 Vss 120 Vss 49 DQ13 50 DQ45 121 DQ24 122 DQ56 51 DQ14 52 DQ46 123 DQ25 124 DQ57 53 DQ15 54 DQ47 125 DQ26 126 DQ58 55 Vss 56 Vss 127 DQ27 128 DQ59 57 NC 58 NC 129 Vcc 130 Vcc 59 NC 60 NC 131 DQ28 132 DQ60 61 CLK0 62 CKE0 133 DQ29 134 DQ61 63 Vcc 64 Vcc 135 DQ30 136 DQ62 65 RAS 66 CAS 137 DQ31 138 DQ63 67 WE 68 CKE1 139 Vss 140 Vss 69 CS0 70 A12 141 SDA 142 SCL 71 CS1 72 N.C 143 Vcc 144 Vcc INFINEON Technologies 3 74 CLK1 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules WE CS0 CS1 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 UDQM DQ8-DQ15 D4 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1 UDQM DQ8-DQ15 D5 A0-A12, BA0, BA1 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 UDQM DQ8-DQ15 D6 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 UDQM DQ8-DQ15 D7 D0-D7 VC C E 2 PROM (256 word x 8 Bit) D0-D7 C VS S D0-D7 RAS D0-D7 CAS D0-D7 CKE0 D0-D7 CLK0 D0-D3 CLK1 D4-D7 SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω SPB04134_256M Block Diagram for two bank 32M x 64 SDRAM DIMM - Module INFINEON Technologies 4 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules DC Characteristics TA = 0 to 70 ×C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input high voltage VIH 2.0 Vcc+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 20 20 mA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 20 20 mA Capacitance TA = 0 to 70 ×C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit 32M x 64 max. Input capacitance (A0 to A11, BA0, BA1) CI1 52 pF Input capacitance (RAS, CAS, WE, CKE0) CI2 46 pF Input Capacitance (CLK0, CLK1) CI3 35 pF Input capacitance (CS0) CI4 30 pF Input capacitance (DQMB0-DQMB7) CI5 15 pF Input / Output capacitance (DQ0-DQ63) CIO 18 pF Input Capacitance (SCL,SA0-2) Csc 8 pF Input/Output Capacitance Csd 10 pF INFINEON Technologies 5 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules Operating Currents per memory bank (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -7.5 -8 ICC1 920 680 Note OPERATING CURRENT trc=trcmin., All banks operated in random access, all banks operated in ping-pong manner 8 PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) tck = min. ICC2P PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) tck = min. ICC2N 160 NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 200 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P BURST OPERATING CURRENT tck = min., Read command cycling ICC4 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling ICC5 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V, tck = infinity. “non-L”-versions L-versions ICC6 mA 1 120 mA 1 180 mA 1 mA 1 mA 1,2 mA 1 mA 1 40 600 mA 1, 2 400 960 880 12 7.2 Notes: 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5 and at 100 MHz for -8 modules. Input signals are changed once during tck. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. INFINEON Technologies 6 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules AC Characteristics 1)2) TA = 0 to 70 ×C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol -7.5 PC133 333 min. Unit -8 PC100 222 max. min. max. Clock and Access Time Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 7.5 12 – – 10 – – ns ns CAS Latency = 3 tCK CAS Latency = 2 – – 133 100 – – 100 100 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 – – 5.4 6 – – 6 6 ns ns Clock Frequency MHz MHz 2, 3 Clock High Pulse Width tCH 2.5 – 3 – ns Clock Low Pulse Width tCL 2.5 – 3 – ns Transition time tT 0.5 7.5 0.5 10 ns Input Setup Time tIS 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 1 – ns 4 Power Down Mode Entry Time tSB 1 – 1 – CLK 4 Power Down Mode Exit Setup Time tPDE 1 – 1 – CLK 4 Mode Register Set-up time tRSC 2 – 2 – CLK Row to Column Delay Time tRCD 20 20 – ns 5 Row Precharge Time tRP 20 20 – ns 5 Row Active Time tRAS 45 45 100k ns 5 Row Cycle Time tRC 67.5 70 – ns 5 Activate(a) to Activate(b) Command period tRRD 15 16 – ns 5 CAS(a) to CAS(b) Command period tCCD 1 1 Setup and Hold Parameter Common Parameters INFINEON Technologies 7 100k CLK 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules Parameter Limit Values Symbol -7.5 PC133 333 Unit -8 PC100 222 min. max. min. max. Refresh Cycle Refresh Period (8192 cycles) tREF – 64 – 64 ms Self Refresh Exit Time tSREX 1 – 1 – CLK 6 Data Out Hold Time tOH 3 – 3 – ns Data Out to Low Impedance Time tLZ 0 – 0 – ns Data Out to High Impedance Time tHZ 3 7 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 CLK Read Cycle 2, 7 Write Cycle Data Input to Precharge (write recovery) tWR – 2 – CLK DQM Write Mask Latency tDQW – 0 – CLK INFINEON Technologies 8 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules Notes: 1. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. . t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD 1.4 V INPUT t AC t LZ t AC t OH I/O OUTPUT 1.4 V t HZ 50 pF Measurement conditions for tac and toh SPT03404 3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to “wake-up“ the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. INFINEON Technologies 9 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules Serial Presence Detects: A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table: Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description SPD Entry Value Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 13 9 2 64 0 LVTTL 7.5 / 10.0 ns 5.4 / 6.0 ns SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time INFINEON Technologies 10 Hex 32Mx64 32Mx64 -7.5 -8 80 08 04 0D 09 02 40 00 01 75 54 A0 60 none Self-Refresh, 7.8 µs 00 82 x16 n/a tccd = 1 CLK 10 00 01 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 10 ns 6.0 ns 0F 04 06 01 01 00 0E A0 60 not supported not supported FF FF 20 ns 14 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules SPD-Table (cont’d): Byte# Description 28 Minimum Row Active to Row Active delay 29 Minimum RAS to CAS delay 30 Minimum Ras pulse width 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures’s information (optional) 125 126 Frequency Specification 127 Details 128+ Unused storage locations INFINEON Technologies 11 SPD Entry Value Hex 15 / 16 ns 32Mx64 32Mx64 -7.5 -8 0F 10 20 ns 45 / 60 ns 128MB 1.5 / 2 ns 0.8 / 1 ns 1.5 / 2 ns 0.8 / 1 ns 14 2D 32 20 15 08 15 08 20 10 20 10 FF 12 Revision 1.2 1E 81 FF 64 C7 FF 3.01 HYS64V32220GD(L) 256MB 144 pin SO-DIMM SDRAM Modules 256 MByte SO-DIMM Module package (JEDEC MO-190) (144 pin, dual read-out, single in-line memory module) 67,6 63,6 31.75 3.8 3.3 1 23.2 59 61 32.8 143 1 ± 0.1 2.6 1.5 ±0.1 3.7 2 60 1.8 62 144 4 20 6 4 ±0.1 4.6 2.54 min. 0.25 max. Detail of Contacts 0.6 ±0.05 0.8 GLD09138 note: all tolerances are in accordance with the JEDEC standard INFINEON Technologies 12 3.01 Attention please ! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. This infomation describes the type of components and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact INFINEON Technologies Offices in Munich or the INFINEON Technologies Sales Offices and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest INFINEON Technologies office or representative. Packing Please use the recycling operators known to you. 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