ICS ICS83948AYIT

ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83948I is a low skew, 1-to-12 Differential-to-LVCMOS Fanout Buffer and a member
HiPerClockS™ of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83948I has
two selectable clock inputs. The CLK, nCLK
pair can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
• Twelve LVCMOS outputs
ICS
The ICS83948I is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics
make the ICS83948I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
• Selectable LVCMOS clock or differential CLK, nCLK inputs
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 350ps (maximum)
• Part to part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
Q3
32 31 30 29 28 27 26 25
Q0
Q1
CLK_SEL
VDDO
0
Q2
CLK
nCLK
GND
1
Q1
LVCMOS_CLK
VDDO
Q
LE
Q0
GND
D
CLK_EN
Q2
Q3
Q4
CLK_SEL
1
24
GND
LVCMOS_CLK
2
23
Q4
CLK
3
22
VDDO
nCLK
4
21
Q5
CLK_EN
5
20
GND
OE
6
19
Q6
VDD
7
18
VDDO
GND
8
17
Q7
Q5
ICS83948I
9 10 11 12 13 14 15 16
GND
Q8
VDDO
Q9
GND
Q10
Q7
VDDO
Q11
Q6
Q8
Q9
Q10
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
Q11
OE
83948AYI
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1
REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
CLK_SEL
2
LVCMOS_CLK
Input
Pullup
Description
Clock select input. Selects LVCMOS clock input
when HIGH. Selects CLK, nCLK inputs when LOW.
LVCMOS / LVTTL interface levels.
Clock input. LVCMOS / LVTTL interface levels.
3
CLK
Input
Pullup
Non-inver ting differential clock input.
4
nCLK
Input
5
CLK_EN
Input
Pullup
Clock enable. LVCMOS / LVTTL interface levels.
6
OE
Input
Pullup
Output enable. LVCMOS / LVTTL interface levels.
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
10, 14, 18, 22, 26, 30
VDD
Power
Positive supply pin.
GND
Power
Power supply ground.
Output
Clock outputs. LVCMOS / LVTTL interface levels.
Power
Output supply pins.
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
VDDO
Input
Pullup
Pulldown Inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
4
pF
25
pF
RPULLUP
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
7
Ω
CPD
Test Conditions
Minimum
Typical
Maximum
Units
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK, nCLK
LVCMOS_CLK
0
Selected
De-selected
1
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
Differential to Single Ended
Non Inver ting
CLK_SEL
LVCMOS_CLK
CLK
nCLK
Q0:Q12
0
—
0
1
LOW
0
—
1
0
HIGH
Differential to Single Ended
Non Inver ting
0
—
0
Biased; NOTE 1
LOW
Single Ended to Single Ended
Non Inver ting
0
—
1
Biased; NOTE 1
HIGH
Single Ended to Single Ended
Non Inver ting
0
—
Biased; NOTE 1
0
HIGH
Single Ended to Single Ended
Inver ting
0
—
Biased; NOTE 1
1
LOW
Single Ended to Single Ended
Inver ting
1
0
—
—
LOW
Single Ended to Single Ended
Non Inver ting
1
1
—
—
HIGH
Single Ended to Single Ended
Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83948AYI
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2
REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter
Minimum
Typical
Maximum
Units
Positive Supply Voltage
3.0
3.3
3.6
V
VDDO
Output Supply Voltage
3.0
3.3
3.6
V
IDD
Power Supply Current
55
mA
VDD
Test Conditions
TABLE 4B. DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter
Maximum
Units
VIH
Input High Voltage
Test Conditions
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0. 8
V
0.15
1.3
V
GND + 0.5
VDD - 0.85
V
±100
µA
VPP
Peak-to-Peak Input Voltage
VCMR
Input Common Mode Voltage; NOTE 1, 2
IIN
Input Current
VOH
Output High Voltage
Minimum
IOH = -20mA
Typical
2.5
Output Low Voltage
IOL = 20mA
VOL
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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3
V
0.4
V
REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter
fMAX
Output Frequency
tPD
Propagation Delay
CLK, nCLK;
NOTE 1A
LVCMOS_CLK;
NOTE 1B
Test Conditions
Minimum
f ≤ 150MHz
f ≤ 150MHz
Maximum
250
Units
MHz
2.25
3.75
ns
2
4
ns
350
ps
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 2, 6
tsk(pp)
Par t-to-Par t Skew;
NOTE 3, 6
tR
tF
Output Rise Time
Output Fall Time
0.8V to 2V
0.8V to 2V
tPW
Output Pulse Width
f < 150MHz
tPZL, tPZH
Output Disable Time; NOTE 4
CLK, nCLK
LVCMOS_CLK
Typical
1.5
ns
0.2
0.2
2
1.0
1.0
ns
ns
ns
tCycle/2 - 800
tCycle/2 + 800
ps
Measured on
rising edge @VDDO/2
11
tPLZ, tPHZ
Output Enable Time; NOTE 4
11
CLK_EN to
1
Clock Enable
CLK, nCLK
Setup Time;
tS
CLK_EN to
NOTE 5
0
LVCMOS_CLK
CLK, nCLK to
1
Clock Enable
CLK_EN
tH
Hold Time;
LVCMOS_CLK
NOTE 5
1
to CLK_EN
NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 1B: Measured from the VDD/2 or crosspoint of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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4
ns
ns
ns
ns
ns
ns
REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±0.15V
V DD
SCOPE
VDD,
VDDO
nCLK
Qx
LVCMOS
V
Cross Points
PP
V
CMR
CLK
GND
GND = -1.65V±0.15V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
Qx
VDDO
2
Qx
DDO
2
PART 2
Qy
VDDO
2
Qy
V
V
DDO
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
2V
2V
Clock
Outputs
0.8V
0.8V
tR
LVCMOS_
CLK
tF
VDDO
2
nCLK
CLK
OUTPUT RISE/FALL TIME
Q0:Q11
VDDO
VDDO
VDDO
2
2
2
t PW
VDDO
2
Q0:Q11
tPD
➤
➤
t PERIOD
odc =
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83948AYI
PROPAGATION DELAY
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5
REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
C1
0.1uF
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
83948AYI
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REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83948I is: 1040
Pin compatible with the MPC948/948L
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REV. C DECEMBER 15, 2005
ICS83948I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
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REV. C DECEMBER 15, 2005
Integrated
Circuit
Systems, Inc.
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS83948AYI
ICS83948AYI
32 Lead LQFP
tray
0°C to 70°C
ICS83948AYIT
ICS83948AYI
32 Lead LQFP
1000 tape & reel
0°C to 70°C
ICS83948AYILF
ICS83948AYIL
32 Lead "Lead-Free" LQFP
tray
0°C to 70°C
ICS83948AYILFT
ICS83948AYIL
32 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83948AYI
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9
REV. C DECEMBER 15, 2005
Integrated
Circuit
Systems, Inc.
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
T5
Page
4
B
T5
4
B
T5
4
B
T5
4
1
2
6
B
C
T2
T8
83948AYI
9
Description of Change
Date
AC Characteristics table - tLZ, tHZ row changed symbol to read tPLZ, tPHZ and
changed Parameter to read Output Enable Time.
Added rows: tS "Clock Enable Setup Time" and tH "Clock Enable Hold Time".
AC Characteristics table, tS and tH rows - replaced SYNC_OE with CLK_EN.
Added an extra note to Propagation Delay row.
AC Characteristics table, fMAX row corrected typo error of 150MHz to 250MHz.
AC Characteristics table - tPW row, added f< 150MHz for tPW Test Conditions.
Features Section - added Lead-Free bullet.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added Recommendations for Unused Output Pins.
Ordering Information Table - added Lead-Free par t number, marking and note.
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10
05/20/02
6/26/02
8/8/02
11/11/02
12/15/05
REV. C DECEMBER 15, 2005