ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. Internal bias on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • 4 LVCMOS/LVTTL outputs, 7Ω typical output impedance ICS • Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 inputs • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Fully integrated PLL • Cycle-to-cycle jitter: 45ps (maximum) • Output skew: 45ps (maximum) • Static phase offset: 50 ± 125ps (3.3V ± 5%) • Full 3.3V or 2.5V operating supply • 5V tolerant inputs • Lead-Free package available • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT PLL_SEL CLK0 nCLK0 ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128 Q0 0 0 Q1 1 CLK1 nCLK1 1 PLL Q2 CLK_SEL FB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Q3 GND Q0 VDD o SEL0 SEL1 SEL2 SEL3 CLK_SEL VDD CLK0 nCLK0 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q1 VDDO Q2 GND Q3 VDDO MR FB_IN PLL_SEL CLK1 nCLK1 VDDA 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm G Package Top View SEL0 SEL1 SEL2 SEL3 MR 87004AG www.icst.com/products/hiperclocks.html 1 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 12, 21 GND Q0, Q3, Q2, Q1 VDDO SEL0, SEL1, SEL2, SEL3 2, 20, 22, 24 3, 19, 23 4, 5, 6, 7 8 Type Power Output Power Input CLK_SEL Input 9 VDD Power 10 CLK0 Input Description Power supply ground. Clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. Output supply pins. Determines output divider values in Table 3. Pulldown LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects differential CLK1, nCLK1. Pulldown When LOW, selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels. Core supply pin. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. 11 nCLK0 Input Pulldown 13 VDDA Power Analog supply pin. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. 14 nCLK1 Input Pulldown 15 CLK1 Input Pulldown Non-inver ting differential clock input. Selects between the PLL and reference clock as input to the dividers. 16 PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. LVCMOS/LVTTL feedback input to phase detector for regenerating 17 FB_IN Input Pulldown clocks with "zero delay". Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 18 MR Input Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CPD Power Dissipation Capacitance (per output) ROUT Output Impedance 87004AG Test Conditions Minimum Typical Maximum Units VDD, VDDA, VDDO = 3.465V 23 pF VDD, VDDA, VDDO = 2.625V 17 pF 12 Ω 5 www.icst.com/products/hiperclocks.html 2 7 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR TABLE 3A. PLL ENABLE FUNCTION TABLE SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q3 0 0 0 0 125 - 250 ÷1 Inputs 0 0 0 1 62.5 - 125 ÷1 0 0 1 0 31.25 - 62.5 ÷1 0 0 1 1 15.625 -31.25 ÷1 0 1 0 0 125 - 250 ÷2 0 1 0 1 62.5 - 125 ÷2 0 1 1 0 31.25 - 62.5 ÷2 0 1 1 1 125 - 250 ÷4 1 0 0 0 62.5 - 125 ÷4 1 0 0 1 125 - 250 ÷8 1 0 1 0 62.5 - 125 x2 1 0 1 1 31.25 - 62.5 x2 1 1 0 0 15.625 - 31.25 x2 1 1 0 1 31.25 - 62.5 x4 1 1 1 0 15.625 - 31.25 x4 1 1 1 1 15.625 - 31.25 x8 TABLE 3B. PLL BYPASS FUNCTION TABLE SEL3 SEL2 SEL1 S E L0 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q3 0 0 0 0 ÷8 0 0 0 1 ÷8 Inputs 87004AG 0 0 1 0 ÷8 0 0 1 1 ÷ 16 0 1 0 0 ÷ 16 0 1 0 1 ÷ 16 0 1 1 0 ÷ 32 0 1 1 1 ÷ 32 1 0 0 0 ÷ 64 1 0 0 1 ÷ 128 1 0 1 0 ÷4 1 0 1 1 ÷4 1 1 0 0 ÷8 1 1 0 1 ÷2 1 1 1 0 ÷4 1 1 1 1 ÷2 www.icst.com/products/hiperclocks.html 3 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VDD Core Supply Voltage Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 6 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK_SEL, MR, FB_IN, SEL0, SEL1, SEL2, SEL3 IIL VOH Output High Voltage; NOTE 1 Units 2 VDD + 0.3 V -0.3 0.8 V 150 µA 5 µA VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = VIN = 2.625V CLK_SEL, MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL Maximum VDD = VIN = 3.465V, PLL_SEL Input Low Current Minimum Typical VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V -5 µA -150 µA VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams. 87004AG www.icst.com/products/hiperclocks.html 4 0.5 V REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH IIL Test Conditions Minimum Typical Maximum Units CLK0, CLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V 150 µA nCLK0, nCLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V 150 µA Input High Current CLK0, CLK1 VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V -5 µA nCLK0, nCLK1 VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V -150 µA Input Low Current V PP Peak-to-Peak Input Voltage 0.15 1.3 Common Mode Input Voltage; GND + 0.5 VDD - 0.85 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. V V TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 96 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 6 mA 87004AG Test Conditions www.icst.com/products/hiperclocks.html 5 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units fMAX tjit(cc) Output Frequency Propagation Delay, CLK0, nCLK0 NOTE 1 CLK1, nCLK1 Static Phase Offset; CLK0, nCLK0 NOTE 2, 4 CLK1, nCLK1 Output Skew; CLK0, nCLK0 NOTE 3, 4 CLK1, nCLK1 Cycle-to-Cycle Jitter ; NOTE 4 15.625 250 MHz 5 6 ns 50 175 ps PLL_SEL = 0V 40 50 ps tL PLL Lock Time fOUT > 40MHz 30 45 ps 1 ms 800 ps odc Output Duty Cycle 40 50 60 NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. tR / tF Output Rise/Fall Time % tPD t(Ø) tsk(o) Test Conditions PLL_SEL = 0V f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 3.3V fREF ≤ 167MHz, Qx ÷ 1 20% to 80% Minimum -75 Typical 400 TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX tjit(cc) Output Frequency Propagation Delay, CLK0, nCLK0 NOTE 1 CLK1, nCLK1 Static Phase Offset; CLK0, nCLK0 NOTE 2, 4 CLK1, nCLK1 Output Skew; CLK0, nCLK0 NOTE 3, 4 CLK1, nCLK1 Cycle-to-Cycle Jitter ; NOTE 4 Maximum Units 15.625 250 MHz 5.3 6.7 ns -25 125 ps PLL_SEL = 0V 40 45 ps tL PLL Lock Time fOUT > 40MHz 35 45 ps 1 ms tR / tF Output Rise/Fall Time 700 ps odc Output Duty Cycle 44 50 56 NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % tPD t(Ø) tsk(o) 87004AG Test Conditions PLL_SEL = 0V f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 2.5V fREF ≤ 167MHz, Qx ÷ 1 20% to 80% www.icst.com/products/hiperclocks.html 6 Minimum -175 400 Typical REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDA, VDDO Qx LVCMOS SCOPE VDD, VDDA, VDDO Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT V DD V DDO Qx nCLK0, nCLK1 V V Cross Points PP 2 CMR V CLK0, CLK1 DDO Qy 2 t sk(o) GND DIFFERENTIAL INPUT LEVEL OUTPUT SKEW V V DDO Q0:Q3 V DDO 2 DDO 2 n ➤ tcycle ➤ 80% 80% tR tF 2 tcycle n+1 ➤ Clock Outputs 20% 20% ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER 87004AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 VOH VOL CLK0, CLK1 VOH VDDO 2 VOL FB_IN ➤ ➤ t (Ø) Q0:Q3 VDDO 2 t PD t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) STATIC PHASE OFFSET Q0:Q3 PROPAGATION DELAY VDDO VDDO VDDO 2 2 2 t PW t PERIOD odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 87004AG www.icst.com/products/hiperclocks.html 8 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA. 3.3V VDD .01µF 10Ω VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87004AG www.icst.com/products/hiperclocks.html 9 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 87004AG nCLK Zo = 50 Ohm BY FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 10 BY REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70°C/W 63°C/W 60°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87004 is: 2578 87004AG www.icst.com/products/hiperclocks.html 11 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 87004AG www.icst.com/products/hiperclocks.html 12 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87004AG ICS87004AG 24 Lead TSSOP 60 per tube 0°C to 70°C ICS87004AGT ICS87004AG 24 Lead TSSOP on Tape and Reel 2500 0°C to 70°C ICS87004AG ICS87004AG 24 Lead "Lead Free" TSSOP 60 per tube 0°C to 70°C ICS87004AGT ICS87004AG 24 Lead "Lead Free" TSSOP on Tape and Reel 2500 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87004AG www.icst.com/products/hiperclocks.html 13 REV. A JUNE 16, 2004 ICS87004 Integrated Circuit Systems, Inc. 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page A T8 13 87004AG Description of Change Ordering Information table - added "Lead-Free" par t number. www.icst.com/products/hiperclocks.html 14 Date 6/16/04 REV. A JUNE 16, 2004