ICS87951I-147 LOW SKEW, 1-TO-9 DIFFERENTIAL-TOLVCMOS ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS87951I-147 is a low voltage, low skew 1ICS to-9 Differential-to-LVCMOS/LVTTL Zero Delay HiPerClockS™ Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS87951I-147 has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the ICS87951I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87951I147 contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. • Fully integrated PLL • Nine single ended 3.3V or 2.5V LVCMOS/LVTTL outputs • Selectable single ended CLK0 or differential CLK1, nCLK1 inputs • The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels • CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 200MHz • VCO range: 250MHz to 500MHz • External feedback for ”zero delay” clock regeneration • Cycle-to-cycle jitter, RMS: 7ps (maximum) • Output skew: 270ps (maximum) • Full 3.3V operating supply at -40°C to 85°C ambient operating temperature • Full 2.5V operating supply at 0°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages PIN ASSIGNMENT GND QB VDDO QA GND CLK0 PLL_SEL CLK_SEL 32 31 30 29 28 27 26 25 VDDA 1 24 EXT_FB 2 23 VDDO DIV_SELA 3 22 QC1 21 GND 20 QD0 QC0 DIV_SELB 4 DIV_SELC 5 DIV_SELD 6 19 VDDO GND 7 18 QD1 CLK1 8 17 GND ICS87951I-147 9 10 11 12 13 14 15 16 QD2 VDDO QD3 GND QD4 VDDO MR/nOE nCLK1 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 1 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER BLOCK DIAGRAM DIV_SELA Internal Pulldown PLL_SEL Internal Pulldown CLK0 Internal Pulldown CLK_SEL nCLK1 CLK1 Internal Pulldown Internal Pulldown/ Pullup 1 0 ÷2 PHASE DETECTOR VCO 250-500MHz 0 1 0 QA ÷4 ÷8 1 0 LPF QB 1 EXT_FB Internal Pullup DIV_SELB Internal Pulldown 0 QC0 1 QC1 DIV_SELC Internal Pulldown MR/nOE Internal Pulldown POWER-ON RESET QD0 0 QD1 1 QD2 QD3 DIV_SELD Internal Pulldown QD4 IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 2 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power 2 EXT_FB Input Pullup 3 DIV_SELA Input Pulldown 4 DIV_SELB Input Pulldown 5 DIV_SELC Input Pulldown 6 DIV_SELD Input Pulldown 7, 13, 17, 21, 25, 29 GND Power 8 CLK1 Input 9 nCLK1 Input Pulldown Inver ting differential clock input. MR/nOE Input Active High Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated Pulldown (HiZ). When logic LOW, the internal dividers and outputs are enabled. LVCMOS / LVTTL interface levels. 10 Type 11, 15, 19, 23, 27 12, 14, 16, 18, 20 VDDO Power QD4, QD3, QD2, QD1, QD0 Output 22, 24 QC1, QC0 Output 26 QB Output 28 QA Output 30 CLK0 Input 31 PLL_SEL Input 32 CLK_SEL Input Description Analog supply pin. Feedback input to phase detector for regenerating clocks with "zero delay". LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank C outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank D outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Power supply ground. Pullup Non-inver ting differential clock input. Output supply pins. Bank D clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank B clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank A clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL phase detector reference clock input. Selects between the PLL and the reference clock as the input to the Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK0. When LOW, Pulldown selects CLK1, nCLK1. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF VDDA, VDDO = 3.465V 25 pF VDDA, VDDO = 2.625V CPD Power Dissipation Capacitance (per output) 15 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 3 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Input Outputs MR/nOE QA QB QC0, QC1 QD0:QD4 1 HiZ HiZ HiZ HiZ 0 Enabled Enabled Enabled Enabled TABLE 3B. OPERATING MODE FUNCTION TABLE Input PLL_SEL TABLE 3C. PLL INPUT FUNCTION TABLE Inputs Operating Mode CLK_SEL PLL Input 0 Bypass 0 CLK1, nCLK1 1 PLL 1 CLK0 TABLE 3D. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE Inputs Outputs DIV_SELA DIV_SELB DIV_SELC DIV_SELD QA QB QCx QDx 0 0 0 0 VCO/2 VCO/4 VCO/4 VCO/4 0 0 0 1 VCO/2 VCO/4 VCO/4 VCO/8 0 0 1 0 VCO/2 VCO/4 VCO/8 VCO/4 0 0 1 1 VCO/2 VCO/4 VCO/8 VCO/8 0 1 0 0 VCO/2 VCO/8 VCO/4 VCO/4 0 1 0 1 VCO/2 VCO/8 VCO/4 VCO/8 0 1 1 0 VCO/2 VCO/8 VCO/8 VCO/4 0 1 1 1 VCO/2 VCO/8 VCO/8 VCO/8 1 0 0 0 VCO/4 VCO/4 VCO/4 VCO/4 1 0 0 1 VCO/4 VCO/4 VCO/4 VCO/8 1 0 1 0 VCO/4 VCO/4 VCO/8 VCO/4 1 0 1 1 VCO/4 VCO/4 VCO/8 VCO/8 1 1 0 0 VCO/4 VCO/8 VCO/4 VCO/4 1 1 0 1 VCO/4 VCO/8 VCO/4 VCO/8 1 1 1 0 VCO/4 VCO/8 VCO/8 VCO/4 1 1 1 1 VCO/4 VCO/8 VCO/8 VCO/8 IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 4 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDDA + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 42.1°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3. 3 3.465 V IDDO Power Supply Current 115 mA IDDA Analog Supply Current 20 mA All VDD pins TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 2.5V±5%, TA = 0°C TO 85°C Symbol Parameter VDDA Analog Supply Voltage Test Conditions VDDO Output Supply Voltage IDDO Power Supply Current IDDA Analog Supply Current Minimum Typical Maximum Units 2.375 2. 5 2.625 V 2.375 2.5 2.625 V 75 mA 12 mA All VDD pins TABLE 4C. DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIN VPP VCMR VOH VOL Test Conditions Maximum Units 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V ±120 µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V IOL = 40mA 0.55 V IOL = 12mA 0.3 V DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL CLK0 Input Current Peak-to-Peak CLK1, nCLK1 Input Voltage Common Mode Input Voltage; CLK1, nCLK1 NOTE 1, 2 Output High Voltage Output Low Voltage IOH = -40mA Minimum Typical 2.4 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is VDDA+ 0.3V. IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 5 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER TABLE 4D. DC CHARACTERISTICS, VDDA = VDDO = 2.5V±5%, TA = 0°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIN VPP VCMR Test Conditions DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL CLK0 Input Current Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V -0.3 0.8 V ±150 µA CLK1, nCLK1 0.15 1.3 V CLK1, nCLK1 GND + 0.5 VDD - 0.85 V VOH Output High Voltage IOH = -15mA VOL Output Low Voltage IOL = 15mA 1.8 V 0.6 V Maximum Units 250 MHz Maximum Units 250 MHz Qx ÷4 125 MHz QB, QC, QD ÷8 62.5 MHz 250 500 MHz -135 170 ps -420 -100 ps 270 ps 7.5 ps 10 mS 30 0 800 ps 46 54 % NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is VDDA+ 0.3V. TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fREF Input Reference Frequency Test Conditions Minimum Typical TABLE 6A. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum QA ÷2 fMAX fVCO t(Ø) tsk(o) tjit(cc) tLOCK Output Frequency PLL VCO Lock Range CLK0 Static Phase Offset; CLK1, NOTE 1,3 nCLK1 Output Skew; NOTE 2, 3 Cycle-to-Cycle Jitter, RMS; NOTE 3 PLL Lock Time; NOTE 3 fREF = 50MHz, Feedback = VCO/8 All Outputs @ Same Frequency Typical tR / tF Output Rise/Fall Time odc Output Duty Cycle tPZL Output Enable Time 6 ns tPLZ, tPHZ Output Disable Time 7 ns 20% to 80% All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 6 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER TABLE 6B. AC CHARACTERISTICS, VDDA = VDDO = 2.5V±5%, TA = 0°C TO 85°C Symbol fMAX fVCO Parameter Test Conditions Maximum Units QA ÷2 200 MHz Qx ÷4 120 MHz QB, QC, QD ÷8 60 MH z Output Frequency Minimum Typical PLL VCO Lock Range 250 500 MHz -180 220 ps -500 -165 ps 310 ps 9 ps tLOCK CLK0 Static Phase Offset; C LK1, NOTE 1,3 nCLK1 Output Skew; NOTE 2, 3 Cycle-to-Cycle Jitter, RMS; NOTE 3 PLL Lock Time; NOTE 3 10 mS 300 700 ps 46 54 % t(Ø) tsk(o) tjit(cc) FVCO ≤ 400MHz, All Outputs @ same frequency tR / tF Output Rise/Fall Time o dc Output Duty Cycle tPZL Output Enable Time 6 ns tPLZ, tPHZ Output Disable Time 7 ns 20% to 80% All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 7 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDDA, VDDO Qx LVCMOS SCOPE VDDA, VDDO Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT VDD V DDO Qx nCLK1 V V Cross Points PP 2 CMR V CLK1 DDO Qy 2 t sk(o) GND DIFFERENTIAL INPUT LEVEL V V V DDO DDO 2 DDO 2 ➤ QA, QB, QCx, QDx OUTPUT SKEW ➤ tcycle n tcycle n+1 80% 80% 2 ➤ Clock Outputs ➤ t jit(cc) = tcycle n –tcycle n+1 20% 20% tR tF 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME nCLK1 CLK0, CLK1 V DDO 2 VDD t PW t odc = 2 EXT_FB PERIOD t PW ➤ t (Ø) ➤ QAx, QBx, QCx, QDx tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter x 100% t (Ø) mean = Static Phase Offset t PERIOD (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER PHASE JITTER AND STATIC PHASE OFFSET 8 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87951I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DDA, and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 3.3V or 2.5V VDDO .01µF 10Ω VDDA .01µF 10µF FIGURE 2. POWER SUPPLY FILTERING 9 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. There should be no trace attached. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 LVPECL HiPerClockS Input R1 50 R2 50 HiPerClockS Input R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 10 BY ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87951I-147 is: 2674 Pin compatible with the MPC951 IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 11 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 12 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS87951AYI-147 ICS87951AYI-147 32 Lead LQFP tray -40°C to 85°C ICS87951AYI-147T ICS87951AYI-147 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS87951AYI-147LF ICS951AI147L 32 Lead "Lead-Free" LQFP tray -40°C to 85°C ICS87951AYI-147LFT ICS951AI147L 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 13 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER REVISION HISTORY SHEET Rev A A Table T9 T9 Page 1 13 10 13 Description of Change Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free par t number and note. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected standard marking and added lead-free marking. IDT ™ / ICS™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 14 Date 6/14/05 6/21/06 ICS87951I-147 REV A JUNE 21, 2006 ICS87951I-147 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA