Integrated Circuit Systems, Inc. ICS9248-73 Frequency Timing Generator for Pentium II Systems General Description The ICS9248-73 is a single chip clock for Intel Pentium II. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-73 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Features Generates the following system clocks: - 2 - CPUs @ 2.5V , up to 150MHz. - 1 - IOAPIC @ 2.5V, PCI/2MHz. - 9 - SDRAMs @ 3.3V, up to 150MHz. - 2 - 3V66 @ 3.3V, 2x PCI MHz. - 8 - PCIs @ 3.3V. - 2 - 48MHz, @ 3.3V fixed. - 1 - REF @ 3.3V, 14.318MHz. - 1 - 24_48MHz, @ 3.3V fixed. Supports spread spectrum modulation , down spread 0 to -0.5%, ±0.25% center spread. I2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal Block Diagram Pin Configuration 48-Pin 300 mil SSOP *120K ohm pull-up to VDD on indicated inputs. **60K ohm pull-up to VDD on indicated inputs. 1. These pins will have 2x drive strength Power Groups Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9248-73 Rev B 2/10/00 GNDREF, VDDREF = REF & Crystal GND3V66, VDD3V66 = 3V66 GNDPCI, VDDPCI = PCICLK GNDCOR, VDDCOR = PLL core GND48, VDD48 = 48MHz GNDSDR, VDDSDR = SDRAM GNDLCPU, VDDLCPU = CPUCLK GNDAPIC, VDDAPIC = IOAPIC ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-73 Pin Descriptions PIN NUMBER 1 2, 9, 10, 18, 25, 30, 38 P I N NA M E TYPE DESCRIPTION SEL_3V66 REF0 IN OUT This pin selects the 3V66 output frequency. 3.3V, 14.318MHz reference clock output. VDD PWR 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) 3 X1 IN 4 X2 OUT GND PWR Ground pins for 3.3V supply 3V66 (0:1) OUT 3.3V clock outputs for HUB running at 2XPCI MHz PCICLK0 FS0 OUT IN 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. PCICLK1 OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS 5, 6, 14, 21, 29, 42, 34, 7, 8 11 12 13 15, 16, 17, 19, 20 FS1 PCICLK2 SEL24_48# PCICLK (3:7) IN OUT IN OUT Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input to select output. 3.3V PCI clock outputs, with Synchronous CPUCLKS 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input 24 SDATA IN Data input for I2C serial input. 48MHz OUT 26 27 28 FS3 IN 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B Logic input frequency select bit. Input latched at power on. 48MHz OUT 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B 24_48MHz OUT 24 or 48MHz output controlled by SEL24_48#. FS2 IN Logic input frequency select bit. Input latched at power on. 29 GND48 PWR Ground for 48MHz outputs 31 SDRAM_F OUT 3.3V free running 100MHz SDRAM not affected by I2C OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C GNDL PWR 45, 44 CPUCLK (0:1) OUT 47 48, 46 IOAPIC VDDL OUT PWR Ground for 2.5V power supply for CPU & APIC 2 . 5 V H o s t bu s c l o c k o u t p u t , u p t o 1 5 0 M H z d e p e n d i n g o n F S ( 0 : 3 ) pins Refer page 3. 2.5V clock outputs running at PCI/2 MHz. 2.5V power suypply for CPU, IOAPIC 41, 40, 39, 37, SDRAM (0:7) 36, 35, 33, 32, 43 2 ICS9248-73 Frequency Selection FS3 FS2 FS1 FS0 CPU SDRAM PCI MHz MHz MHz 3V66 MHz IOAPIC MHz SEL_3V66=0 SEL_3V66=1 0 0 0 0 100.23 100.23 33.41 66.82 66.82 16.70 0 0 0 1 100.90 100.90 33.63 67.26 67.26 16.81 0 0 1 0 105.00 105.00 35.00 70.00 70.00 17.50 0 0 1 1 66.89 100.33 33.44 66.89 66.89 16.72 0 1 0 0 120.00 120.00 40.00 64.00* 80.00 20.00 0 1 0 1 124.00 124.00 41.33 64.00* 82.66 20.67 0 1 1 0 133.30 133.30 44.43 64.00* 88.86 22.21 0 1 1 1 133.30 133.30 33.32 66.65 66.65 16.66 1 0 0 0 140.00 140.00 35.00 70.00 70.00 17.50 1 0 0 1 150.00 150.00 37.50 64.00* 75.00 18.75 1 0 1 0 114.99 114.99 38.33 64.00* 76.66 19.16 1 0 1 1 70.00 105.00 35.00 70.00 70.00 17.50 1 1 0 0 75.00 112.50 37.50 64.00* 75.00 18.75 1 1 0 1 83.31 124.96 41.65 64.00* 83.31 20.83 1 1 1 1 1 1 0 1 90.00 95.00 90.00 95.00 30.00 31.67 60.00 63.33 60.00 63.33 15.00 15.83 Note: * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation. Clock Enable Configuration PD # CPUCLK SD RAM IOAPIC 66M Hz PCICLK REF, 48M Hz Os c VCOs 0 LO W LO W LO W LO W LO W LO W O FF O FF 1 ON ON ON ON ON ON ON ON 3 ICS9248-73 Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) Description Bit Bit 7 0 - ±0.25% Center Sperad Spectrum 1-Down Spread Spectrum 0 to -0.5% Bit CPUCLK SDRAM PCICLK (2, 6:4) MH z MHz MHz Bit (2, 6:4) Bit 3 Bit 1 Bit 0 PWD 3V66 MHz 0 IOAPIC MHz 0000 0001 0010 0011 0100 0101 100.23 100.90 105.00 66.89 120.00 124.00 100.23 100.90 105.00 100.33 120.00 124.00 33.41 33.63 35.00 33.44 40.00 41.33 SEL_3V66=0 66.82 67.26 70.00 66.89 64.00* 64.00* SEL_3V66=1 66.82 67.26 70.00 66.89 80.00 82.66 16.70 16.81 17.50 16.72 20.00 20.67 0110 133.30 133.30 44.43 64.00* 88.86 22.21 0111 133.30 133.30 33.32 66.65 66.65 16.66 1000 140.00 140.00 35.00 70.00 70.00 17.50 1001 150.00 150.00 37.50 64.00* 75.00 18.75 1010 114.99 114.99 38.33 64.00* 76.66 19.16 1011 70.00 105.00 35.00 70.00 70.00 17.50 1100 75.00 112.50 37.50 64.00* 75.00 18.75 1101 83.31 124.96 41.65 64.00* 83.31 20.83 1110 90.00 90.00 30.00 60.00 60.00 15.00 63.33 15.83 1111 95.00 95.00 31.67 63.33 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 6:4 0 - Normal 1 - Spread spectrum enable 0 - Running 1 - Tristate all outputs Notes: 1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000. * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation. 4 XXXX Note 1 0 0 0 ICS9248-73 Byte 2: Control Register (1 = enable, 0 = disable) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 28 27 26 31 PWD X X X 1 1 1 0 1 Description FS3# FS0# FS2# 24-48MHz 48MHz 48MHz (Reserved) SDRAM_F Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 32 33 35 36 37 39 40 41 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 4: Control Register (1 = enable, 0 = disable) Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 7 8 47 44 45 PWD 0 1 1 X 1 X 1 1 Description (Reserved) 3V66_0 3V66_1 SEL_3V66# IOAPIC FS1# CPUCLK1 CPUCLK0 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 5 ICS9248-73 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time 1 Clk Stabilization Delay 1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD2.5OP 66 IDD2.5OP 100 IDD3.3P D CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 66MHz; Max discrete cap loads Select @ 100MHz; Max discrete cap loads Select @ 66MHz; Max discrete cap loads Select @ 100MHz; Max discrete cap loads CL = 0 pF; PWRDWN# = 0 MIN 2 VSS-0.3 -5 -200 TYP 0.1 2.0 -100 300 300 14 21 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 380 mA 70 100 mA 5 10 mA VDD = 3.3 V 12 14.318 16 MHz CIN CINX Logic Inputs X1 & X2 pins 27 36 5 45 pF pF TTrans To 1st crossing of target Freq. 3 ms 3 ms 3 10 10 ms ns ns Fi TS From 1st crossing to 1% target Freq. TStab tPZH, tPZH tPLZ, tPZH From VDD = 3.3 V to 1% target Freq. Output enable delay (all outputs) Output diable delay (all outputs) Guaranteed by design, not 100% tested in production. 6 1 1 1 ICS9248-73 Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current 19 TYP 2.36 0.33 -34 25 VOL = 0.4 V, VOH = 2.0 V 0.4 1.5 2 ns VOH = 2.0 V, VOL = 0.4 V 0.4 1.4 1.8 ns Duty Cycle d t2B1 VT = 1.25 V; Freq>= 140MHz VT = 1.25 V; Freq< 140MHz 40 43 48 48 50 53 % % Skew tsk2B1 VT = 1.25 V 50 175 ps VT = 1.25 V; CPU @ 66.8 MHz VT = 1.25 V; CPU @ 100.23 MHz 500 130 250 ps Rise Time tr2B 1 Fall Time tf2B1 Jitter, Cycle-to-cycle 1 SYMBOL VOH2B VOL2B IOH2B IOL2B tjcyc-cyc2B1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 MAX UNITS V 0.4 V -19 mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 25 TYP 3.1 0.18 -55 43 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.55 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.4 2 ns d t1 VT = 1.5 V 45 48 55 % Skew tsk1 VT = 1.5 V 50 175 ps Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1 tjcyc-cyc1 tjcyc-cyc1 Fall Time 1 Duty Cycle 1 1 1 VT = 1.5 V; 3V66 Freq > 75MHz VT = 1.5 V; 3V66 Freq < 75MHz Guaranteed by design, not 100% tested in production. 7 100 500 ps 350 500 ps ICS9248-73 Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 1 Duty Cycle Jitter, Cycle-to-cycle1 1 SYMBOL VOH4B VOL4B IOH4B IOL4B CONDITIONS IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 19 TYP 2.3 0.36 -24 23 MAX UNITS V 0.4 V -16 mA mA Tr4B VOL = 0.4 V, VOH = 2.0 V 0.4 1.4 2.1 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 0.4 1.45 2.2 ns Dt4B VT = 1.25 V VT = 1.25 V 45 50 55 % 140 500 ps tjcyc-cyc4B Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH3 VOL3 IOH3 IOL3 CONDITIONS 41 TYP 2.9 0.32 -73 50 VOL = 0.4 V, VOH = 2.4 V 0.4 0.95 VOH = 2.4 V, VOL = 0.4 V 0.4 1 2 ns VT = 1.5 V 45 53 55 % 85 250 ps 110 250 ps IOH = -25 mA IOL = 20 mA VOH = 2.0 V VOL = 0.8 V Tr3 1 Fall Time Tf3 1 Duty Cycle Dt3 1 Skew Tsk1 Jitter, Cycle-to-cycle tjcyc-cyc3B1 VT = 1.5 V VT = 1.25 V Rise Time 1 1 Guarenteed by design, not 100% tested in production. 8 MIN 2.4 MAX UNITS V 0.4 V -40 mA mA 2 ns ICS9248-73 Electrical Characteristics - 48MHz/FS3; REF0 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle Duty Cycle 1 1 1 Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 25 TYP 3.1 0.19 -55 42 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.1 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1 4 ns d t5 VT = 1.5 V, 48MHz/FS3 45 51 55 % d t5 VT = 1.5 V, REF 45 52 55 % 190 500 ps 310 1000 ps 16 TYP 2.9 0.35 -28 22 MAX UNITS V 0.4 V -20 mA mA tjcyc-cyc5 tjcyc-cyc5 VT = 1.5 V, 48MHz/FS3 VT = 1.5 V, REF Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz; 24_48MHz TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 1 Duty Cycle Jitter, Cycle-to-cycle1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 tr5 VOL = 0.4 V, VOH = 2.4 V 1.5 2.4 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.5 2.2 4 ns d t5 VT = 1.5 V VT = 1.5 V 45 50 55 % 240 500 ps tjcyc-cyc5 Guaranteed by design, not 100% tested in production. 9 ICS9248-73 Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Output High Current Output High Current Output Low Current Output Low Current 1 SYMBOL VOH1 VOH1 VOL1 VOL1 IOH1 IOH1 IOL1 IOL1 tr1 1 tf1 Rise Time Fall Time Duty Cycle 1 d t1 tsk1 1 Skew Jitter, Cycle-to-cycle1 1 tjcyc-cyc1 CONDITIONS IOH = -11 mA; Pci0 & Pci1 IOH = -11 mA IOL = 9.4 mA; Pci0 & Pci1 IOL = 9.4 mA VOH = 2.0 V; Pci0 & Pci1 VOH = 2.0 V VOL = 0.8 V; Pci0 & Pci1 VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V; PCI0:1, CL =60pF VOL = 0.4 V, VOH = 2.4 V; PCI2:7 VOH = 2.4 V, VOL = 0.4 V; PCI0:1, CL =60pF VOH = 2.4 V, VOL = 0.4 V; PCI2:7 VT = 1.5 V VT = 1.5 V; CL =60pF for Pci0 & PCI1 VT = 1.5 V; CL =50pF for Pci0 & PCI1 VT = 1.5 V; CL =40pF for Pci0 & PCI1 VT = 1.5 V Guaranteed by design, not 100% tested in production. 10 MIN 2.4 2.4 25 25 0.5 0.5 0.5 0.5 45 TYP 3.2 3.1 0.12 0.2 -110 -55 82 42 1.5 1.7 1.4 1.7 50 545 360 455 130 MAX UNITS V V 0.4 V 0.4 V -22 mA -22 mA mA mA 2.3 ns 2.3 ns 2 ns 2 ns 55 500 500 % ps ps ps ps ICS9248-73 Group Offset Waveforms Group Skews at common Transition Edges TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) CL = 20 pF for CPU and IOAPIC CL = 50 pF for PCI0 & PCI1, CL = 30 pF for other PCIs, SDRAM and 3V66 GROUP SYMBOL CONDITIONS MIN TYP CPU to SDRAM tCP U-SDRAM VT = 1.5 V; VTL = 1.25 V SDRAM leads CPU by 2.5ns for CPU66 0 100 CPU leads SDRAM by 5.0ns for CPU100 CPU to 3V66 tCP U-3V66 VT = 1.5 V; VTL = 1.25 V CPU leads 3V66 by 7.5ns for CPU66 0 100 CPU leads 3V66 by 0.0ns for CPU100 0 360 IOAPIC to PCI t IOAP IC-P CI VT = 1.5 V; VTL = 1.25 V t3V66-P CI VT = 1.5 V 1.5 2.5 3V66 to PCI Guaranteed by design, not 100% tested in production. 11 MAX UNITS 500 ps 500 ps 500 4 ps ns ICS9248-73 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 12 ICS9248-73 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 13 ICS9248-73 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS924873 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 14 ICS9248-73 Pin 1 Index Area .093 DIA. PIN (Optional) D/2 E/2 PARTING LINE H L DETAIL “A” TOP VIEW BOTTOM VIEW -eA2 c SEE DETAIL “A” A .004 C -E- A A1 A2 B c D E e H h L N µ SEATING PLANE -DEND VIEW SYMBOL B COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0° 8° SIDE VIEW VARIATIONS MIN. .620 AC A1 D NOM. .625 -C- N MAX. .630 48 “For current dimensional specifications, see JEDEC 95.” Dimensions in inches 48 Pin 300 mil SSOP Package Ordering Information ICS9248yF-73-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 15 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.