ICS ICS932S202

ICS932S202
Integrated
Circuit
Systems, Inc.
Frequency Timing Generator for Differential PIII Type
Dual-CPU Systems
Recommended Application:
Serverwork HE-T, HE-SL & LE-T Chipsets
Key Specifications:
• CPU Output Jitter: <150ps
Output Features:
• 2 - CPUs @ 2.5V, up to 180MHz
• 2 - CPU chipset @ 2.5V, up to 180MHz
• 3 - IOAPIC @ 2.5V
• 3 - 3V66MHz @ 3.3V
• 11 - PCIs @ 3.3V
• 1 - 48MHz, @ 3.3V fixed
•
IOAPIC Output Jitter: <500ps
•
48MHz, 3V66, PCI Output Jitter: <500ps
•
Ref Output Jitter. <1000ps
•
CPU Output Skew: <175ps
•
IOAPIC Output Skew <250ps
•
PCI Output Skew: <500ps
• 1 - 24/48MHz, @ 3.3V
• 2 - REF @ 3.3V
Features:
• Up to 180MHz frequency support
•
3V66 Output Skew <250ps
•
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ =
1.3ns)
•
CPU to PCI Output Offset: 0.0 - 1.5ns (typ =
0.9ns)
•
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ =
2.0ns)
Support power management: Power down Mode
from I2C programming.
•
Spread spectrum for EMI control
± 0.25% center spread).
•
Uses external 14.318MHz crystal
•
5 - FS pins for frequency select
Block Diagram
Pin Configuration
PLL2
48MHz
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
SEL24_48#
REF (1:0)
CPU
DIVDER
CPUCLK (1:0)
CPU_CSCLK (1:0)
IOAPIC
DIVDER
IOAPIC (2:0)
PCI
DIVDER
PCICLK (10:0)
3V66
DIVDER
3V66 (2:0)
Control
SDATA
SCLK
Logic
FS (4:0)
Config.
PD#
24_48MHz
Reg.
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GNDPCI
*FS0/PCICLK0
*FS1/PCICLK1
VDDPCI
*FS2/PCICLK2
*FS3/PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
PCICLK10
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS932S202
•
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC0
IOAPIC1
GNDLAPIC
IOAPIC2
VDDLCPU
CPUCLK0
GNDLCPU
CPUCLK1
VDDLCPU
CPU_CSCLK0
CPU_CSCLK1
GNDLCPU
VDD66
3V66_0
3V66_1
3V66_2
GND66
SDATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
0600A—08/04/03
ICS932S202
General Description
The ICS932S202 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This
chip provides all the clocks required for such a system.
Spread Spectrum may be enabled through I2C. Spread spectrum typically reduces system EMI by 8dB to 10dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS932S202 employs
a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Pin Descriptions
Pin number
Pin name
1, 7, 13, 19, 25,
GND
31, 36, 41, 45
2
REF0
REF1
3
SEL24_48
4, 10, 16, 23,
VDD
28, 35
5
X1
6
X2
PCICLK0
8
FS0
PCICLK1
9
FS1
PCICLK2
11
FS2
PCICLK3
12
FS3
22, 21, 20, 18,
PCICLK (10:4)
17, 15, 14
24
PD#
26
24_48MHz
27
29
30
48MHz
FS4
SCLK
SDATA
Type
Description
PWR
Ground pins
OUT
OUT
IN
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
PWR
Power pins 3.3V
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
IN
OUT
OUT/IN
IN
IN
I/O
34, 33, 32
3V66 (2:0)
OUT
38, 37
40, 42
39, 43
44, 46, 47
48
CPU_CSCLK (1:0)
CPUCLK (1:0)
VDDLCPU
IOAPIC (2:0)
VDDLAPIC
OUT
OUT
PWR
OUT
PWR
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the
output clocks are held at a Low state.
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output. 3.3V
Logic - input for frequency selection
Clock input of I2C input
Data pin for I2C circuitry 5V tolerant
3.3V clock outputs. These outputs are stopped when
CPU_STOP# is driven active..
Chipset clock outputs @ 2.5V
CPU clock outputs @ 2.5V.
Power pins for CPUCLKs. 2.5V
IOAPIC clocks @ 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
0600A—08/04/03
2
ICS932S202
Functionality
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
103.0
100.0
100.45
100.9
107.1
109.0
112.0
114.00
116.00
118.00
133.30
120.00
122.00
125.00
50.0
66.7
133.3
133.9
138.0
142.0
146.0
150.0
153.0
156.0
159.1
162.0
166.7
168.0
171.0
174.0
177.0
180.0
PCI
34.33
33.33
33.48
33.63
35.70
36.33
37.33
28.50
29.00
29.50
33.33
30.00
30.50
31.25
16.67
16.67
33.33
33.48
34.50
35.50
36.50
37.50
38.25
39.00
39.78
40.50
41.67
42.00
42.75
43.50
44.25
45.00
3V66
68.67
66.67
66.97
67.27
71.40
72.67
74.67
57.00
58.00
59.00
66.65
60.00
61.00
62.50
33.33
33.33
66.67
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.55
81.00
83.33
84.00
85.50
87.00
88.50
90.00
0600A—08/04/03
3
IOAPIC
17.17
16.67
16.74
16.82
17.85
18.17
18.67
14.25
14.50
14.75
16.66
15.00
15.25
15.63
8.33
8.33
16.67
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.89
20.25
20.83
21.00
21.38
21.75
22.13
22.50
ICS932S202
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Bit
(2, 7:4)
Bit 2
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 7
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 6
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
Bit 4
CPU
FS0
0
103.0
1
100.0
0
100.45
1
100.9
0
107.1
1
109.0
0
112.0
1
114.00
0
116.00
1
118.00
0
133.30
1
120.00
0
122.00
1
125.00
0
50.0
1
66.7
0
133.3
1
133.9
0
138.0
1
142.0
0
146.0
1
150.0
0
153.0
1
156.0
0
159.1
1
162.0
0
166.7
1
168.0
0
171.0
1
174.0
0
177.0
1
180.0
PWD
PCI
3V66
IOAPIC
34.33
33.33
33.48
33.63
35.70
36.33
37.33
28.50
29.00
29.50
33.33
30.00
30.50
31.25
16.67
16.67
33.33
33.48
34.50
35.50
36.50
37.50
38.25
39.00
39.78
40.50
41.67
42.00
42.75
43.50
44.25
45.00
68.67
66.67
66.97
67.27
71.40
72.67
74.67
57.00
58.00
59.00
66.65
60.00
61.00
62.50
33.33
33.33
66.67
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.55
81.00
83.33
84.00
85.50
87.00
88.50
90.00
17.17
16.67
16.74
16.82
17.85
18.17
18.67
14.25
14.50
14.75
16.66
15.00
15.25
15.63
8.33
8.33
16.67
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.89
20.25
20.83
21.00
21.38
21.75
22.13
22.50
Reser ved
Note 1
Bit 3
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
0
Bit 1
0 - Normal
1 - Spread spectrum enabled
1
Bit 0
0 - Running
1 - Tristate all outputs
0
Note 1:
Default at power-up will be for latched logic inputs to define frequency, as displayed byBit 3.
0600A—08/04/03
4
ICS932S202
Byte 1: CPU, Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
38
37
42
47
46
44
-
PWD
1
1
1
1
1
1
1
X
Byte 2: PCI Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Description
CPUCLK 1
CPUCSCLK0
CPUCSCLK1
CPUCLK 0
IOAPIC0
IOAPIC1
IOAPIC2
(Reserved)
Pin #
PWD
Description
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Bit 7
18
1
PCICLK7
Bit 6
17
1
PCICLK6
Bit 5
15
1
PCICLK5
Bit 4
14
1
PCICLK4
Bit 3
12
1
PCICLK3
Bit 2
11
1
PCICLK2
Bit 1
9
1
PCICLK1
Bit 0
8
1
PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
33
32
2
3
-
PWD
1
1
1
X
1
1
X
X
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_0
3V66_1
3V66_2
FS1#
REF0
REF1
FS3#
FS2#
Pin #
26
27
22
21
20
-
PWD
1
1
X
1
1
1
1
X
Description
24_48MHz
48MHz
FS0#
(Reserved)
PCICLK10
PCICLK9
PCICLK8
FS4#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are
disabled from switching.
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
Byte6: Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin #
-
PWD
1
1
1
1
1
1
1
1
Description
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Bit
Pin #
PWD
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
0
0
0
0
0
1
1
0
Description
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
0600A—08/04/03
5
ICS932S202
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
–65°C to +150°C
115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VIH
Input High Voltage
VIL
Input Low Voltage
VIN = VDD
IIH
Input High Current
VIN = 0V; Inputs with no pull-up
IIL1
Input Low Current
resistors
VIN = 0V; Inputs with pull-up
IIL2
Input Low Current
resistors
MIN
2
VSS - 0.3
TYP
MAX
UNITS
VDD + 0.3
V
0.8
V
5
µA
-5
µA
-200
µA
IDD3.3OP100
CL = 30 pF; Select @ 100 MHz
137
160
mA
IDD3.3OP133
CL = 30 pF; Select @ 133 MHz
143
160
mA
220
14.318
600
16
5
45
µA
MHz
pF
pF
3
ms
3
ms
3
ms
Operating Supply Current
CL =30 pF; PWRDWN#=0
VDD = 3.3 V
Logic Inputs
1
Input Capacitance
X1 & X2 pins
To 1st crossing of target
1
Ttrans
Transition time
frequency
From
1st
crossing
to 1 % target
1
Ts
Settling Time
frequency.
From VDD = 3.3 V to 1% target
1
TSTAB
Clk Stabilization
frequency
1
Guaranteed by design, not 100% tested in production.
Powerdown Current
Input Frequency
IDD3.3PD
Fi
CIN
CINX
11
27
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; VDD = 3.3 V +/- 5%, VDDL = 2.5V +/- 5% (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
CL = 30 pF; Select @ 100 MHz
IDD2.5OP100
Operating Supply Current
IDD2.5OP133
CL = 30 pF; Select @ 133 MHz
CL = 30 pF; PWRDWN# = 0
IDD2.5PD
Power Down Supply Current
0600A—08/04/03
6
MIN
TYP
34
58
3
MAX
75
90
100
UNITS
mA
mA
mA
ICS932S202
Group Offset
Group
Offset
Measurement Loads
Measure Points
CPU to 3V66
0.8 to 1.8ns CPU leads CPU @ 20pF, 3V66 @ 30pF
CPU @1.25V, 3V66 @ 1.5V
CPU to PCI
0 to 1.5ns CPU leads
CPU @ 20pF, PCI @ 30pF
CPU @ 1.25V, PCI @ 1.5V
CPU to IOAPIC 1.5 to 4.0ns CPU leads CPU @ 20pF, IOAPIC @ 20pF CPU @ 1.25V, IOAPIC @ 1.25V
Note: 1. All offsets are to be measured at rising edges.
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
IOH = -12 mA
2
2.3
Output High Voltage
VOH2B
IOL = 12 mA
0.3
Output Low Voltage
VOL2B
I
V
=
1.7
V
-35
Output High Current
OH2B
OH
IOL2B
VOL = 0.7 V
19
26
Output Low Current
1
VOL = 0.4 V, VOH = 2.0 V
0.4
0.73
Rise Time
tr2B
1
VOH = 2.0 V, VOL = 0.4 V
0.4
0.76
Fall Time
tf2B
1
VT = 1.25 V
45
50.6
Duty Cycle
dt2B
-2
Cpu0:1
VT=1.25 to 1.5V @ all frequency
CPU0:3 VT=1.25 to 1.5V @ 66MHz
140
Skew
VT=1.25 to 1.5V @ 100MHz
165
VT=1.25 to 1.5V @ 133MHz
155
VT=1.25 to 1.5V @ 200MHz
70
1
V
=
1.25
V
t
108
Jitter, Cycle-to-cycle
jcyc-cyc2B
T
1
Guaranteed by design, not 100% tested in production.
0600A—08/04/03
7
MAX
0.4
-19
0.9
0.9
55
175
175
175
175
175
250
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ps
ps
ps
ps
ICS932S202
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output High Voltage
VOH1
IOH = -25 mA
2.4
2.9
Output Low Voltage
VOL1
IOL = 20 mA
0.32
Output High Current
IOH1
VOH = 2.0 V
-73
Output Low Current
IOL1
VOL = 0.8 V
41
50
1
Rise Time
Tr
VOL = 0.4 V, VOH = 2.4 V
0.5
1.31
1
Fall Time
Tf
VOH = 2.4 V, VOL = 0.4 V
0.5
1.39
1
Duty Cycle
Dt
VT = 1.5 V
45
49
1
VT = 1.5 V
85
Skew
Tsk1
1
VT = 1.5 V
tjcyc-cyc1
163
Jitter, Cycle-to-cycle
1
MAX
0.4
-40
2
2
55
250
500
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output High Voltage
VOH1
IOH = -11 mA
2.4
3.1
IOL = 9.4 mA
0.17
Output Low Voltage
VOL1
VOH = 2.0 V
-62
Output High Current
IOH1
VOL = 0.8 V
25
45
Output Low Current
IOL1
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
1.42
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.54
1
Duty Cycle
dt1
VT = 1.5 V
45
50.8
tsk1
VT = 1.5 V
266
Skew
1
Jitter, Cycle-to-cycle
tjcyc-cyc1
VT = 1.5 V
133
1
Guaranteed by design, not 100% tested in production.
0600A—08/04/03
8
MAX
0.4
-22
2.5
2.5
55
500
500
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ICS932S202
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
IOH = -12 mA
Output High Voltage
VOH5
Output Low Voltage
VOL5
IOL = 9 mA
IOH5
VOH = 2.0 V
Output High Current
IOL5
VOL = 0.8 V
Output Low Current
1
Rise Time
tr5
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf5
VOH = 2.4V, VOL = 0.4 V
1
VT = 1.5 V
Duty Cycle
dt5
1
VT = 1.5 V
tjcyc-cyc5
Jitter, Cycle-to-Cycle
1
MIN
2.6
16
45
TYP
2.9
0.3
-27
22
1.9
2.10
50.9
303
MAX
0.4
-22
4
4
55
500
UNITS
V
V
mA
mA
ns
ns
%
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
MIN
IOH = -12 mA
2.6
Output High Voltage
VOH5
IOL = 9 mA
Output Low Voltage
VOL5
IOH5
VOH = 2.0 V
Output High Current
IOL5
VOL = 0.8 V
16
Output Low Current
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr5
1
Fall Time
tf5
VOH = 2.4V, VOL = 0.4 V
1
Duty Cycle
dt5
VT = 1.5 V
45
1
t
V
=
1.5
V
Jitter, Cycle-to-Cycle
jcyc-cyc5
T
1
Guaranteed by design, not 100% tested in production.
0600A—08/04/03
9
TYP
2.9
0.3
-27
22
1.9
2.00
52.6
850
MAX
0.4
-22
4
4
55
1000
UNITS
V
V
mA
mA
ns
ns
%
ps
ICS932S202
Electrical Characteristics - CPU_CSCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
IOH = -12 mA
2
2.3
Output High Voltage
VOH2B
IOL = 12 mA
0.3
Output Low Voltage
VOL2B
IOH2B
VOH = 1.7 V
-35
Output High Current
IOL2B
VOL = 0.7 V
19
26
Output Low Current
1
VOL = 0.4 V, VOH = 2.0 V
0.4
0.9
Rise Time
tr2B
1
VOH = 2.0 V, VOL = 0.4 V
0.4
0.8
Fall Time
tf2B
1
VT = 1.25 V
45
54
Duty Cycle
dt2B
34
Cpu_CS0:1 VT=1.25 to 1.5V @ all frequency
Skew
1
tjcyc-cyc2B
VT = 1.25 V
Jitter, Cycle-to-cycle
119
1
MAX
0.4
-19
1.6
1.6
55
175
250
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output High Voltage
VOH4B
IOH = -12.0 mA
2
2.3
Output Low Voltage
VOL4B
IOL = 12 mA
0.31
Output High Current
IOH4B
VOH = 1.7 V
-33
Output Low Current
IOL4B
VOL = 0.7 V
19
27
1
Rise Time
tr4B
VOL = 0.4 V, VOH = 2.0 V
0.5
1.8
1
Fall Time
tf4B
VOH = 2.0 V, VOL = 0.4 V
0.5
1.8
1
Duty Cycle
dt4B
VT = 1.25 V
45
49.3
1
tsk4B
VT = 1.25 V
95
Skew
1
VT = 1.25 V
tjcyc-cyc4B
112
Jitter, Cycle-to-cycle
1
Guaranteed by design, not 100% tested in production.
0600A—08/04/03
10
MAX
0.4
-19
2
2
55
250
500
UNITS
V
V
mA
mA
ns
ns
%
ps
ICS932S202
Power Management Features:
PD#
CPUCLK IOAPIC
3V66
PCI
PCI_F
REF.
48MHz
Osc
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
1
ON
ON
ON
ON
ON
ON
ON
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency
Signal
PD#
Signal State
1 (normal operation)
0 (power down)
No. of rising edges
of PCICLK
3mS
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes
low/high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
0600A—08/04/03
11
ICS932S202
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
ICS (Slave/Receiver)
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0600A—08/04/03
12
ICS932S202
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the
internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle
to complete.
PD#
CPUCLK
3V66
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS932S202device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0600A—08/04/03
13
ICS932S202
300 mil SSOP
c
N
SYMBOL
L
E1
INDEX
AREA
A
A1
b
c
D
E
E1
e
h
L
N
a
E
1 2
α
h x 45°
D
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
N
A
48
A1
-Ce
b
SEATING
PLANE
D mm.
MIN
15.75
D (inch)
MAX
16.00
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
.10 (.004) C
Ordering Information
ICS93S202yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0600A—08/04/03
14
MAX
.630