ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Programmable Timing Control Hub for K7TM System Recommended Application: SiS741 style chipset with 964 South Bridge. Features/Benefits: • Selectable synchronous/asynchronous AGP/PCI frequency • Programmable output frequency. Output Features: • Programmable output divider ratios. • 1 - Pair of differential open drain CPU outputs • Programmable output rise/fall time. • 1 - Single-ended open drain CPU output • Programmable output skew. • 1 - Pair of current mode differential serial reference clock • Programmable spread percentage for EMI control. • 8 - PCICLK @ 3.3V including 2 PCI clock free running • Watchdog timer technology to reset system • 2 - AGPCLK @ 3.3V if system malfunctions. • 3 - REF @ 3.3V • Programmable watch dog safe frequency. • 2 - ZCLK @ 3.3V • Support I2C Index read/write and block read/write • 2 - IOAPIC @ 2.5V operations. • 1 - 12_48MHz @ 3.3V • Uses external 14.318MHz reference input. • 1 - 24_48MHz @ 3.3V Key Specifications: • CPU Output Jitter <250ps • AGP Output Jitter <250ps • ZCLK Output Jitter <250ps • PCI Output Jitter <500ps • CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns Pin Configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU MHz 200.00 200.01 200.97 190.11 100.00 100.00 100.99 95.00 166.66 166.65 161.59 151.97 133.33 133.34 133.98 126.66 206.02 210.00 214.06 217.90 103.01 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 ZCLK MHz 133.33 133.34 133.98 126.74 133.33 133.34 134.66 126.66 133.33 133.32 129.27 121.57 133.33 133.34 133.98 126.66 137.35 140.00 142.70 145.27 137.35 AGP MHz 66.66 66.67 66.99 63.37 66.66 66.67 67.33 63.33 66.66 66.66 64.64 60.79 66.66 66.67 66.99 63.33 68.67 70.00 71.35 72.63 68.67 PCI MHz 33.33 33.33 33.49 31.69 33.33 33.33 33.66 31.67 33.33 33.33 32.32 30.39 33.33 33.33 33.49 31.67 34.34 35.00 35.68 36.32 34.34 1 0 1 0 1 105.00 100.00 140.00 70.00 35.00 *(PCI_STOP#)PCICLK3 21 1 0 1 1 0 106.99 100.00 142.65 71.33 35.66 *(CPU_STOP#)PCICLK4 22 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 109.01 164.66 167.91 171.22 174.38 137.32 140.00 142.67 145.33 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 145.35 131.73 134.33 136.98 139.50 137.32 140.00 142.67 145.33 72.68 65.86 67.17 68.49 69.75 68.66 70.00 71.34 72.66 36.34 32.93 33.58 34.24 34.88 34.33 35.00 35.67 36.33 *(PD#)PCICLK5 23 Bit4 0813B—05/17/05 VDDREF 1 48 VDDLAPIC **FS0/REF0 2 47 IOAPIC1 **FS1/REF1 3 46 IOAPIC0 **Mode/REF2 4 GNDREF 5 45 GNDAPIC 44 VDDSRC X1 6 43 SRCCLKT X2 7 42 SRCCLKC 41 GND GNDZ 8 ZCLK0 9 ZCLK1 10 VDDZ 11 SCLK 12 VDDPCI 13 *FS2/PCICLK_F0 14 ICS952703 Functionality 40 CPUCLKODT1 39 GNDCPU 38 CPUCLKODT0 37 CPUCLKODC0 36 AVDD 35 AGND 34 IREF 33 SDATA *FS3/PCICLK_F1 15 PCICLK0 16 32 GNDAGP 31 AGPCLK0 30 AGPCLK1 PCICLK1 17 GNDPCI 18 VDDPCI 19 29 VDDAGP 28 AVDD48 PCICLK2 20 27 12_48MHz/SEL12_48#MHz* 26 24_48MHz/SEL24_48#MHz**~ GNDPCI 24 25 GND48 48-SSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output have 1.5X Drive Strength ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. General Description The ICS952703 is a two chip clock solution for desktop designs using SiS741 style chipsets. When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952703 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram Frequency Dividers PLL2 12_48MHZ 24_48MHZ X1 X2 XTAL REF (2:0) CPUCLKODT (1:0) CPU_STOP# CPUCLKODC0 SRCCLKT SRCCLKC PCI_STOP# SCLK Programmable Spread PLL1 SEL24_48MHZ SEL12_48MHz PD# SDATA Programmable Frequency Dividers Control Logic STOP Logic IOAPIC (1:0) PCICLKF (1:0) PCICLK (5:0) FS (3:0) ZCLK (1:0) MODE AGPCLK (1:0) 0813B—05/17/05 2 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN TYPE PWR I/O I/O I/O PWR IN OUT PWR OUT OUT PWR IN PWR I/O I/O OUT OUT PWR PWR OUT DESCRIPTION PWR PWR Ref, XTAL power supply, nominal 3.3V Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output. Ground pin for the REF outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin for the ZCLK outputs 3.3V Hyperzip clock output. 3.3V Hyperzip clock output. Power supply for ZCLK clocks, nominal 3.3V Clock pin of I2C circuitry 5V tolerant Power supply for PCI clocks, nominal 3.3V Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V PCI clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / PCI clock output. Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / PCI clock output. Asynchronous active low input pin used to power down the device into a low power state / PCI clock output. Ground pin for the PCI outputs Ground pin for the 48MHz outputs 24_48MHz/SEL24_48#MHz**~ I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. 27 12_48MHz/SEL12_48#MHz* I/O 12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz. 28 29 30 31 32 33 AVDD48 VDDAGP AGPCLK1 AGPCLK0 GNDAGP SDATA PWR PWR OUT OUT PWR I/O 34 IREF OUT 35 36 AGND AVDD PWR PWR 37 CPUCLKODC0 OUT 38 CPUCLKODT0 OUT 39 GNDCPU PWR 40 CPUCLKODT1 OUT 41 GND PWR 42 SRCCLKC OUT 43 SRCCLKT OUT 44 45 46 47 48 VDDSRC GNDAPIC IOAPIC0 IOAPIC1 VDDLAPIC PWR PWR OUT OUT PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V Power supply for AGP clocks, nominal 3.3V AGP clock output AGP clock output Ground pin for the AGP outputs Data pin for I2C circuitry 5V tolerant This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Analog Ground pin for Core PLL 3.3V Analog Power pin for Core PLL "Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. Ground pin for the CPU outputs True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. Ground pin. Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Supply for SRC clocks, 3.3V nominal Ground pin for the IOAPIC outputs. IOAPIC clock outputs, norminal 2.5V. IOAPIC clock outputs, norminal 2.5V. Power pin for the IOAPIC outputs. 2.5V. 21 22 VDDREF **FS0/REF0 **FS1/REF1 **Mode/REF2 GNDREF X1 X2 GNDZ ZCLK0 ZCLK1 VDDZ SCLK VDDPCI *FS2/PCICLK_F0 *FS3/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 *(PCI_STOP#)PCICLK3 *(CPU_STOP#)PCICLK4 23 *(PD#)PCICLK5 24 25 GNDPCI GND48 26 I/O I/O I/O * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength 0813B—05/17/05 3 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS952703 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0813B—05/17/05 4 Not acknowledge stoP bit ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Table1: Frequency Selection Table Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 200.00 200.01 200.97 190.11 100.00 100.00 100.99 95.00 166.66 166.65 161.59 151.97 133.33 133.34 133.98 126.66 206.02 210.00 214.06 217.90 103.01 105.00 106.99 109.01 164.66 167.91 171.22 174.38 137.32 140.00 142.67 145.33 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 ZCLK MHz 133.33 133.34 133.98 126.74 133.33 133.34 134.66 126.66 133.33 133.32 129.27 121.57 133.33 133.34 133.98 126.66 137.35 140.00 142.70 145.27 137.35 140.00 142.65 145.35 131.73 134.33 136.98 139.50 137.32 140.00 142.67 145.33 AG P MHz 66.66 66.67 66.99 63.37 66.66 66.67 67.33 63.33 66.66 66.66 64.64 60.79 66.66 66.67 66.99 63.33 68.67 70.00 71.35 72.63 68.67 70.00 71.33 72.68 65.86 67.17 68.49 69.75 68.66 70.00 71.34 72.66 0813B—05/17/05 5 PCI MHz 33.33 33.33 33.49 31.69 33.33 33.33 33.66 31.67 33.33 33.33 32.32 30.39 33.33 33.33 33.49 31.67 34.34 35.00 35.68 36.32 34.34 35.00 35.66 36.34 32.93 33.58 34.24 34.88 34.33 35.00 35.67 36.33 Spread % 0.5% 0.35% 0.35% 0.35% 0.5% 0.35% 0.35% 0.35% 0.5% 0.35% 0.35% 0.35% 0.5% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% 0.35% down c enter c enter c enter down c enter c enter c enter down c enter c enter c enter down c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter c enter ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. 2 I C Table: Frequency Select Register Byte 0 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type 0 1 PWD SS_EN SEL12_48MHz SEL24_48MHz Bit4 FS3 FS2 FS1 FS0 Spread Enable Output Select Output Select Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 RW RW RW RW RW RW RW RW OFF 48MHz 48MHz ON 12MHz 24MHz 1 Latch Latch 0 Latch Latch Latch Latch Name Control Function Type 0 1 PWD REF0 REF1 REF2 SRCCLKT/C PCICLK_F0 PCICLK_F1 PCICLK0 PCICLK1 Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD PCICLK2 PCICLK3 PCICLK4 PCICLK5 24_48MHz 12_48MHz AGPCLK1 AGPCLK0 Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD See Table1: Frequency Selection Table 2 I C Table: Output Control Register Byte 1 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 2 3 4 43,42 14 15 16 17 7 6 5 4 3 2 1 0 2 I C Table: Output Control Register Byte 2 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 20 21 22 23 26 27 30 31 7 6 5 4 3 2 1 0 2 I C Table: Output Control Register Pin # Byte 3 Bit 7 - Reserved Reserved RW - - 1 Bit 6 - Reserved Reserved RW - - 0 Bit Bit Bit Bit Bit Bit - IREF Bit1 IREF Bit0 Vendor_ID3 Vendor_ID2 Vendor_ID1 IREF Mulitiplier Programming Bits RW RW RW RW RW 00 = 5 x Iref 01 = 4 x Iref - 10 = 6 x Iref 11 = 7 x Iref - 1 0 0 0 0 5 4 3 2 1 0 Vendor ID Vendor_ID0 RW 0813B—05/17/05 6 1 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. 2 I C Table: Output Skew Control Register Byte 4 Bit Bit Bit Bit Bit Bit Bit Bit Pin # PCISkw3 PCISkw2 PCISkw1 PCISkw0 AGPSkw3 AGPSkw2 AGPSkw1 AGPSkw0 - 7 6 5 4 3 2 1 0 Name Control Function Type RW RW RW RW RW CPU-AGP 7 Step Skew RW Control (ps) RW RW CPU-PCI 7 Step Skew Control (ps) 0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 1 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 0100:/4 0101:/6 0110:/10 0111:/14 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1000:/8 1001:/12 1010:/20 1011:/28 PWD 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900 X X X X X X X X 2 I C Table: Output Divider Control Register Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name ZCLKDiv3 ZCLKDiv2 ZCLKDiv1 ZCLKDiv0 AGPDiv3 AGPDiv2 AGPDiv1 AGPDiv0 Control Function ZCLK Divider Ratio Programmaing Bits AGP Divider Ratio Programmaing Bits Type RW RW RW RW RW RW RW RW 0 0000:/2 0001:/3 0010:/5 0011:/7 0000:/2 0001:/3 0010:/5 0011:/7 PWD 1 1100:/16 1101:/24 1110:/40 1111:/56 1100:/16 1101:/24 1110:/40 1111:/56 X X X X X X X X 2 I C Table: Output Drive Control Register Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type 0 1 PWD PCIStr1 PCIStr0 PCICLKF (1:0) Strength Control PCIStr1 PCIStr0 PCIStr1 PCIStr0 AGPStr1 AGPStr0 PCICLK (2:0) Strength Control PCICLK (5:3) Strength Control AGPCLK Strength Control RW RW RW RW RW RW RW RW 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.70X 01 = 0.80X 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.90X 11 = 1.00X 1 1 1 1 1 1 1 1 Name Control Function Type 0 1 PWD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW - - 1 1 1 1 1 1 1 1 2 I C Table: Reserved Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - 0813B—05/17/05 7 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. 2 I C Table: Byte Count Register Byte 8 Pin # Name Control Function Type 0 1 PWD Bit 7 - BC7 RW 0 Bit 6 - BC6 RW 0 Bit 5 - BC5 RW Bit 4 - BC4 Bit 3 - BC3 Bit 2 - BC2 RW 1 Bit 1 - BC1 RW 1 Bit 0 - BC0 RW 1 RW Byte Count Programming b(7:0) RW 0 Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. 0 1 2 I C Table: WD Time Control & Async Frequency Selection Register Byte 9 Pin # Name Control Function Type Reserved Fix PLL Async Freq Programming bits Reserved Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 RW RW RW RW 7 6 5 4 - Reserved ASYNC1 ASYNC0 Reserved Bit 3 - WDTCtrl Bit 2 Bit 1 Bit 0 - WD2 WD1 WD0 Bit Bit Bit Bit RW RW RW RW 0 1 See Table 2: Asynchronous Frequency Selection Table Reserved Reserved 290ms Base 1160ms Base These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. PWD 0 0 0 0 0 1 1 1 Table 2: Asynchronous Frequency Selection Table B9 bit6 B9 bit5 0 0 1 1 0 1 0 1 SRC ZCLK AGP PCI Main PLL Main PLL Main PLL 100 133.33 66.66 100 150.00 75 100 133.33 80 Main PLL 33.33 37.5 40 2 I C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Bit 7 - M/NEN Bit 6 Bit 5 Bit 4 - WDEN WDStatus WD SF4 Bit 3 - WD SF3 Bit 2 - WD SF2 Bit 1 - WD SF1 Bit 0 - WD SF0 Control Function M/N Programming Enable Watchdog Enable WD Alarm Status Watch Dog Safe Freq Programming bits Type 0 1 PWD RW Disable Enable 0 RW R RW Disable Normal Enable Alarm 0 0 0 RW RW RW RW 0813B—05/17/05 8 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). 0 0 0 0 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. 2 I C Table: VCO Frequency Control Register Byte 11 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div8 N Divider Prog bit 8 RW Bit 6 - N Div9 N Divider Prog bit 9 RW X Bit 5 - M Div5 RW X Bit 4 - M Div4 Bit 3 - M Div3 Bit 2 - M Div2 Bit 1 - M Div1 Bit 0 - M Div0 X The decimal representation of M and N Divier in Byte 11 and 12 will configure the RW VCO frequency. Default at power up = latch-in or Byte 0 Rom table. M Divider Programming RW bits RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW RW X X X X X 2 I C Table: VCO Frequency Control Register Byte 12 Pin # Control Function Name Bit 7 Bit 6 - N Div7 N Div6 Bit 5 - N Div5 Bit 4 - N Div4 Bit 3 - N Div3 Bit 2 - N Div2 Bit 1 - N Div1 Bit 0 - N Div0 Type 0 1 PWD RW RW X X RW X The decimal representation of M and N Divier in Byte 11 and 12 will configure the N Divider Programming RW VCO frequency. Default at power up = b(7:0) latch-in or Byte 0 Rom table. RW RW VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW RW X X X X X 2 I C Table: Spread Spectrum Control Register Byte 13 Pin # Control Function Name Type 0 1 PWD Bit 7 - SSP7 RW Bit 6 - SSP6 RW Bit 5 - SSP5 RW Bit 4 - SSP4 RW Bit 3 - SSP3 Bit 2 - SSP2 RW Bit 1 - SSP1 RW X Bit 0 - SSP0 RW X Spread Spectrum Programming b(7:0) RW X X These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. X X X X 2 I C Table: Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Type 0 1 PWD R - - 0 Bit 7 - Reserved Bit 6 - SSP14 RW Bit Bit Bit Bit Bit Bit - SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 RW RW RW RW RW RW 5 4 3 2 1 0 Spread Spectrum Programming b(14:8) 0813B—05/17/05 9 X These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. X X X X X X ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND –0.5 V to VDD +0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 1 SYMBOL CONDITIONS MIN 2 V IH VIL VSS - 0.3 VIN = VDD I IH IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 IDD(op) IDDPD Fi CIN Transition Time1 Clk Stabilization1 CINX Ttrans TSTAB Skew1 TCPU-PCI CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; 11 Logic Inputs TYP MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 mA 40 mA 16 MHz 5 pF X1 & X2 pins To 1st crossing of target Freq. From VDD = 3.3 V to 1% target Freq. 27 45 3 3 pF ms ms VT = 1.5 V 1.5 4 ns Guaranteed by design, not 100% tested in production. 0813B—05/17/05 10 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Electrical Characteristics - CPUCLKT/C TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Current Source V O = Vx Zo1 Output Impedance IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOL = 0.175V, VOH = 0.525V Rise Time t r3 VOH = 0.175V VOL = 0.525V Fall Time t f3 VT = 50% Duty Cycle dt3 VT = 50% Skew t sk3 1 VT = 50% Jitter, Cycle to cycle tjcyc-cyc MIN TYP MAX UNITS 3000 Ω 2.4 V 0.4 700 700 55 100 150 175 175 45 ps ps % ps ps Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 1 Fall Time 1 Duty Cycle 1 Skew Jitter SYMBOL VOH1 VOL1 IOH1 I OL1 CONDITIONS IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.1 16 TYP MAX UNITS V 0.4 V -22 mA 57 mA t r1 VOL = 0.4 V, VOH = 2.4 V 2 ns t f1 VOH = 2.4 V, VOL = 0.4 V 2 ns dt1 VT = 1.5 V 55 % VT = 1.5 V 500 ps VT = 1.5 V VT = 1.5 V 500 500 ps ps t sk1 tjcyc-cyc tjabs1 1 45 1 Guaranteed by design, not 100% tested in production. 0813B—05/17/05 11 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Electrical Characteristics - AGPCLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage Skew VOH1 VOL1 IOH1 I OL1 tr11 tf11 dt11 t sk11 Jitter tjcyc-cyc 1 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle CONDITIONS MIN VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V TYP MAX UNITS MHz 55 Ω V -33 30 0.55 -33 38 V mA mA VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V 0.5 45 2 55 ns % 250 ps 250 ps VT = 1.5 V VT = 1.5 V 3V66 Electrical Characteristics - REF TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 SYMBOL VOH5 VOL5 IOH5 I OL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 16 TYP MAX UNITS V 0.4 V -22 mA mA t r5 VOL = 0.4 V, VOH = 2.4 V 4 ns t f5 VOH = 2.4 V, VOL = 0.4 V 4 ns Duty Cycle dt5 Jitter1 tjcyc-cyc5 tjabs5 VT = 1.5 V VT = 1.5 V VT = 1.5 V 55 1000 800 % ps ps 1 Fall Time 1 45 0813B—05/17/05 12 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Electrical Characteristics - ZCLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage Skew VOH1 VOL1 IOH1 I OL1 tr11 tf11 dt11 t sk11 Jitter tjcyc-cyc 1 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle CONDITIONS MIN VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V TYP MAX UNITS MHz 55 Ω V -33 30 0.55 -33 38 V mA mA VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V 0.5 45 2 55 ns % 250 ps 250 ps VT = 1.5 V VT = 1.5 V 0813B—05/17/05 13 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0813B—05/17/05 14 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms PCI_STOP# PCI_F 33MHz PCI 33MHz tsu CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms CPU_STOP# CPUT CPUC CPU_STOP# Functionality CPU_STOP# CPUT CPUC 1 Normal Normal 0 iref * Mult Float 0813B—05/17/05 15 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. c N SYMBOL L E1 E INDEX AREA 1 2 α h x 45° D A A A1 b c D E E1 e h L N α A1 -Ce SEATING PLANE b .10 (.004) C N 48 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS952703yFLFT Example: ICS 95XXXX y F LF - T Designation for tape and reel packaging RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0813B—05/17/05 16 MAX .630 ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Revision History Rev. B Issue Date Description 5/17/2005 Added LF Ordering Information Page # 16 0813B—05/17/05 17