ICS ICS9LPR426A

ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
Low Power Programmable Timing Control Hub™ for P4™ processor
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
PCIEX outputs cycle-cycle jitter < 125ps
Output Features:
•
SATA outputs cycle-cycle jitter < 125ps
•
2 - 0.7V push-pull differential CPU pairs
•
PCI outputs cycle-cycle jitter < 500ps
•
5 - 0.7V push-pull differential PCIEX pairs
•
+/- 100ppm frequency accuracy on CPU, PCIEX and
SATA clocks
•
1 - 0.7V push-pull differential SATA pair
+/- 100ppm frequency accuracy on USB clocks
•
1 - 0.7V push-pull differential CPU/PCIEX selectable pair •
•
1 - 0.7V push-pull differential 27MHz/LCDCLK/PCIEX
Features/Benefits:
selectable pair
•
Supports tight ppm accuracy clocks for Serial-ATA and
•
4 - PCI (33MHz)
PCIEX
•
2 - PCICLK_F, (33MHz) free-running
•
Supports programmable spread percentage and
•
1 - USB, 48MHz
frequency
•
2 - REF, 14.318MHz
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
PEREQ# pins to support PCIEX power management.
•
Low power differential clock outputs (No 50W resistor
to GND needed)
Recommended Application:
Low Power CK410M Compliant Main Clock
Pin Configuration
PCIeT_L1
PCIeC_L1
VDDPCIEX
PCIeT_L2
PCIeC_L2
PCIeT_L3
PCIeC_L3
SATACLKT_L
SATACLKC_L
VDDPCIEX
Functionality Table
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2/REQ_SEL**
PCI&PCIEX_STOP#
CPU_STOP#
REF1/FSLC/TEST_SEL
REF0
GND
X1
X2
VDDREF
SDATA
SCLK
GND
Bit 4 Bit 3
Bit 2 Bit 1 Bit 0 CPU
FS LC FSLB FSLA MHz
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
VDDCPU
0
1
0
0
1
CPUT_L1
CPUC_L1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
56-TSSOP
1
0
1
0
1
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
ICS9LPR426A
VDDPCI
GND
PCICLK3
PCICLK4
*SELPCIEX0_LCD#PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
*SELLCD_27#/PCICLK_F1
Vtt_PwrGd#/PD
VDD48
FSLA/USB_48MHz
GND
DOTT_96MHzL
DOTC_96MHzL
FSLB/TEST_MODE
27FIX/LCD_SSCGT/PCIeT_L0
27SS/LCD_SSCGC/PCIeC_L0
CPUT_L0
CPUC_L0
VDD
GNDA
VDDA
CPUITPT_L2/PCIeT_L6
CPUITPC_L2/PCIeC_L6
VDDPCIEX
PEREQ1#/PCIeT_L5
PEREQ2#/PCIeC_L5
PCIeT_L4
PCIeC_L4
GND
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
269.33
271.99
274.66
277.33
279.99
282.66
285.33
287.99
269.33
271.99
274.66
277.33
279.99
282.66
285.33
287.99
PCIEX
MHz
PCI
MHz
SATA
MHz
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
100.75
101.75
102.74
103.74
104.74
105.74
106.73
107.73
108.73
109.73
110.72
111.72
112.72
113.72
114.71
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
115.71 33.33
100.00
1346–10/23/07
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
PWR
PWR
OUT
OUT
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 3.3V PCI clock
output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP#.
SELLCD_27#: latched input to select pin functionality
1 = LCDCLK pair
0 = 27MHzSS/27MHzSS# pair
Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be
sampled. PD is an asynchronous active high input pin used to put the device into a low
power state. The internal clocks, PLLs and the crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.
Ground pin.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm to GND
needed.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed.
1
2
3
4
VDDPCI
GND
PCICLK3
PCICLK4
5
*SELPCIEX0_LCD#PCICLK5
6
7
GND
VDDPCI
8
ITP_EN/PCICLK_F0
I/O
9
*SELLCD_27#/PCICLK_F1
I/O
10
Vtt_PwrGd#/PD
IN
11
VDD48
12
FSLA/USB_48MHz
13
GND
PWR
14
DOTT_96MHzL
OUT
15
DOTC_96MHzL
OUT
16
FSLB/TEST_MODE
17
27FIX/LCD_SSCGT/PCIeT_L0
OUT
18
27SS/LCD_SSCGC/PCIeC_L0
OUT
19
PCIeT_L1
OUT
20
PCIeC_L1
OUT
21
VDDPCIEX
PWR
22
PCIeT_L2
OUT
23
PCIeC_L2
OUT
24
PCIeT_L3
OUT
25
PCIeC_L3
OUT
26
SATACLKT_L
OUT
27
SATACLKC_L
OUT
28
VDDPCIEX
PWR
I/O
PWR
PWR
PWR
I/O
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z
and REF/N divider mode while in test mode. Refer to Test Clarification Table.
27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True
clock of low power PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
27MHz Spreading Push-Pull output / Complementary clock of LCDCLK_SS output /
Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
Power supply for PCI Express clocks, nominal 3.3V
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed)
Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND
needed)
Power supply for PCI Express clocks, nominal 3.3V
1346—10/23/07
2
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
Pin Description (Continued)
PIN #
TYPE
DESCRIPTION
29
GND
PIN NAME
PWR
30
PCIeC_L4
OUT
31
PCIeT_L4
OUT
32
PEREQ2#/PCIeC_L5
I/O
33
PEREQ1#/PCIeT_L5
I/O
34
VDDPCIEX
PWR
35
CPUITPC_L2/PCIeC_L6
OUT
36
CPUITPT_L2/PCIeT_L6
OUT
37
38
39
VDDA
GNDA
VDD
PWR
PWR
PWR
40
CPUC_L1
OUT
41
CPUT_L1
OUT
42
VDDCPU
PWR
43
CPUC_L0
OUT
44
CPUT_L0
OUT
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REF0
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
REF1/FSLC/TEST_SEL
54
CPU_STOP#
IN
55
PCI&PCIEX_STOP#
IN
56
PCICLK2/REQ_SEL**
I/O
Ground pin.
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled. / Complement clock of differential low power PCI Express output.
No 50ohm resistor to GND needed.
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled. / True clock of differential low power PCI Express output. No
50ohm resistor to GND needed.
Power supply for PCI Express clocks, nominal 3.3V
Complement clock of differential pair CPU output. / Complement clock of differential
PCIEX pair. These are 0.8V push pull outputs. No 50ohm resistor to GND needed.
True clock of differential pair CPU output. / True clock of differential PCIEX pair. These
are 0.8V push pull outputs. No 50ohm resistor to GND needed.
3.3V power for the PLL core.
Ground pin for the PLL core.
Power supply, nominal 3.3V
Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor
to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs. No 50 ohm resistor to GND
needed.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor
to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND
needed.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched
input to enable test mode. Refer to Test Clarification Table
Stops all CPU clocks, except those set to be free running clocks
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by
this input.
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
I/O
1346—10/23/07
3
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
General Description
ICS9LPR426A is a low power CK410M-compliant clock specification. This clock synthesizer provides a single chip solution
for next generation P4 Intel processors and Intel chipsets. ICS9LPR426A is driven with a 14.318MHz crystal.
Block Diagram
Frequency
Dividers
Fixed PLL
X1
X2
USB_48MHz
XTAL
REF(1:0)
CPUCLKT (1:0)
SCLK
SDATA
FSLA
FSLB
FSLC
PEREQ#(2:1)
CPU_STOP#
PCI/PCIEX_STOP#
ITP_EN
REQ_SEL
TEST_SEL
TEST_MODE
CPUCLKC (1:0)
PLL
Array
Programmable
Frequency
Divider
Array
Control
Logic
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
PCICLK_F(1:0)
STOP
Logic
PCICLK (5:2)
PCIEXT (5:1)
PCIEXC (5:1)
SATACLKT
Vtt_Pwr_GD/PD#
SATACLKC
27FIX/LCD_SSCGT/PCIEX0T
27SS/LCD_SSCGC/PCIEX0C
M and N programming range
M
3
4
5
6
7
8
9
10
11
12
13
Minimum
N
200
150
120
100
85
75
66
60
54
50
46
Maximum
N
400
300
240
200
171
150
133
120
109
100
92
M
14
15
16
17
18
19
20
21
22
23
24
Yellow range is programming with more margin
1346—10/23/07
4
Minimum
N
42
40
37
35
33
31
30
28
27
26
25
Maximum
N
85
80
75
70
66
63
60
57
54
52
50
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
FS4
(B0b4)
FS3 (B0b3)
FS LC
(B0b2)
FSLB
(B0b1)
FSLA
(B0b0)
CPU
MHz
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
269.33
271.99
274.66
277.33
279.99
282.66
285.33
287.99
269.33
271.99
274.66
277.33
279.99
282.66
285.33
287.99
1346—10/23/07
5
Spread %
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
CPU PLL Spread Depends on PCI PLL Spread
Table 1: CPU PLL Spread Frequency Selection Table
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
Table2: PCIEX PLL Spread and Frequency Selection Table
FS4
(B19b4)
FS3
(B19b3)
FSLC
(B19b2)
FSLB
(B19b1)
FSLA
(B19b0)
PCIEX
MHz
Spread
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
99.75
100.00
101.75
102.74
103.74
104.74
105.74
106.73
107.73
108.73
109.73
110.72
111.72
112.72
113.72
114.71
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
1346—10/23/07
6
115.71
PCIEX PLL Spread Depends on PCI PLL Spread
%
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
Table3: SATA PLL Spread and Frequency Selection Table
Bit 2
FS3
B22b2
(B31b6)
(Hardwired Low = 0)
Bit 1
Bit 0
(Hardwired (Hardwired
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1346—10/23/07
7
SATA
MHz
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
Pin 17/18
MHz
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
27.00
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*
100.00
N/A*
Spread
%
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
+/- 0.3 Center
+/- 0.3 Center
+/- 0.3 Center
+/- 0.3 Center
+/- 0.3 Center
+/- 0.3 Center
+/- 0.3 Center
+/- 0.3 Center
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
SELPCIEX_LCD# and SELLCD_27# definition:
SELPCIEX_LCD#
SELLCD_27#
Pin #17/18
0
0
27MHzFixed/27MHz_SS pair
SATA source
PCI PLL
0
1
LCD_SST/C pair
SATA PLL
1
0
PCIe0T/C
SATA PLL
1
1
PCIe0T/C
SATA PLL
Table4: PCI PLL Spread and Frequency Selection Table
Bit 3
Bit 4
Bit 2
(Hardwired
(Hardwired Low = 0)
(Hardwired Low = 0)
Low = 0)
FSLB
(B22b1)
FSLA
(B22b0)
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1346—10/23/07
8
PCI
LCD/SATA
Spread
MHz
MHz
%
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
33.33
100.00
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
+/- 0.25% Center
+/- 0.5% Center
+/- .3% Center
1% down
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
General I2C serial interface information for the ICS9LPR426A
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
1346—10/23/07
9
Not acknowledge
stoP bit
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
I2C Table: Frequency Select Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
ROD
SS_EN2
Reserved
FS4
FS3
FSLC
FSLB
FSLA
0
Disable
OFF
-
1
Enable
ON
-
Control Function
Reset on Demand
PCI PLL Spread Enable
Reserved
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Control Function
Output Control
Select I2c readback from
Reserved
PCIEX PLL M/N Enable
Reserved
Strength Programming
Stop all PCI and PCIEX clocks
CPU PLL M/N Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Shadow RAM
Disable
1X
Outputs Stopped
Disable
1
Enable
Active RAM
Enable
2X
Outputs Active
Enable
PWD
1
1
X
0
X
0
1
0
Control Function
Output Control
Type
RW
0
Disable
1
Enable
PWD
1
Output Control
RW
Disable
Enable
1
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
Control Function
Output Control
Output Control
Output Control
Output Control
Reserved
Reserved
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
1
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
X
X
1
Output Control
0
Disable
Disable
Disable
Disable
Disable
Disable
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
PWD
1
1
1
1
R
LCDCLK
PCIEX0
latch
RW
RW
RW
Disable
-
Enable
-
1
X
X
See Table 1: Frequency Selection Table
PWD
0
1
X
0
0
Latch
Latch
Latch
I2C Table: Output Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Dot96Mhz
I2C RB
Reserved
PCIEX PLL MNEN
Reserved
REF0 STRENGTH
PCI/PCIEX_STOP#
CPU PLL MNEN
I2C Table: Output Control Register
Byte 2
Name
USB_48Mhz
Bit 7
CPUCLK2_ITP /
Bit 6
PCIEXT/C6
SATACLKT/C
Bit 5
REF1
Bit 4
PCICLK5
Bit 3
PCICLK4
Bit 2
PCICLK3
Bit 1
PCICLK2
Bit 0
I2C Table: Output Control Register
Byte 3
Name
PCICLK1
Bit 7
PCICLK0
Bit 6
PCIEXT/C5
Bit 5
PCIEXT/C4
Bit 4
Reserved
Bit 3
Reserved
Bit 2
PCIEXT/C3
Bit 1
PCIEXT/C2
Bit 0
I2C Table: Output Control Register
Name
Byte 4
PCIEXT/C1
Bit 7
REF0
Bit 6
CPUCLK1
Bit 5
CPUCLK0
Bit 4
Bit 3
SEL PCIEX_LCDCLK#
Bit 2
Bit 1
Bit 0
PCIEXT/C0
Reserved
Reserved
Control Function
Output Control
Output Control
Output Control
Output Control
Selects PCIEX or LCD/27MHz on pins
17 and 18
Output Control
Reserved
Reserved
1346—10/23/07
10
1
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
I2C Table: Output Control Register
Byte 5
Name
PCIEXT/C4
Bit 7
Reserved
Bit 6
Reserved
Bit 5
SATACLK
Bit 4
PCIEXT/C3
Bit 3
PCIEXT/C2
Bit 2
PCIEXT/C1
Bit 1
PCIEXT/C0
Bit 0
0
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
PWD
0
X
X
0
0
0
0
0
0
00 = 700mV
10 = 800mV
00 = 700mV
10 = 800mV
00 = 700mV
10 = 800mV
1
01 = 900mV
11 = 1000mV
01 = 900mV
11 = 1000mV
01 = 900mV
11 = 1000mV
PWD
0
0
X
X
0
0
0
0
Type
R
R
R
R
R
R
R
R
0
001 = ICS
-
1
-
PWD
0
0
0
0
0
0
0
1
Type
R
R
R
RW
RW
RW
RW
RW
0
1
PWD
0
0
0
0
1
1
1
1
Control Function
Allow assertion of PCI_STOP# or
setting of PCI_STOP control bit in I2C
register to stop PCIEX clocks.
RW
RW
RW
RW
RW
RW
RW
RW
I2C Table: Amplitude Control Register
Byte 6
Name
Control Function
Type
Diff AMP
RW
CPU Differential output Amplitude
Bit 7
Control
Diff AMP
RW
Bit 6
Reserved
Reserved
RW
Bit 5
Reserved
Reserved
RW
Bit 4
Diff AMP
RW
DOT96 Differential output Amplitude
Bit 3
Control
Diff AMP
RW
Bit 2
Diff AMP
SATACLK Differential output Amplitude RW
Bit 1
Control
Diff AMP
RW
Bit 0
I2C Table: Revision and Vendor ID Register
Byte 7
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
I2C Table: Byte Count Register
Byte 8
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Revision ID
VENDOR ID
Control Function
Byte Count Programming b(7:0)
I2C Table: Watch Dog Timer Control Register
Byte 9
Name
Control Function
HWD_EN
Watchdog Hard Alarm Enable
Bit 7
SWD_EN
Watchdog Soft Alarm Enable
Bit 6
WD Hard Status
WD Hard Alarm Status
Bit 5
WD Soft Status
WD Soft Alarm Status
Bit 4
WDTCtrl
Watch Dog Alarm Time base Control
Bit 3
HWD2
WD Hard Alarm Timer Bit 2
Bit 2
HWD1
WD Hard Alarm Timer Bit 1
Bit 1
HWD0
WD Hard Alarm Timer Bit 0
Bit 0
1346—10/23/07
11
Writing to this register will configure how many bytes will be
read back, default is 0F = 15 bytes.
0
1
Type
Disable
Enable
RW
Enable
Disable
RW
Normal
Alarm
R
Normal
Alarm
R
1160ms Base
290ms Base
RW
RW These bits represent X*290ms (or 1.16S) the watchdog timer
waits before it goes to alarm mode. Default is 7 X 290ms =
RW
2s.
RW
PWD
0
0
X
X
0
1
1
1
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
I2C Table: WD Safe Frequency Control Register
Byte 10
Name
Control Function
SWD2
WD Soft Alarm Timer Bit 2
Bit 7
SWD1
WD Soft Alarm Timer Bit 1
Bit 6
SWD0
WD Soft Alarm Timer Bit 0
Bit 5
WD SF4
Bit 4
WD SF3
Bit 3
Watch Dog Safe Freq Programming
WD SF2
Bit 2
bits
WD SF1
Bit 1
WD SF0
Bit 0
Type
1
0
RW These bits represent X*290ms (or 1.16S) the watchdog timer
RW
waits before it goes to alarm mode. Default is 7 X 290ms =
2s.
RW
RW
RW
Writing to these bit will configure the safe frequency as
RW
Byte10 bit (4:0).
RW
RW
PWD
1
1
1
0
0
0
0
0
I2C Table: CPU PLL Frequency Control Register
Byte 11
Name
Control Function
N Div2
N Divider Prog bit 2
Bit 7
N Div1
N Divider Prog bit 1
Bit 6
M Div5
Bit 5
M Div4
Bit 4
M Divider Programming
M Div3
Bit 3
bit (5:0)
M Div2
Bit 2
M Div1
Bit 1
M Div0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
I2C Table: CPU PLL Frequency Control Register:
Byte 12
Name
Control Function
Type
N Div10
RW
Bit 7
N Div9
RW
Bit 6
N Div8
RW
Bit 5
N Div7
N Divider Programming Byte12 bit(7:0) RW
Bit 4
and Byte11 bit(7:6)
N Div6
RW
Bit 3
N Div5
RW
Bit 2
N Div4
RW
Bit 1
N Div3
RW
Bit 0
0
1
The decimal representation of M and N Divider in Byte 11
and 12 will configure the CPU PLL VCO frequency. Default
at power up = latch-in or Byte 0 Rom table. VCO Frequency
= 24 x Ndiv(10:0)/Mdiv(5:0)
0
1
The decimal representation of M and N Divider in Byte 11
and 12 will configure the CPU PLL VCO frequency. Default
at power up = latch-in or Byte 0 Rom table. VCO Frequency
= 24 x Ndiv(10:0)/Mdiv(5:0)
PWD
X
X
X
X
X
X
X
X
I2C Table: PCI PLL Spread Spectrum Control Register
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
Spread Spectrum Programming
bit(7:0)
0
1
These Spread Spectrum bits in Byte 13 and 14 will program
the spread percentage of PCI PLL
PWD
X
X
X
X
X
X
X
X
I2C Table: PCI PLL Spread Spectrum Control Register
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
Spread Spectrum Programming
bit(14:8)
1346—10/23/07
12
0
1
These Spread Spectrum bits in Byte 13 and 14 will program
the spread percentage of PCI PLL
PWD
0
X
X
X
X
X
X
X
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
I2C Table: PCIEX PLL Frequency Control Register
Byte 15
Name
Control Function
N Div2
N Divider Prog bit 2
Bit 7
N Div1
N Divider Prog bit 1
Bit 6
M Div5
Bit 5
M Div4
Bit 4
M Divider Programming
M Div3
Bit 3
bit (5:0)
M Div2
Bit 2
M Div1
Bit 1
M Div0
Bit 0
0
1
Type
RW
RW
RW
The decimal representation of M and N Divider in Byte 15
RW and 16 will configure the PCI PLL VCO frequency. Default at
power up = latch-in or Byte 0 Rom table. VCO Frequency =
RW
24 x Ndiv(10:0)/Mdiv(5:0)
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
I2C Table: PCIEX PLL Frequency Control Register:
0
1
Byte 16
Name
Control Function
Type
N Div10
RW
Bit 7
N Div9
RW
Bit 6
N Div8
RW
The decimal representation of M and N Divider in Byte 15
Bit 5
N Divider Programming Byte16 bit(7:0) RW and 16 will configure the PCI PLL VCO frequency. Default at
N Div7
Bit 4
power up = latch-in or Byte 0 Rom table. VCO Frequency =
and Byte15 bit(7:6)
N Div6
RW
Bit 3
24 x Ndiv(10:0)/Mdiv(5:0)
N Div5
RW
Bit 2
N Div4
RW
Bit 1
N Div3
RW
Bit 0
PWD
X
X
X
X
X
X
X
X
Bytes 17,18 are reserved
I2C Table: PCIEX PLL Frequency Select Select Register
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
FS4
FS3
FSLC
FSLB
FSLA
I2C Table: Output Control Register
Byte 20
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
Bit 0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
1x
Free-Running
Load
Free-Running
Free-Running
1
2x
Stoppable
Do not Load
Stoppable
Stoppable
PWD
0
0
0
0
1
1
0
RW
Disable
Enable
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
1
1
1
1
1
1
1
1
Strength Control
CPU_1
Load Control
CPUCLK_2/ITP
Reserved
Reserved
CPUCLK_0
Free running Control
IIC Load control
Free-Running Controls
Reserved
Reserved
Free Running Controls
Reset Synchronization upon Reset
(Byte 21)
I2C Table: Synchronization Control Register
Byte 21
Name
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
1
-
Type
RW
RW
RW
RW
RW
RW
RW
RW
48Mhz
RESET Sync
0
-
Control Function
Reserved
Reserved
Reserved
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1346—10/23/07
13
See Table 2: PCIEX PLL Frequency Selection Table
PWD
0
0
0
0
0
Latch
Latch
Latch
ICS9LPR426A
Advance Information
Integrated
Circuit
Systems, Inc.
I2C Table: Output Control Register
Byte 22
Name
PCIEXT/C5
Bit 7
PCIEXT/C6
Bit 6
PCICLK_F1
Bit 5
PCICLK_F0
Bit 4
REF1
Bit 3
Reserved
Bit 2
PCI PLL Freq. Select
Bit 1
PCI PLL Freq. Select
Bit 0
Control Function
Free- Running Control
Free- Running Control
Free- Running Control
Free- Running Control
Strength Control
Reserved
Freq Select Bit 1
Freq Select Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Free-Running
Free-Running
Free-Running
Free-Running
1X
-
1
Stoppable
Stoppable
Stoppable
Stoppable
2X
-
See Table 4: PCI PLL Frequency Selection Table
PWD
0
0
0
0
0
X
0
0
Bytes 23-27 are reserved
I2C Table: Programmable output divider Register
Byte 28
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
Control Function
Reserved
Reserved
Reserved
Reserved
CPU Divider Ratio Programming Bits
for CPU PLL
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0000:/2
0001:/3
0010:/5
0011:/7
1100:/16
1101:/24
1110:/40
1111:/56
PWD
X
X
X
X
X
X
X
X
1100:/16
1101:/24
1110:/40
1111:/56
PWD
X
X
X
X
X
X
X
X
1100:/N/A
1101:/24
1110:/72
1111:/N/A
PWD
X
X
X
X
X
X
X
X
1
0100:/4
0101:/6
0110:/10
0111:/14
1000:/8
1001:/12
1010:/20
1011:/28
I2C Table: Programmable output divider Register
Byte 29
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
PCIEXDiv3
PCIEXDiv2
PCIEXDiv1
PCIEXDiv0
Type
RW
RW
RW
RW
RW
PCIEX Divider Ratio Programming Bits RW
for PCIEX PLL
RW
RW
0
-
Control Function
Reserved
Reserved
Reserved
Reserved
0000:/2
0001:/3
0010:/5
0011:/7
1
0100:/4
0101:/6
0110:/10
0111:/14
1000:/8
1001:/12
1010:/20
1011:/28
I2C Table: Programmable output divider Register
Byte 30
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
PCIDiv3
PCIDiv2
PCIDiv1
PCIDiv0
I2C Table: PEREQ# Control Register
Byte 31
Name
SELLCD_27#
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
PEREQ2# Control
Bit 3
PEREQ2# Control
Bit 2
PEREQ1# Control
Bit 1
PEREQ1# Control
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
PCI Divider Ratio Programming Bits
Control Function
Select LCD or 27MHz for pins 17/18
Reserved
Reserved
Reserved
PCIEX6 is controlled
PCIEX1 is controlled
PCIEX4 is controlled
PCIEX0 is controlled
1346—10/23/07
14
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
R
RW
RW
RW
RW
RW
RW
RW
0
0000:/N/A
0001:/3
0010:/9
0011:/N/A
1
0100:/N/A
0101:/6
0110:/18
0111:/N/A
0
27MHz
Not Controlled
Not Controlled
Not Controlled
Not Controlled
1000:/N/A
1001:/12
1010:/36
1011:/N/A
1
LCDCLK
Controlled
Controlled
Controlled
Controlled
PWD
latch
X
X
X
0
0
0
0
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I2C Table: Skew programming Register
Byte 32
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
CPUCLK0 Skew Control (ps)
CPUCLK1 Skew Control (ps)
1346—10/23/07
15
0
0000:0
0001:100
0010:200
0011:300
0000:0
0001:100
0010:200
0011:300
1
0100:400
0101:500
0110:600
0111:700
0100:400
0101:500
0110:600
0111:700
1000:800
1001:900
1010:1000
1011:1100
1000:800
1001:900
1010:1000
1011:1100
1100:1200
1101:1300
1110:1400
1111:1500
1100:1200
1101:1300
1110:1400
1111:1500
PWD
0
0
0
0
0
0
0
0
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Absolute Maximum Rating
PARAMETER
1
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
VDD + 0.5V
V
1
V
1
°
3.3V Core Supply Voltage
3.3V Logic Input Supply
Voltage
Storage Temperature
VDD_A
-
VDD_In
-
Ts
-
-65
150
C
1
Ambient Operating Temp
Tambient
-
0
70
°C
1
Case Temperature
Tcase
-
115
°C
1
Input ESD protection HBM
ESD prot
-
V
1
GND - 0.5
VDD + 0.5V
2000
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
MAX
UNITS
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
-5
uA
1
-200
uA
1
IIL1
Input Low Current
IIL2
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
Operating Supply Current
Operating Current
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
TYP
Notes
VIH_FS
3.3 V +/-5%
0.7
VDD + 0.3
V
1
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
1
IDD3.3OP
Full Active, CL = Full load;
175
350
mA
1
IDD3.3OP
all outputs driven
175
400
mA
1
Powerdown Current
IDD3.3PD
all diff pairs driven
2
70
mA
1
Input Frequency
Fi
VDD = 3.3 V
14.31818
MHz
2
Pin Inductance
Lpin
7
nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
5
pF
1
1.8
ms
1
33
kHz
1
300
us
1
Tfall_PD
X1 & X2 pins
From VDD Power-Up or deassertion of PD to 1st clock
Triangular Modulation
CPU output enable after
PD de-assertion
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
Input Capacitance
Clk Stabilization
TSTAB
Modulation Frequency
Tdrive_PD
SMBus Voltage
30
2.7
VDD
Low-level Output Voltage
VOL
@ IPULLUP
Current sinking at
IPULLUP
VOL = 0.4 V
SCLK/SDATA
(Max VIL - 0.15) to
TRI2C
Clock/Data Rise Time
(Min VIH + 0.15)
(Min VIH + 0.15) to
SCLK/SDATA
TFI2C
(Max VIL - 0.15)
Clock/Data Fall Time
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
4
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
1346—10/23/07
16
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AC Electrical Characteristics - (CPU, PCIEX, SATACLK, DOT96Mhz)
SYMBOL
tSLR
CONDITIONS
MIN
MAX
UNITS
NOTES
Rising Edge Slew Rate
PARAMETER
Differential Measurement
2.5
8
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
2.5
8
V/ns
1,2
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
Crossing Point Voltage
VXABS
Single-ended Measurement
300
Crossing Point Variation
VXABSVAR
Single-ended Measurement
Duty Cycle
DCYC
Differential Measurement
CPU Jitter - Cycle to Cycle
CPUJC2C
SRC Jitter - Cycle to Cycle
mV
1
550
mV
1,3,4
140
mV
1,3,5
55
%
1
Differential Measurement
85
ps
1
SRCJC2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
250
ps
1
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC Skew
SRCSKEW
Differential Measurement
TBD
ps
1
45
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Electrical Characteristics - PCICLK/PCICLK_F
SYMBOL
RDSP
CONDITIONS*
VO = VDD*(0.5)
MIN
Output Impedance
PARAMETER
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
TYP
12
MAX
UNITS
NOTES
55
Ω
1
V
1
0.55
V OH @MIN = 1.0 V
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
Output Low Current
IOL
Edge Rate
tslewr/f
Rising/Falling edge rate
Rise Time
tr
Fall Time
-33
30
VOL @ MAX = 0.4 V
V
1
mA
1
mA
1
mA
1
38
mA
1
1
4
V/ns
1
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
1
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Group Skew
tskew
VT = 1.5 V
250
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
3
Spread Spectrum is off
1346—10/23/07
17
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Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER
SYMBOL
CONDITIONS*
MIN
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
1,2
Clock period
Tperiod
48.00MHz output nominal
20.8313
20.8354
ns
2
Output Impedance
RDSP
VO = VDD*(0.5)
12
55
Ω
1
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
V
1
Output High Current
IOH
mA
1
mA
1
mA
1
TYP
0.55
V OH @MIN = 1.0 V
-33
VOH@MAX = 3.135 V
-33
VOL @ MIN = 1.95 V
Output Low Current
IOL
Edge Rate
tslewr/f
Rising/Falling edge rate
Edge Rate
tslewr/f_USB
Rise Time
Fall Time
30
VOL @ MAX = 0.4 V
38
mA
1
1
4
V/ns
1
USB48 Rising/Falling edge rate
1
2
V/ns
1
tr
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
1
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Rise Time
tr_USB
VOL = 0.4 V, VOH = 2.4 V
1
2
ns
1
Fall Time
tf_USB
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Group Skew
tskew
VT = 1.5 V
250
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only)
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
TYP
300
ppm
1,2
Clock period
Tperiod
14.318MHz output nominal
69.8270
69.8550
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
Output Low Current
IOL
Edge Rate
tslewr/f
Rise Time
tr1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
Skew
tsk1
VT = 1.5 V
Duty Cycle
dt1
VT = 1.5 V
Jitter
tjcyc-cyc
VT = 1.5 V
V
1
0.4
V
1
-29
-23
mA
1
29
27
mA
1
Rising/Falling edge rate
1
4
V/ns
1
VOL = 0.4 V, VOH = 2.4 V
1
2
ns
1
1
2
ns
1
500
ps
1
55
%
1
1000
ps
1
VOL @MIN = 1.95 V,
@MAX = 0.4 V
VOL
45
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
1346—10/23/07
18
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Test Clarification Table
HW
Comments
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MODE
HW PIN
<2.0V
X
OUTPUT
NORMAL
>2.0V
0
HI-Z
>2.0V
1
REF/N
1346—10/23/07
19
ICS9LPR426A
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56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
aaa
-0.10
-.004
c
N
L
E1
E
INDEX
AREA
1 2
D
A
A2
A1
VARIATIONS
-C-
N
e
SEATING
PLANE
b
56
D mm.
MIN
MAX
13.90
14.10
Reference Doc.: JEDEC Publication 95, M O-153
aaa C
10-0039
Ordering Information
ICS9LPR426AGLF-T
Example:
ICS XXXX A G LF- T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator
Device Type
Prefix
ICS = Standard Device
1346—10/23/07
20
D (inch)
MIN
.547
MAX
.555
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Revision History
Rev.
0.1
0.2
0.3
0.4
0.5
0.6
Issue Date Description
05/09/07 Initial Release
06/04/07 Updated SMBUS
1. Updated Output Features.
06/22/07 2. Updated Block Diagram
08/21/07 Added Test Clarification Table.
09/14/07 Updated Electrical Characteristics.
10/23/07 Added Programming Range Table
1346—10/23/07
21
Page #
Various
1,
4
19
16
4