IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS FEATURES: DESCRIPTION: • Input frequency: - For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, or 622.08MHz - For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz, 333.26MHz, or 666.52MHz - For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz, 312.5MHz, or 625MHz - For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz, 322.26MHz, or 644.53MHz • 3-level inputs for feedback divide ratio and output frequency range selection • 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT • Regenerated input clock or QOUT/4 on QREG • Lock indicator • Power-down mode • LVPECL or LVDS outputs • Three modes of output frequency range - Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version of the input clock. - Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz. - Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version of the input clock frequency. • Selectable loop bandwidths • Hitless switchover • Differential LVPECL, LVDS, or single-ended LVTTL input interface • 2.375 - 3.465V core and I/O • Available in VFQFPN package The IDT5T940 generates a high precision FEC (Forward Error Correction) or non-FEC source clock for SONET/SDH systems as well as a source clock for Gigabit Ethernet systems. This device also has clock regeneration capability: it creates a "clean" version of the clock input by using the internal oscillator to square the input clock's rising and falling edges and remove jitter. In the event that the main clock input fails, the device automatically locks to a backup reference clock using a hitless switchover mechanism. This device detects loss of valid CLKIN and leaves the VCO of the PLL at the last valid frequency while an alternate input REFIN is selected. If CLKIN and REFIN are different frequencies, the multiplication factor will be adjusted to retain the same output frequency. The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10 has LVDS outputs and the IDT5T940-30 has LVPECL outputs. The three modes of output frequency range are controlled by the SELmode, which is a 3-level pin. When SELmode is high or low, the QOUT is a multiplied version of the input clock while QREG is a regenerated version of the input clock. When SELmode is mid, the QOUT is a multiplied version of the input clock while QREG is QOUT/4. The IDT5T940 features a selectable loop bandwidth. APPLICATIONS: • • • • • Terabit routers Gigabit ethernet systems SONET / SDH systems Digital cross connects Optical transceiver modules FUNCTIONAL BLOCK DIAGRAM PLLBW1 CLKIN CLKIN PLLBW0 QREG INPUT MUX DIVN PLL QREG QOUT DIVM REFIN REFIN QOUT CONTROL LOGIC LOCK, FREQ. DETECTOR PD SELMODE LOCK CLK/ REF0 CLK/ REF1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE DECEMBER 2003 1 c 2003 Integrated Device Technology, Inc. DSC 6195/23 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) PD VDD GND QOUT QOUT GND VDD Symbol 28 27 26 25 24 23 22 GND 1 21 VDD CLKIN 2 20 GND CLKIN 3 19 QREG GND 4 18 QREG REFIN 5 17 GND REFIN 6 16 VDD GND 7 15 LOCK GND Max Unit VDD Power Supply Voltage –0.5 to +4.1 V VI Input Voltage –0.5 to +4.1 V VO Output Voltage –0.5 to VDD+0.5 V TJ Junction Temperature 150 °C TSTG Storage Temperature –65 to +165 °C NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 14 CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) Parameter PLLBW1 13 PLLBW0 12 VDD 11 SELMODE 10 CLK/REF0 9 CLK/REF1 VDD 8 Description Typ. Max. Unit CIN Input Capacitance Description 2.5 3 pF COUT Output Capacitance — — pF NOTE: 1. Capacitance applies to all inputs except CLK/REF[1:0] and SELmode. VFQFPN TOP VIEW RECOMMENDED OPERATING RANGE Symbol Description Min. Typ. Max. Unit TA Ambient Operating Temperature –40 +25 +85 °C VDD Power Supply Voltage 2.375 — 3.465 V VT Termination Voltage (LVPECL) — VDD – 2 — V Termination Voltage (LVDS) — 1.2 — 2 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE PLL BANDWIDTH SELECTION PLLBW[1:0] Min. Max. Min. CLKIN/REFIN OUTPUT FREQUENCY RANGE SELmode QOUT/QOUT QREG/QREG Unit LL 65KHz 120KHz 19.44MHz L 155.5 - 166.6 regenerated CLKIN/CLKIN MHz LH 250KHz 500KHz 19.44MHz M 622 - 666.5 155.5 - 166.6 MHz HL 1MHz 2MHz 38.88MHz H 622 - 666.5 regenerated CLKIN/CLKIN MHz HH 4MHz 8MHz 155.52MHz LOCK FREQUENCY DETECTOR INPUT FREQUENCY RANGE CLK/REF[1:0] Input Frequency Range HH 19.4MHz - 20.9MHz HM reserved HL 38.8MHz - 41.7MHz MH 77.7MHz - 83.4MHz MM Automatic Detection ML 155.5MHz - 167MHz LH 311MHz - 334MHz LM reserved LL 622MHz - 667MHz The 5T940 will lock to, and track, a valid CLKIN signal; LOCK will be low when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch to lock to REFIN without generating any glitches on the output. The fact that the PLL is locked to REFIN rather than CLKIN is indicated by a high state on LOCK. When a valid input is then applied to CLKIN, the 5T940 will smoothly switch back to locking on CLKIN, and LOCK will go low. LOCK will also switch to high should the frequency of CLKIN drift close to the limits of the VCO tuning range. PIN DESCRIPTION Pin Name I/O Type CLKIN, CLKIN I Adjustable(1) Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the floating input. Description REFIN, REFIN I Adjustable(1) Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the floating input. CLK/REF[1:0] I 3-level(2) 3 level inputs controlling PLL feedback divider ratio. Automatic detection is used if both inputs are MID. SELmode I 3-level(2) 3 level input to select output frequency range for QOUT/QOUT and QREG/QREG (see Output Frequency Range table) PLLBW[1:0] I LVTTL PLL Bandwidth Select Inputs (see PLL Bandwidth Selection table) Power Down Control. Shuts off entire chip when LOW. PD I LVTTL QOUT, QOUT 0 Adjustable(3) Differential clock output. LVPECL or LVDS outputs. QREG, QREG 0 Adjustable Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs. LOCK 0 LVTTL LOW when PLL is locked to CLKIN, HIGH in all other conditions VDD PWR Power Supply GND PWR Ground (3) NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V LVTTL levels Single-ended 2.5V LVTTL levels Differential LVPECL levels Differential LVDS levels 2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. 3. Outputs can be LVPECL or LVDS. 3 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION Application Non-FEC REFIN (MHz) 19.44, 38.88, 77.76, 155.52, 311.04, 622.08 CKIN (MHz) SELmode 19.44 LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH 38.88 77.76 155.52 311.04 622.08 FEC 20.83, 41.66, 83.31, 166.63, 333.26, 666.52 20.83 41.66 83.31 166.63 333.26 666.52 4 QREG (MHz) QOUT (MHz) 19.44 155.52 19.44 38.88 155.52 38.88 77.76 155.52 77.76 155.52 155.52 155.52 311.04 155.52 311.04 622.08 155.52 622.08 20.83 166.63 20.83 41.66 166.63 41.66 83.31 166.63 83.31 166.63 166.63 166.63 333.26 166.63 333.26 666.52 166.63 666.52 155.52 622.08 622.08 155.52 622.08 622.08 155.52 622.08 622.08 155.52 622.08 622.08 155.52 622.08 622.08 155.52 622.08 622.08 166.63 666.52 666.52 166.63 666.52 666.52 166.63 666.52 666.52 166.63 666.52 666.52 166.63 666.52 666.52 166.63 666.52 666.52 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION (CONTINUED) Application REFIN (MHz) 10GE copper 19.53, 39.06, 78.12, 156.25, 312.5, 625 CKIN (MHz) SEL mode 19.53 LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH 39.06 78.12 156.25 312.5 625 10GE optical 20.14, 40.28, 80.56, 161.13, 322.26, 644.53 20.14 40.28 80.56 161.13 322.26 644.53 5 QREG (MHz) QOUT (MHz) 19.53 156.25 19.53 39.06 156.25 39.06 78.12 156.25 78.12 156.25 156.25 156.25 312.50 156.25 312.5 625 156.25 625 20.14 161.13 20.14 40.28 161.13 40.28 80.56 161.13 80.56 161.13 161.13 161.13 322.26 161.13 322.26 644.53 161.13 644.53 156.25 625 625 156.25 625 625 156.25 625 625 156.25 625 625 156.25 625 625 156.25 625 625 161.13 644.53 644.53 161.13 644.53 644.53 161.13 644.53 644.53 161.13 644.53 644.53 161.13 644.53 644.53 161.13 644.53 644.53 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS(1,2) Symbol Typ. Max Unit IDD_PD Power Supply Current Parameter VDD = Max., PD = GND, All outputs unloaded Test Conditions — 50 µA ∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 2.375V — 100 µA VDD = Max., QOUT = 622MHz, All outputs unloaded — 200 mA (LVTTL inputs only) ITOT Total Power Supply Current NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. As a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasonable operating temperature. That means that these parts must not burn up under extended use in a typical application. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIHH VIMM VILL I3 Parameter Input HIGH Voltage Level(1) Input MID Voltage Level(1) Input LOW Voltage Level(1) 3-Level Input DC Current Test Conditions 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD VIN = VDD/2 VIN = GND Min. VDD – 0.4 VDD/2 – 0.2 — — –50 –200 HIGH Level MID Level LOW Level Max — VDD/2 + 0.2 0.4 200 +50 — Unit V V V µA NOTE: 1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the PLL may require additional tAQ time before all datasheet limits are achieved. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL Symbol IIH IIL VIK VIN VIH VIL Parameter Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH DC Input LOW Test Conditions VDD = 3.465V VDD = 3.465V VDD = 2.375V, IIN = -18mA Min. — — — - 0.3 1.7 — Typ. — — - 0.7 — — — Max ±1 ±1 - 1.2 +3.465 — 0.7 Unit µA V V V V DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVPECL(1) Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD = 3.465V -20 — +20 µA Input Characteristics IIN Input Current (CLKIN, REFIN) VCMR Common Mode Input Voltage VDIF Differential Voltage Required to Toggle Input 1 — VDD - 0.3 V 100 — — mV Output Characteristics VOH Output Voltage HIGH (terminated through 50Ω tied to VDD - 2V)(2) VDD - 1.15 — VDD - 0.9 V VOL Output Voltage LOW (terminated through 50Ω tied to VDD - 2V)(2) VDD - 1.95 — VDD - 1.61 V 0.55 — 0.93 V VSWING Peak-to-Peak Output Voltage Swing NOTES: 1. VDD = 2.375 - 3.645V. 2. Not to exceed VDD - 0.05V. 6 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVDS Symbol Parameter Test Conditions Min. VDD = 3.465V Typ. Max. Unit Input Characteristics -20 — +20 µA VCM Common Mode Input Voltage Range(1) 0.9 — VDD - 0.05 V VDIF Differential Voltage Required to Toggle Input 100 — — mV IIN Input Current (CLKIN, REFIN) Output Characteristics VOT(+) Differential Output Voltage for the TRUE Binary State 247 — 454 mV VOT(-) Differential Output Voltage for the FALSE Binary State -247 — -454 mV ∆VOT Change in VOT Between Complementary Output States — — 50 mV VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V ∆VOS Change in VOS Between Complementary Output States IOS Outputs Short Circuit Current IOSD Differential Outputs Short Circuit Current — — 50 mV VOUT(+) and VOUT(-) = 0V — 9 24 mA VOUT(+) = VOUT(-) — 6 12 mA Min. Typ. Max. Unit 40 50 60 % NOTE: 1. Not to exceed VDD - 0.05V. INPUT TIMING REQUIREMENTS Symbol Parameter REFH Input Reference Clock Duty Cycle FREF Input Reference Clock Range 19.44 — 666.52 MHz REFTOL Input Reference Clock Frequency Tolerance -100 — 100 ppm FCLKIN Clock in Frequency Range CLKIN H tAQ LOCKTOL tJIT(TOL) 19.44 — 666.52 MHz Clock in Duty Cycle 40 50 60 % Acquisition Time from Return of Valid CLKIN — 60 150 us Frequency Tolerance for LOCK -600 ±450 600 ppm Tolerance to Input Jitter GR-253 Sect. 5.6.2.2 AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-192) Symbol QOUT Parameter Multiplied Clock Output Frequency Min. Typ. Max. SELmode = LOW 155.52 — 166.63 SELmode = MID 155.52 — 666.52 SELmode = HIGH 622.08 — 666.52 Unit MHz QREG Regenerated Clock Output Frequency 19.44 — 666.52 MHz CLKIN Input Clock Frequency 19.44 — 667 MHz LVPECL — 150 — ps LVDS — 100 — LVPECL — 150 — tR Output Rise Time tF Output Fall Time — 100 — tSK Skew between QOUT and QREG — 10 20 ps PLLBW PLL Bandwidth Setting 65 80 120 KHz tP Jitter Transfer Peaking — — 0.1 dB tJ Jitter Generation(1) Output Frequency = 622MHz - 666.5MHz — 0.3 0.65 ps (RMS) (with 50KHz to 80MHz band pass filter) Output Frequency = 155.5MHz - 166.6MHz — 1 2 45 — 55 LVDS tDUTY Output Duty Cycle NOTE: 1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table. 7 ps % IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-48) Symbol Parameter SELmode = LOW QOUT Multiplied Clock Output Frequency QREG Regenerated Clock Output Frequency CLKIN Input Clock Frequency tR Output Rise Time tF Output Fall Time tSK Min. Typ. Max. 155.52 — 166.63 Unit SELmode = MID 155.52 — 666.52 SELmode = HIGH 622.08 — 666.52 MHz 19.44 — 666.52 MHz 19.44 — 667 MHz LVPECL — 150 — ps LVDS — 100 — LVPECL — 150 — LVDS — 100 — ps Skew between QOUT and QREG — 10 20 ps PLLBW PLL Bandwidth Setting 65 80 120 KHz 250 305 500 tP Jitter Transfer Peaking — 0.05 0.1 Output frequency = 622MHz - 666.5MHz — 0.1 0.3 Jitter Generation Output frequency = 155.5MHz - 166.6MHz — 0.4 1.5 (with 12KHz to 20MHz filter)(1) Output frequency = 77.7MHz - 83.4MHz — 0.5 1.7 45 — 55 tJ tDUTY Output Duty Cycle dB ps (RMS) % NOTE: 1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table. AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-12) Symbol Parameter SELmode = LOW QOUT Multiplied Clock Output Frequency Min. Typ. Max. 155.52 — 166.63 SELmode = MID 155.52 — 666.52 SELmode = HIGH 622.08 — 666.52 Unit MHz QREG Regenerated Clock Output Frequency 19.44 — 666.52 MHz CLKIN Input Clock Frequency 19.44 — 667 MHz LVPECL — 150 — ps LVDS — 100 — LVPECL — 150 — LVDS — 100 — — 10 20 65 80 120 tR Output Rise Time tF Output Fall Time tSK Skew between QOUT and QREG PLLBW tP tJ PLL Bandwidth Setting Jitter Transfer Peaking Jitter Generation (with 3KHz to 5MHz filter) tDUTY (1) 250 305 500 1000 1250 2000 — 0.05 0.1 Output frequency = 155.5MHz - 166.6MHz — 0.3 1.1 Output frequency = 77.7MHz - 83.4MHz — 0.4 1.3 Output frequency = 19.4MHz - 20.9MHz — 0.5 1.6 45 — 55 Output Duty Cycle NOTE: 1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table. 8 ps ps KHz dB ps (RMS) % IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE TEST CONDITIONS A LVDS DRIVER 50Ω VDIFF VT TEST POINT 50Ω B Test Circuit for LVDS Output Characteristics A 50Ω VDIFF VT 50Ω B Test Circuit for LVDS Input Characteristics A LVPECL DRIVER 50Ω VDIFF VDD - 2V 50Ω B Test Circuit for LVPECL Output Characteristics A 50Ω VDIFF VB 50Ω B VB = VDD - 2V Test Circuit for LVPECL Input Characteristics 9 IDT5T940 PRECISION CLOCK GENERATOR OC-192 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 I -40°C to +85°C (Industrial) NL Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package 5T940-10 5T940-30 Precision Clock Generator - LVDS Output Precision Clock Generator - LVPECL Output for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 10 for Tech Support: [email protected] (408) 654-6459