RoboClockII™ Junior CY7B9930V CY7B9940V High-Speed Multi-Frequency PLL Clock Buffer Features Functional Description • 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation • Matched pair output skew < 200 ps • Zero input-to-output delay • 10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines • Commercial temp. range with eight outputs at 200 MHz • Industrial temp. range with eight outputs at 200 MHz • 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs • Multiply ratios of (1–6, 8, 10, 12) • Operation up to 12x input frequency • Individual output bank disable for aggressive power management and EMI reduction • Output high-impedance option for testing purposes • Fully integrated PLL with lock indicator • Low cycle-to-cycle jitter (<100 ps peak-peak) • Single 3.3V ± 10% supply • 44-pin TQFP package The CY7B9930V and CY7B9940V High-Speed MultiFrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer or communication systems. Ten configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in three banks. The FB feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12. Any one of these ten outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature that allows smooth change over to secondary clock source, when the primary clock source is not in operation. The reference inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout. Functional Block Diagram Pin Configuration QFA0 QFA1 Divide Matrix 2QA0 2QA1 Bank 2 2QB0 2QB1 DIS2 VCCQ FBKA GND GND QFA1 VCCN QFA0 GND 33 VCCQ 2QB1 2 32 REFA+ VCCN 3 31 REFA – 2QB0 4 30 REFSEL GND 5 29 REFB– Bank 1 CY7B9930V/40V GND 6 28 REFB+ 2QA1 7 27 FS VCCN 8 26 GND 2QA0 9 25 VCCQ GND 10 24 DIS2 GND 11 23 DIS1 1QA0 1QA1 12 13 14 15 16 17 18 19 20 21 22 3901 North First Street • San Jose, CA 95134 GND Output_Mode 1QB1 VCCN 1QB0 GND • GND 1QB0 1QB1 DIS1 Cypress Semiconductor Corporation Document #: 38-07271 Rev. *B FBDS0 1 GND 3 3 44 43 42 41 40 39 38 37 36 35 34 GND 1QA1 FBDS0 FBDS1 3 3 VCCN Feedback Bank FS Output_Mode Control Logic Divide Generator VCO Filter 1QA0 Phase Freq. Detector REFA+ REFA– REFB+ REFB– REFSEL LOCK LOCK FBDS1 44-Pin TQFP FBKA • 408-943-2600 Revised July 25, 2002 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Pin Definitions[1] Name I/O Type Description FBKA Input LVTTL Feedback Input. REFA+, REFA– REFB+, REFB– Input LVTTL/ LVDIFF Reference Inputs: These inputs can operate as differential PECL or single-ended TTL reference inputs to the PLL. When operating as a single-ended LVTTL input, the complementary input must be left open. REFSEL Input LVTTL Reference Select Input: The REFSEL input controls how the reference input is configured. When LOW, it will use the REFA pair as the reference input. When HIGH, it will use the REFB pair as the reference input. This input has an internal pull-down. FS Input 3-level Input Frequency Select: This input must be set according to the nominal frequency (fNOM). See Table 1. FBDS[0:1] Input 3-level Input Feedback Divider Function Select. These inputs determine the function of the QFA0 and QFA1 outputs. See Table 2. DIS[1:2] Input LVTTL Output Disable: Each input controls the state of the respective output bank. When HIGH, the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See Table 3. These inputs each have an internal pull-down. LOCK Output LVTTL PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the reference signal. When LOW, the PLL is attempting to acquire lock. Output_Mode Input Output Mode: This pin determines the clock outputs’ disable state. When this input is HIGH, the clock outputs will disable to high-impedance (HI-Z). When this input is LOW, the clock outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter factory test mode. QFA[0:1] Output LVTTL Clock Feedback Output: This pair of clock outputs is intended to be connected to the FB input. These outputs have numerous divide options. The function is determined by the setting of the FBDS[0:1] pins. [1:2]Q[A:B][0:1] Output LVTTL Clock Output. VCCN 3-Level Input PWR Output Buffer Power: Power supply for each output pair. VCCQ PWR Internal Power: Power supply for the internal circuitry. GND PWR Device Ground. Block Diagram Description VCO, Control Logic, and Divide Generator Phase Frequency Detector and Filter These two blocks accept signals from the REF inputs (REFA+, REFA–, REFB+ or REFB–) and the FB input (FBKA). Correction information is then generated to control the frequency of the Voltage Controlled Oscillator (VCO). These two blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal. The RoboClockII Junior has a flexible REF input scheme. These inputs allow the use of either differential LVPECL or single-ended LVTTL inputs. To configure as single-ended LVTTL inputs, the complementary pin must be left open (internally pulled to 1.5V), then the other input pin can be used as a LVTTL input. The REF inputs are also tolerant to hot insertion. The REF inputs can be changed dynamically. When changing from one reference input to the other reference input of the same frequency, the PLL is optimized to ensure that the clock outputs period will not be less than the calculated system budget (tMIN = tREF (nominal reference clock period) – tCCJ (cycle-to-cycle jitter) – tPDEV (max. period deviation)) while reacquiring lock. The VCO accepts analog control inputs from the PLL filter block. The FS control pin setting determines the nominal operational frequency range of the divide by one output (fNOM) of the device. fNOM is directly related to the VCO frequency. There are two versions of the RoboClockII Junior, a low-speed device (CY7B9930V) where fNOM ranges from 12 MHz to 100 MHz, and a high-speed device (CY7B9940V) which ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table 1. The fNOM frequency is seen on “divide-by-one” outputs. Table 1. Frequency Range Select FS[2] LOW CY7B9930V CY7B9940V fNOM (MHz) fNOM (MHz) Min. Max. Min. Max. 12 26 24 52 MID 24 52 48 100 HIGH 48 100 96 200[3] Note: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO. fNOM always appears on an output when the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided. 3. The maximum output frequency is 200 MHz. Document #: 38-07271 Rev. *B Page 2 of 9 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Divide Matrix Lock Detect Output Description The Divide Matrix is comprised of three independent banks: two banks of clock outputs and one bank for feedback. Each clock output bank has two pairs of low-skew, high-fanout output buffers ([1:2]Q[A:B][0:1]), and an output disable (DIS[1:2]). The LOCK detect output indicates the lock condition of the integrated PLL. Lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. Phase error is declared when the phase difference between the two inputs is greater than the specified device propagation delay limit (tPD). The feedback bank has one pair of low-skew, high-fanout output buffers (QFA[0:1]). One of these outputs may connect to the selected feedback input (FBKA+). This feedback bank also has two divider function selects FBDS[0:1]. The divide capabilities for each bank are shown in Table 2. Table 2. Output Divider Function Function Selects Output Divider Function When in the locked state, after four or more consecutive feedback clock cycles with phase-errors, the LOCK output will be forced LOW to indicate out-of-lock state. When in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the LOCK output to indicate lock condition (LOCK = HIGH). If the feedback clock is removed after LOCK has gone HIGH, a “Watchdog” circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting LOCK LOW. This time out period is based upon a divided down reference clock. FBDS1 FBDS0 Bank1 Bank2 Feedback Bank LOW LOW /1 /1 /1 LOW MID /1 /1 /2 LOW HIGH /1 /1 /3 MID LOW /1 /1 /4 This assumes that there is activity on the selected REF input. If there is no activity on the selected REF input then the LOCK detect pin may not accurately reflect the state of the internal PLL. MID MID /1 /1 /5 Factory Test Mode Description MID HIGH /1 /1 /6 HIGH LOW /1 /1 /8 HIGH MID /1 /1 /10 HIGH HIGH /1 /1 /12 The device will enter factory test mode when the OUTPUT_MODE is driven to MID. In factory test mode, the device will operate with its internal PLL disconnected; input level supplied to the reference input will be used in place of the PLL output. In TEST mode the selected FB input must be tied LOW. All functions of the device are still operational in factory test mode except the internal PLL and output bank disables. The OUTPUT_MODE input is designed to be a static input. Dynamically toggling this input from LOW to HIGH may temporarily cause the device to go into factory test mode (when passing through the MID state). Output Disable Description The outputs of Bank 1 and Bank 2 can be independently put into a HOLD-OFF or high-impedance state. The combination of the Output_Mode and DIS[1:2] inputs determines the clock outputs’ state for each bank. When the DIS[1:2] is LOW, the outputs of the corresponding bank will be enabled. When the DIS[1:2] is HIGH, the outputs for that bank will be disabled to a high-impedance (HI-Z) or HOLD-OFF state depending on the Output_Mode input. Table 3 defines the disabled output functions. The HOLD-OFF state is intended to be a power saving feature. An output bank is disabled to the HOLD-OFF state in a maximum of six output clock cycles from the time when the disable input (DIS[1:2]) is HIGH. When disabled to the HOLD-OFF state, outputs are driven to a logic LOW state on its falling edge. This ensures the output clocks are stopped without glitch. When a bank of outputs is disabled to HI-Z state, the respective bank of outputs will go HI-Z immediately. Table 3. DIS[1:2] Pin Functionality OUTPUT_MODE DIS[1:2]/FBDIS Output Mode HIGH/LOW LOW ENABLED HIGH HIGH HI-Z LOW HIGH HOLD-OFF MID X FACTORY TEST Document #: 38-07271 Rev. *B Factory Test Reset When in factory test mode (OUTPUT_MODE = MID), the device can be reset to a deterministic state by driving the DIS2 input HIGH. When the DIS2 input is driven HIGH in factory test mode, all clock outputs will go to HI-Z; after the selected reference clock pin has 5 positive transitions, all the internal finite state machines (FSM) will be set to a deterministic state. The deterministic state of the state machines will depend on the configurations of the divide selects and frequency select input. All clock outputs will stay in high-impedance mode and all FSMs will stay in the deterministic state until DIS2 is deasserted. When DIS2 is deasserted (with OUTPUT_MODE still at MID), the device will re-enter factory test mode. Page 3 of 9 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Absolute Maximum Conditions Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current.................................................... >±200 mA Storage Temperature .....................................−40°C to +125°C Operating Range Ambient Temperature with Power Applied ..−40°C to +125°C Range Supply Voltage to Ground Potential .................−0.5V to +4.6V Commercial DC Input Voltage ..........................................−0.3V to VCC+0.5V Output Current into Outputs (LOW) .............................40 mA Ambient Temperature VCC 0°C to +70°C 3.3V ±10% –40°C to +85°C 3.3V ±10% Industrial Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VCC = Min., IOH = –30 mA 2.4 – V IOH = –2 mA, VCC = Min. 2.4 – V VCC = Min., IOL= 30 mA – 0.5 V LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK) VOH LVTTL HIGH Voltage QFA[0:1], [1:2]Q[A:B][0:1] VOL LVTTL LOW Voltage QFA[0:1], [1:2]Q[A:B][0:1] IOZ High-Impedance State Leakage Current LOCK LOCK IOL= 2 mA, VCC = Min. – 0.5 V –100 100 µA 2.0 VCC+0.3 V 2.0 VCC+0.3 V –0.3 0.8 V –0.3 0.8 V VCC = GND, VIN = 3.63V – 100 µA LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2]) VIH LVTTL Input HIGH FBKA+, REF[A:B]± Min. < VCC < Max. REFSEL, DIS[1:2] VIL LVTTL Input LOW FBKA+, REF[A:B]± Min. < VCC < Max. REFSEL, DIS[1:2] II LVTTL VIN >VCC FBKA+, REF[A:B]± IlH LVTTL Input HIGH Current FBKA+, REF[A:B]± VCC = Max., VIN = VCC – 500 µA REFSEL, DIS[1:2] VIN = VCC – 500 µA LVTTL Input LOW Current FBKA+, REF[A:B]± VCC = Max., VIN = GND –500 – µA –500 – µA Min. < VCC < Max. 0.87*VCC – V Min. < VCC < Max. 0.47*VCC IlL REFSEL, DIS[1:2] 3-Level Input Pins (FBDS[0:1], FS, Output_Mode) VIHH Three Level Input HIGH[4] MID[4] VIMM Three Level Input VILL Three Level Input LOW[4] Min. < VCC < Max. 0.53*VCC V 0.13*VCC V IIHH Three Level Input HIGH Current 3-level input pins VIN = VCC – 200 µA IIMM Three Level Input MID Current 3-level input pins VIN = VCC/2 –50 50 µA IILL Three Level Input LOW Current 3-level input pins VIN = GND –200 – µA 400 VCC mV LVDIFF Input Pins (REF[A:B]±) VDIFF Input Differential Voltage VIHHP Highest Input HIGH Voltage 1.0 VCC V VILLP Lowest Input LOW Voltage GND VCC – 0.4 V VCOM Common Mode Range (crossing voltage) 0.8 VCC V Note: 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. Document #: 38-07271 Rev. *B Page 4 of 9 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions Min. Max. Unit – 200 mA – 200 mA – 40 mA – 50 mA Operating Current ICCI Internal Operating Current Output Current Dissipation/Pair[6] ICCN VCC = Max., fMAX[5] CY7B9930V CY7B9940V CY7B9930V VCC = Max., CLOAD = 25 pF, RLOAD = 50Ω at VCC/2, fMAX CY7B9940V Capacitance Parameter CIN Description Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Input Capacitance Min. Max. Unit – 5 pF Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11] CY7B9930/40V-2 CY7B9930/40V-5 Min. Max. Min. Max. Unit fin Parameter Clock Input Frequency Description CY7B9930V 12 100 12 100 MHz CY7B9940V 24 200 24 200 MHz fout Clock Output Frequency CY7B9930V 12 100 12 100 MHz CY7B9940V 24 200 24 200 MHz tSKEWPR Matched-Pair Skew[12, 13] – 185 – 185 ps Skew[12, 13] tSKEWBNK Intrabank – 200 – 250 ps tSKEW0 Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[12, 13] – 250 – 550 ps tSKEW1 Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[12, 13] – 250 – 650 ps tCCJ1-3 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) – 150 – 150 ps PeakPeak tCCJ4-12 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) – 100 – 100 ps PeakPeak tPD Propagation Delay, REF to FB Rise –250 250 –500 500 ps – 200 200 ps 2.0 – – ns [14] tPDDELTA Propagation Delay difference between two devices tREFpwh REF input (Pulse Width HIGH)[15] tREFpwl REF input (Pulse Width LOW)[15] tr/tf Output Rise/Fall Time[16] tLOCK PLL Lock Time From Power-up tRELOCK1 PLL Re-Lock Time (from same frequency, different phase) with Stable Power Supply 2.0 2.0 – 2.0 – ns 0.15 2.0 0.15 2.0 ns – 10 – 10 ms – 500 – 500 µs Notes: 5. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B9930V, fNOM = 200 MHz for CY7B9940V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50Ω at VCC/2. 7. This is for non-three level inputs. 8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF. 9. Both outputs of pair must be terminated, even if only one is being used. 10. Each package must be properly decoupled. 11. AC parameters are measured at 1.5V, unless otherwise indicated. 12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω. 13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 15. Tested initially and after any design or process changes that may affect these parameters. 16. Rise and fall times are measured between 2.0V and 0.8V. Document #: 38-07271 Rev. *B Page 5 of 9 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11] (continued) CY7B9930/40V-2 CY7B9930/40V-5 Parameter Description Min. Max. Min. Max. Unit tRELOCK2 PLL Re-Lock Time (from different frequency, different phase) with Stable Power Supply[17] – 1000 – 1000 µs tODCV Output duty cycle deviation from 50%[11] –1.0 1.0 –1.0 1.0 ns tPWH Output HIGH time deviation from 50%[18] – 1.5 – 1.5 ns tPWL Output LOW time deviation from 50%[18] – 2.0 – 2.0 ns tPDEV Period deviation when changing from reference to reference[19] – 0.025 – 0.025 UI 1.0 10 1.0 10 ns 0.5 14 0.5 14 ns ACTIVE[12, 20] tOAZ DIS[1:2] HIGH to output high-impedance from tOZA DIS[1:2] LOW to output ACTIVE from output is high-impedance[20, 21] AC Test Loads and Waveform[22] 3.3V R1 OUTPUT For all other outputs R1 = 100Ω CL R2 = 100Ω CL < 25 pF up to 185 MHz 10 pF from 185 to 200 MHz (Includes fixture and probe capacitance) For LOCK output only R1 = 910Ω R2 = 910 Ω CL < 30 pF R2 (a) LVTTL AC Test Load 3.3V 2.0V 0.8V GND < 1 ns 2.0V 0.8V < 1 ns (b) TTL Input Test Waveform Notes: 17. fNOM must be within the frequency range defined by the same FS state. 18. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 19. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period. 20. Measured at 0.5V deviation from starting voltage. 21. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 18 MHz, 10 pF from 185 to 200 MHz. 22. These figures are for illustration only. The actual ATE loads may vary. Document #: 38-07271 Rev. *B Page 6 of 9 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V AC Timing Diagrams[11] tREFpwl QFA0 or [1:4]Q[A:B]0 tREFpwh REF t SKEWPR t SKEWPR t PWH tPD t PWL QFA1 or [1:4]Q[A:B]1 2.0V FB 0.8V tCCJ1-3,4-12 Q [1:4]QA[0:1] t SKEWBNK t SKEWBNK [1:4]QB[0:1] REF TO DEVICE 1 and 2 tODCV tODCV tPD Q FB DEVICE1 tPDELTA t SKEW0,1 tPDELTA t SKEW0,1 Other Q FB DEVICE2 Ordering Information Propagation Delay (ps) Max. Speed (MHz) 500 100 CY7B9930V-5AC A44 44-Lead Thin Quad Flat Pack Commercial 500 100 CY7B9930V-5AI A44 44-Lead Thin Quad Flat Pack Industrial 500 200 CY7B9940V-5AC A44 44-Lead Thin Quad Flat Pack Commercial Ordering Code Package Name Package Type Operating Range 500 200 CY7B9940V-5AI A44 44-Lead Thin Quad Flat Pack Industrial 250 100 CY7B9930V-2AC A44 44-Lead Thin Quad Flat Pack 250 200 CY7B9940V-2AC A44 44-Lead Thin Quad Flat Pack 250 100 CY7B9930V-2AI A44 44-Lead Thin Quad Flat Pack 250 200 CY7B9940V-2AI A44 44-Lead Thin Quad Flat Pack Document #: 38-07271 Rev. *B Commercial Industrial Page 7 of 9 [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-*B RoboClockII is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07271 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. [+] Feedback RoboClockII™ Junior CY7B9930V CY7B9940V Document History Page Document Title: CY7B9930V/CY7B9940V RoboClockII™ Junior High-Speed Multi-Frequency PLL Clock Buffer Document Number: 38-07271 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110536 12/02/01 SZV Change from Spec number: 38-01141 *A 115109 7/03/02 HWT Add 44TQFP package for both CY7B9930/40V – Industrial Operating Range *B 128463 7/29/03 RGL Added clock input frequency (fin) specifications in the switching characteristics table. Added Min. values for the clock output frequency (fout) in the switching characteristics table. Document #: 38-07271 Rev. *B Page 9 of 9 [+] Feedback