IN74LV374 OCTAL D-TYPE FLIP-FLOP POSITIVE EDGETRIGGER (3-STATE) • • • • • • IN74LV374 are compatible by pinning with KP555ИР23, КР1533ИР13, IN74HC374A and IN74HCT374A series. Input voltage levels are compatible with standard CMOS levels. Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS. Supply voltage range from 2.0 to 3.2 V LOW input current: 1.0 µА; 0.1 µА at Т = 25 °С Output current 8 mА Latch current value not less than 150 mА at Т = 125 °С ESD acceptable values: not less than 2000 V as per HBM, and not less than 200 V as per MM ORDERING INFORMATION IN74LV374N Plastic DIP IN74LV374D SOIC TA = -40° to 125° C for all packages BLOCK DIAGRAM PIN ASSIGNMENT D0 D1 D2 D3 D4 D5 D6 D7 CP OE 03 02 04 05 07 06 08 09 13 12 14 15 17 16 18 19 Q0 OE VCC 01 20 Q0 02 19 Q7 D0 03 18 D7 Q3 D1 04 17 D6 Q4 Q1 05 16 Q6 Q2 06 15 Q5 Q1 Q2 Q5 374 D2 07 14 D5 Q6 D3 08 13 D4 Q7 Q3 09 12 Q4 GND 10 11 11 CP 01 Pin 20=VCC Pin 10 = GND OE L L L H 1 FUNCTION TABLE Inputs Output CP Dn Qn H H L L L, H, X no change X X Z IN74LV374 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Rating Unit VCC Supply voltage -0.5 to +5.0 V 1 IIK * Input diode current mА ±20 IOK *2 Output diode current mА ±50 IO *3 Output source or sink current mА ±35 ICC Bus driver outputs mА ±70 IGND Ground current mА ±70 mW PD Power dissipation per package, Plastic DIP *4 750 500 SOIC *4 Tstg Storage temperature range -65 to +150 °C * In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the absolute maximum ratings functioning is guaranteed at the recommended operating conditions. *1 Provide VI < -0.5 V or VI > VCC + 0.5 V. *2 Provide VO < -0.5 V or VO > VCC + 0.5 V. *3 Provide -0.5 V < VO < VCC + 0.5 V. *4 When operating in the temperature range of 70°C to 125°C power dissipation value decreases - for Plastic DIP by 12 mW/°C - for SOIC by 8 mW/°C RECOMMENDED OPERATING MODES Symbol Parameter Min Max Unit VCC Supply voltage 1.2 3.6 V VIN Input voltage 0 VCC V VOUT Output voltage 0 VCC V TA Operating ambient temperature range. -40 125 °C For all types packages ns tLH, tHL Input rise and fall times VCC =1.2 V 0 1000 VCC =2.0 V 700 500 VCC =3.0 V 400 VCC =3.6 V 2 IN74LV374 DC CHARACTERISTICS Symbol Parameter Test coditions VIH HIGH level VO = input voltage 0.1 V VIL LOW level input voltage VOH HIGH level output voltage VOL II IOZ ICC LOW level output voltage Input leakage current Output OFFstate current Suply current VCC, V 25°C min ma x 0.9 1.4 2.1 2.5 0.3 0.6 0.9 1.1 1.1 1.92 2.92 3.52 2.48 - VCC- 1.2 2.0 3.0 3.6 VO =0.1 V 1.2 2.0 3.0 3.6 VI = VIH or VIL 1.2 2.0 IO = -50 µА 3.0 3.6 VI = VIH or VIL 3.0 IO = -8 mА VI = VIH or VIL 1.2 2.0 IO = 50 µА 3.0 3.6 VI = VIH or VIL 3.0 IO = 8 mА VI = VCC или 3.6 0V 3.6 3-state outputs VI = VIL or VIH VO =VCC or 0V VI =VCC or 3.6 0V IO = 0 µА 3 Limits -40°C to 125°C 85°C min ma min ma x x 0.9 0.9 1.4 1.4 2.1 2.1 2.5 2.5 0.3 0.3 0.6 0.6 0.9 0.9 1.1 1.1 1.0 1.0 1.9 1.9 2.9 2.9 3.5 3.5 2.34 - 2.20 - Unit V V V V V - 0.09 0.09 0.09 0.09 0.33 - 0.1 0.1 0.1 0.1 0.4 - 0.1 0.1 0.1 0.1 0.5 V - ±0.1 - ±1.0 - ±1.0 µА - ±0.5 - ±5 - ±10 µА - 8.0 - 80 - 160 µА IN74LV374 AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns) Test VCC, Symbol Parameter conditions V 25°C tPHL, tPLH from CP to Qn tPHZ tPLZ from OE to Qn tPZH tPZL from OE to Qn tTHL, tTLH tW tSU Propagation delay Figure 1 Propagation delay Figure 3 Propagation delay Figure 3 HIGH-to-LOW Figure 1 and LOW-toHIGH transition time Clock pulse Figure 1 width HIGH or LOW Set-up time Figure 2 Dn to CP 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 min ma x - 180 45 27 - 160 38 25 - 160 38 23 75 16 10 - 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 2.0 3.0 250 18 11 45 13 8 25 5 5 - 27 46 350 23 14 50 17 10 25 5 5 - 22 37 540 28 17 100 20 12 25 5 5 - 18 31 - 7 - - - - - 34 - - - - tH Hold time Dn Figure 2 to CP fc CP naximum Figure 1 pulse frequency Input 3.0 capacitance VI = 0 V or 3.0 Power dissipation VCC capacitance (per flip-flop) CI CPD Limits -40°C to 125°C 85°C min ma min ma x x - 230 - 270 68 56 41 34 - 200 - 240 68 57 43 36 - 200 - 240 58 48 35 29 - 100 - 120 24 20 15 13 - 4 Unit ns MHz pF IN74LV374 tLH VCC 0.9 V1 V1 CP V1 tW 0.1 GND 1/fc tPH tPL L H 0.9 0.9 V1 V1 Qn 0.1 tTHL tTLH 0.1 0V V1 = 0.5VCC Figure 1- Time diagram VCC V1 Dn t SU V1 V1 tH t SU V1 tH GND VCC CP V1 V1 GND V1 = 0.5V CC Figure 2 - Time diagram 5 IN74LV374 tLH tHL 0.9 OE VCC 0.9 V1 V1 0.1 0.1 tPZ 0.9 H VOH tPH V1 Qn GND Z 0V tPLZ Qn VCC V1 tPZL 0.1 VOL V1 = 0.5VCC Figure 3 - Time diagram 6 IN74LV374 Drawing of the chip 1.66 mm 18 17 16 15 14 1.68 mm 19 13 12 20 11 74LV373/374 1 2 3 10 On-chip marking 4 5 6 9 7 Pads allocation Table Pad coordinates (counted from lower left corner), number mm X Y 01 0.142 0.628 02 0.142 0.377 03 0.142 0.125 04 0.498 0.125 05 0.693 0.125 06 0.871 0.125 07 1.095 0.125 08 1.423 0.130 09 1.423 0.329 10 1.423 0.587 11 1.423 0.949 12 1.423 1.198 13 1.423 1.447 14 1.085 1.447 15 0.868 1.447 16 0.696 1.447 17 0.461 1.447 18 0.142 1.447 19 0.142 1.245 20 0.142 0.997 7 8 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108