Data Sheet No.PD94724 IR3638SPbF HIGH FREQUENCY SYNCHRONOUS PWM BUCK CONTROLLER FOR TRACKING APPLIACTIONS Features Description • • • • • • The IR3638 controller IC is designed to provide a simple synchronous Buck regulator for on-board DC to DC applications in a 14-pin SOIC. The IR3638 is designed specifically for tracking applications by providing the track input. The IR3638 operates at a fixed internal 400kHz switching frequency allowing the use of small external components. The device features a programmable soft start set by an external capacitor, under-voltage lockout and output under-voltage detection that latches off the device when an output short is detected. Power up Sequencing / Tracking Enable Input Internal 400kHz Oscillator Programmable Soft-Start Fixed Frequency Voltage Mode Output Voltage as low as 0.6V Applications • • • • • Tracking Applications Game Consoles Computing Peripheral Voltage Regulators Graphics Cards General DC/DC Converters 12V 5V C3 C2 C1 Vc Vcc Q1 HDrv V_CPUCore LDrv SS L1 D1 Vp / Enable Vout C7 Q2 PGnd C6 R1 Fb Comp C4 Gnd R2 C5 R3 Fig. 1: Typical Application Circuit ORDERING INFORMATION PKG PACKAGE DESIG DESCRIPTION S IR3638STRPbF 3/19/07 PIN PARTS PARTS COUNT PER TUBE PER REEL 14 ---2500 T&R ORIANTAION Figure A IR3638SPbF ABSOLUTE MAXIMUM RATINGS Caution: Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. (Voltages referenced to GND) • Vcc Supply Voltage ................................................… -0.5V to 16V • Vc Supply Voltage …………………………………… -0.5V to 25V • Storage Temperature Range ..................................... -65°C To 150°C • Operating Junction Temperature Range ................... 0°C To 150°C • ESD Classification …………………………………..… JEDEC, JESD22-A114 • Moisture Sensitivity Level ……………………………. JEDEC Level 2 @ 260oC Package Information Fb 1 14 NC VP 2 13 SS NC 3 12 Comp Vcc 4 11 NC NC 5 10 Vc LDrv 6 9 HDrv Gnd 7 8 PGnd 14-Pin SOIC NB (S) ΘJA = 88o C/W 3/19/07 2 IR3638SPbF Block Diagram 250mV Vcc 4 4.25V POR 50mV 10 Vc 0.65V 3V Ramp 22uA Oscillator 9 HDrv S SS 13 POR Q Error Comp 64uA Vcc R Reset Dom VP 2 Fb 1 Comp 12 25K 25K 6 LDrv Error Amp 0.4V FbLo Comp POR 8 PGnd 2V 7 Gnd SS Pre-Bias Comparator Fig. 2: Simplified block diagram of the IR3638 3/19/07 3 IR3638SPbF Pin Description Pin Name Description 1 Fb 2 Vp / Enable 3 4 NC Vcc 5 6 NC LDrv Inverting input to the error amplifier. This pin is connected to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Dual function pin. Non inverting input to the error amplifier. Enable input. No Connect This pin provides power for the internal blocks of the IC as well as powers the low side driver. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to power ground. No Connect Output driver for low side MOSFET. 7 Gnd IC ground for internal control circuitry. 8 PGnd Power Ground. This pin serves as a separate ground for the MOSFET drivers and should be connected to the system’s power ground plane. 9 HDrv 10 Vc Output driver for high side MOSFET. The negative voltage at this pin may cause instability for the gate drive circuit. To prevent this, a low forward voltage drop diode (e.g. BAT54 or 1N4148) is required between this pin and Power Ground. This pin powers the high side driver. 11 NC No Connect 12 Comp 13 SS 14 NC 3/19/07 Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. Soft start. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to ground to set the start up time of the output voltage. No Connect 4 IR3638SPbF Recommended Operating Conditions Symbol Definition Vcc Vc Tj Supply Voltage Supply Voltage Junction Temperature Min Max Units 5 Converter Voltage + 5V 0 13.2 20 125 V V o C Electrical Specifications Unless otherwise specified, these specification apply over Vcc=Vc=12V, 0oC<Tj< 125oC Parameter SYM Test Condition Min TYP MAX Units Supply Current VCC Supply Current (Static) VCC Supply Current (Dynamic) VC Supply Current (Static) VC Supply Current (Dynamic) ICC(Static) Enable=0V, No Switching 6.5 10 mA ICC(Dynamic) Fs=400kHz, CLOAD=1.5nF 15 25 mA IC(Static) Enable=0V, No Switching 3.3 10 mA IC(Dynamic) Fs=400kHz, CLOAD=1.5nF 13 20 mA 4.0 3.8 0.2 0.6 0.56 25 0.3 4.25 4.0 0.25 0.65 0.6 42.5 0.4 4.5 4.2 0.35 0.7 0.66 60 0.5 V mV V 360 400 440 kHz Under Voltage Lockout Vcc-Start-Threshold Vcc-Stop-Threshold Vcc-Hysteresis Enable-Start-Threshold Enable-Stop-Threshold Enable-Hysteresis Fb_UVLO Vcc UVLO(R) Vcc UVLO(F) Vcc(Hyst) En UVLO (R) En UVLO (F) En(Hyst) Fb_UVLO Supply ramping up Supply ramping down Supply ramping up and down Supply ramping up Supply ramping down Supply ramping up and down Fb ramping down V V Oscillator Frequency FS Ramp Amplitude Vramp Note1 Min Duty Cycle Dmin Fb=1V, Vp=0.8V Max Duty Cycle Dmax Fs=400kHz, Fb=0.6V, Vp=0.8V Fb Input Bias Current IFB1 Fb Input Bias current 1.25 V 0 % 85 95 % SS=3V -0.1 -0.5 μA IFB2 SS=0V 64 Vp Input Bias Current Ivp SS=3V -0.1 Transconductance gm Input Offset Voltage Vos 81 Error Amplifier Vp Common Mode Range 440 Vp=0.8V Vcomn -6 0.6 0 uA -0.5 uA 1300 μmho +6 mV 1.5 V Note1: Guaranteed by Design but not tested in production. 3/19/07 5 IR3638SPbF Electrical Specifications Unless otherwise specified, these specification apply over Vcc=Vc=12V, 0oC<Tj< 125oC Parameter SYM Test Condition Min TYP MAX Units 12 22 32 μA 1.8 2 2.2 V Soft Start Soft Start Current ISS SS=0V Soft Start Turn On SS (on) Output Drivers LO, Drive Rise Time Tr(Lo) CL=1.5nF, See Fig 3 30 60 ns HI Drive Rise Time Tr(Hi) CL=1.5nF, See Fig 3 30 60 ns LO Drive Fall Time Tf(Lo) CL=1.5nF, See Fig 3 30 60 ns HI Drive Fall Time Tf(Hi) CL=1.5nF, See Fig 3 30 60 ns Dead Band Time Tdead See Fig 3 90 150 ns Tr 35 Tf 9V High Side Driver (HDrv) 2V Tr Tf 9V Low Side Driver (LDrv) 2V Deadband H_to_L Deadband L_to_H Fig. 3: Definition of Rise/Fall time and Deadband Time 3/19/07 6 IR3638SPbF Circuit Description THEORY OF OPEARTION Introduction Error Amplifier The IR3638 is a voltage mode PWM synchronous controller and operates with a fixed 400kHz switching frequency, allowing the use of small external components. The output voltage is set by feedback pin (Fb) and the external reference voltage (Vp). These are two inputs to error amplifier. The error signal between these two inputs is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle (D) which drivers N-channel external MOSFETs. The IR3638 is a voltage mode controller. The error amplifier is of transconductance type and it is capable of operating with Type III compensation control scheme using low ESR output capacitance. The timing of the IC is controlled by an internal oscillator circuit that uses on-chip capacitor to set the switching frequency. Short Circuit Protection The output is protected against the short-circuit. The IR3638 protects the circuit for shorted output by sensing the output voltage (through the external resistor divider). The device shuts down the PWM signals and latches off when the output voltage drops below 0.4V. Start Up / Down Considerations Under-Voltage Lockout The under-voltage lockout circuit monitors the Vcc and Enable input and assures that the MOSFET driver outputs remain in the off state whenever the Vcc or Enable voltages drop below set thresholds. Pre-Bias Startup IR3638 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the soft start reaches about 2.0V. Figure 4 shows a typical Pre-Bias condition at start up. Depends on system configuration, specific amount of output capacitors may be required to prevent discharging the output voltage. The “Typical Application” on page1 shows a standard configuration where multiple input supplies are available. This configuration minimizes the required extra components compared with a single input supply configuration. As it is shown the converter voltage (Bus Voltage) is set to 5V while the IC including the gate driver voltage are biased with 12V supply. In order to maintain a proper start up, it is required that the Bus Voltage ramps up first followed by Vcc, Vc supply. The system will be enabled when the Vp voltage passes the under voltage lock out threshold. Figure 5 shows start up / down sequencing. 5V Bus Voltage V Vo 12V (Vcc, Vc) 0.65V Pre-Bias Voltage (Output Voltage before startup) 0.60V V_CPUCore (Vp of IR3638) POR of IR3638 Time SS (IR3638) Fig. 4: Pre-Bias start up Vout Fig. 5: Start Up / Down Sequence (Refer to Figure1) 3/19/07 7 IR3638SPbF Soft-Start The IR3638 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. To ensure correct start-up, the soft-start sequence initiates when Vcc and Enable rise above their threshold and generate the Power On Ready (POR) signal. The soft-start function operates by sourcing current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the output of error amplifier by injecting a current (64uA) into the Fb pin and generates a voltage about 1.6V (64ux25K) across the negative input of error amplifier (see figure 6). The magnitude of the injected current is inversely proportional to the voltage at the soft-start pin. As the soft-start voltage ramps up, the injected current decreases linearly and so does the voltage at negative input of error amplifier. When the soft-start capacitor is around 1V, the voltage at the negative input of the error amplifier is approximately 0.8V (32uAx25K). As soon as the Fb reaches the Vp voltage, the output of error amplifier will start increasing and generating the first PWM signal. As the soft-start capacitor voltage continues to ramp up, the current flowing into the Fb pin will keep decreasing. The feedback voltage increases linearly as the soft start voltage ramps up. When soft-start voltage is around 2V the output voltage is reached the steady state and the injected current is zero. 3V 22uA SS/SD 64uA POR Comp 25K 25K Fb Fig. 6: Soft-Start circuit for IR3638 Output of UVLO POR 3V ≅2V ≅1V Soft-Start Voltage Current flowing into Fb pin 0V 64uA 0uA Voltage at negative input ≅1.6V of Error Amp Figure 7 shows the theoretical operational waveforms during soft-start. The output voltage start-up time is the time period when soft-start capacitor voltage increases from 1V to 2V. The start-up time will be dependent on the size of the external soft-start capacitor and can be estimate by: T 22μA ∗ start = 2V −1V Css Error Amp Vp 0.8V Vp=0.8V Voltage at Fb pin 0V Fig. 7: Theoretical operation waveforms during soft-start For a given start-up time, the soft-start capacitor (nF) can be estimated as: CSS ≅ 22μA * Tstart (ms) 3/19/07 --(1) 8 IR3638SPbF Application Information Soft-Start Programming Design Example: The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: The following is a design of typical application for IR3638. The application circuit is shown on page 14. Vin = 5V CSS ≅ 22μA * Tstart --(1) Where Tstart is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1uF. Choose a ceramic capacitor at 0.1uF. Vcc = Vc = 12V Vp = 1V Vo = 1.2V Io = 6 A Input Capacitor Selection ΔVo ≤ 30 mV Output Voltage Programming Output voltage is programmed by Vp voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is externally referenced to Vp. The divider is set to provide a voltage equal to Vp (in this case 1V) when the output is at its desired value. The output voltage is defined by using the following equation: ⎛ R ⎞ Vo = Vp ∗ ⎜⎜1 + 1 ⎟⎟ --( 2 ) R2 ⎠ ⎝ When an external resistor divider is connected to the output as shown in figure 8. The input filter capacitor should be selected based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of upper MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: IRMS = Io ∗ D ∗ (1 − D ) Where: --(4 ) D= Vo Vin D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=6A and D=0.24, the IRMS=2.6A. VOUT IR3638 R1 Fb R2 Fig. 8: Typical application of the IR3638 for programming the output voltage Equation (2) can be rewritten as: ⎛ Vp ⎞ ⎟ R2 = R1 ∗ ⎜⎜ ⎟ ⎝ V O−Vp ⎠ --( 3 ) Select R1 =1kOhm, this will result in R2=5kOhm. Ceramic capacitors are recommended due to their peak current capabilities, they also feature low ESR and ESL at higher frequency which enhance better efficiency, Use two 10uF, 16V ceramic capacitor from Panasonic. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( Δi ) . The optimum point is usually found between 20% and 50% ripple of the output current. Select the closest Standard value of 4.99kOhm. 3/19/07 9 IR3638SPbF Inductor Selection (Cont..) For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Vin − Vo = L ∗ It is recommended to select output capacitor with low enough ESR to meet output voltage ripple and step load transient requirements. Δi 1 ; Δt = D ∗ Fs Δt PosCap capacitors offer low ESR with large storage capacity per unit volume. These capacitors offer a cost effective output capacitor solution. Vo Vin ∗ Δi * Fs Sanyo 2R5TPF470M (2.5V, 470uF, 10mOhm) is selected for this design. L = (Vin − Vo ) ∗ --(5 ) Equation (6) can be used to calculate the required ESR for the specific voltage ripple. Vin = Maximum input voltage Vo = Output Voltage Δi = Inductor ripple current One Capacitor would meet the voltage ripple requirement. F s= Switching frequency Power MOSFET Selection Δt = Turn on time D = Duty cycle If Δi ≈ 40%(Io ) , then the output inductor will be: L = 0.95uH The coilcraft DO3316H-102ML (1uH, 6mOhm) is suitable for this application. 10A, Output Capacitor Selection The voltage ripple and transient requirements determines the output capacitors types and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components, these components can be described as: ΔVo = ΔVo(ESR) + ΔVo(ESL) + ΔVo(C ) The IR3638 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gate-source drive voltage (Vgs), maximum output current, On-resistance RDS(on) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (Vin). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low Vgs to prevent undesired turn-on of the complementary MOSFET, which results a shootthrough current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: 2 Pcond = (upper switch)= Iload ∗ Rds(on) ∗ D ∗ ϑ ΔVo(ESR) = ΔIL * ESR - -(6) 2 Pcond = (lower switch)= Iload ∗ Rds(on) ∗ (1 − D) ∗ϑ ϑ = Rds(on) temperature dependency ⎛Vin ⎞ ⎟ * ESL ⎝L⎠ ΔVo(ESL) = ⎜ ΔVo(C ) = ΔIL 8 * Co * Fs ΔVo = Output voltage ripple ΔIL = Inductor ripple current 3/19/07 The RDS(on) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. For this design, IRF8910 is a good choice. The device provides two N-MOSFETs in a compact SO-8 package. 10 IR3638SPbF Power MOSFET Selection (Cont..) Feedback Compensation The IRF8910 has the following data: The IR3638 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). Vds = 20V, Id = 10A Rds(on) = 13.4mΩ @Vgs = 10V The conduction losses will be: Pcon=0.724W The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: The output LC filter introduces a double pole, – 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 10). The resonant frequency of the LC filter expressed as follows: FLC = 1 - - - (8) 2 ∗ π Lo ∗ Co Figure 10 shows gain and phase of the LC filter. Since we already have 180o phase shift just from the output filter, the system risks being unstable. V t +t Psw = ds(off ) * r f * Iload - - - (7) T 2 Where: V ds(off) = Drain to source voltage at the off time tr = Rise time tf = Fall time T = Switching period Iload = Load current The switching time waveforms is shown in figure9. VDS 90% Gain Phase 0 0dB -40dB/decade FLC Frequency -180 FLC Frequency Fig. 10: Gain and Phase of LC filter The IR3638’s error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control and AC phase compensation. 10% VGS td(ON) tr td(OFF) tf Fig. 9: switching time waveforms From IRF8910 data sheet: tr = 10ns, tf = 4.1ns These values are taken under a certain condition test. For more details please refer to the IRF8910 data sheet. By using equation (7), we can calculate the switching losses. Psw=0.37W 3/19/07 The error amplifier can be compensated either in type II or typeIII compensation. When it is used in typeII compensation the transconductance properties of the error amplifier become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in figure 11. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. 11 IR3638SPbF The ESR zero of the output capacitor expressed as follows: 1 FESR = - - - (9) 2 ∗ π * ESR * Co VOUT R1 Fb To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz = 75%FLC Fz = 0.75 * - - - (14) Using equations (15) and (16) to calculate C9. E/A R2 Comp Ve C4 VREF R3 CPOLE Gain(dB) One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: H(s) dB FP = FZ Frequency The transfer function (Ve/Vo) is given by: ⎛ R9 ⎞ 1 + sR3C4 ⎟* H(s) = ⎜⎜ gm * - - - (10) R9 + R8 ⎟⎠ sC4 ⎝ The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: [H(s)] = ⎛⎜⎜ g ⎝ m * R9 ⎞ ⎟ * R3 - - - (11) R9 + R8 ⎟⎠ 1 2π * R3 * C4 1 C *C 2π * R3 * 4 POLE C4 + CPOLE The pole sets to one half of switching frequency which results in the capacitor CPOLE: Fig. 11: TypeII compensation network and its asymptotic gain plot Fz = 1 2π Lo * Co - - - (12) The gain is determined by the voltage divider and error amplifier’s transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs CPOLE = 1 1 π * R3 * Fs − C4 For FP << ≅ 1 π * R3 * Fs - - - (15) Fs 2 Based on the frequency of the zero generated by output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency. Compensator type FESR vs. Fo Output capacitor TypII(PI) FLC<FESR<Fo<Fs/2 Electrolytic , Tantalum TypeIII(PID) Method A FLC<Fo<FESR<Fs/2 Tantalum, ceramic TypeIII(PID) Method B FLC<Fo<Fs/2<FESR Ceramic Use the following equation to calculate R3: R3 = Vosc * Fo * FESR * (R1 + R2 ) Vin * FLC2 * R2 * gm - - - (13) Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R1 and R2 = Feedback Resistor Dividers gm = Error Amplifier Transconductance 3/19/07 Table1- The compensation type and location of FESR versus Fo The details of these compensation types are discussed in application note AN-1043 which can be downloaded from IR Web-Site. 12 IR3638SPbF For this design we have: Vin=5V Vo=1.2V Vosc=1.25V Vp=1.0V gm=450umoh Lo=1.0uH Co=1x470uF, ESR=10mOhm Fs=400kHz These result to: FLC=7.3kHz FESR=33.8kHz Fs/2=200kHz Select crossover frequency: Fo=40kHz Since: FLC<FESR<Fo<Fs/2, typeII compensation is selected to place the poles and zeros. Using equations 12, 13 and 15 will result to the following compensation values: R3 = Vosc * Fo * FESR * (R1 + R2 ) Vin * FLC2 * R2 * gm - - - (13) R3 = 16.76K, Select R3 = 16.2K Fz = 1 2π * R3 * C4 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc and Vc should be close to respective pins. It is important to place the feedback components include feedback resistors and compensation components close to Fb and Comp pins. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. - - - (12) C4 = 1.78nF, Select C4 = 1.8nF CPOLE ≅ 1 π * R3 * Fs - - - (15) CPOLE = 49 pF , Select CPOLE ≤ 22 pF 3/19/07 13 IR3638SPbF 12V 5V C2=1uF C1=1uF Q=IRF8910 Vc Vcc C3=2x22uF (ceramic) HDrv External Supply 1V D1 Vp / Enable L1 C7=1x470uF, 10mOhm (PosCap) LDrv SS PGnd C6=0.1uF Vout=1.2V @ 6A DO3316H-102ML R1=1K Fb Comp C4=1.8nF Gnd R2=4.99K C5=22pF R3=16.2K Fig.16: Application circuit for 5V to 1.2V @ 6A 3/19/07 14 IR3638SPbF 1 1 1 Figure A IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 5/31/2007 3/19/07 15